mcxa_pac/scg0/
spllmdiv.rs

1#[doc = "Register `SPLLMDIV` reader"]
2pub type R = crate::R<SpllmdivSpec>;
3#[doc = "Register `SPLLMDIV` writer"]
4pub type W = crate::W<SpllmdivSpec>;
5#[doc = "Field `MDIV` reader - Feedback divider ratio (M-divider)."]
6pub type MdivR = crate::FieldReader<u16>;
7#[doc = "Field `MDIV` writer - Feedback divider ratio (M-divider)."]
8pub type MdivW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Feedback ratio change request.\n\nValue on reset: 0"]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum Mreq {
13    #[doc = "0: Feedback ratio change is not requested"]
14    Disabled = 0,
15    #[doc = "1: Feedback ratio change is requested"]
16    Enabled = 1,
17}
18impl From<Mreq> for bool {
19    #[inline(always)]
20    fn from(variant: Mreq) -> Self {
21        variant as u8 != 0
22    }
23}
24#[doc = "Field `MREQ` reader - Feedback ratio change request."]
25pub type MreqR = crate::BitReader<Mreq>;
26impl MreqR {
27    #[doc = "Get enumerated values variant"]
28    #[inline(always)]
29    pub const fn variant(&self) -> Mreq {
30        match self.bits {
31            false => Mreq::Disabled,
32            true => Mreq::Enabled,
33        }
34    }
35    #[doc = "Feedback ratio change is not requested"]
36    #[inline(always)]
37    pub fn is_disabled(&self) -> bool {
38        *self == Mreq::Disabled
39    }
40    #[doc = "Feedback ratio change is requested"]
41    #[inline(always)]
42    pub fn is_enabled(&self) -> bool {
43        *self == Mreq::Enabled
44    }
45}
46#[doc = "Field `MREQ` writer - Feedback ratio change request."]
47pub type MreqW<'a, REG> = crate::BitWriter<'a, REG, Mreq>;
48impl<'a, REG> MreqW<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51{
52    #[doc = "Feedback ratio change is not requested"]
53    #[inline(always)]
54    pub fn disabled(self) -> &'a mut crate::W<REG> {
55        self.variant(Mreq::Disabled)
56    }
57    #[doc = "Feedback ratio change is requested"]
58    #[inline(always)]
59    pub fn enabled(self) -> &'a mut crate::W<REG> {
60        self.variant(Mreq::Enabled)
61    }
62}
63impl R {
64    #[doc = "Bits 0:15 - Feedback divider ratio (M-divider)."]
65    #[inline(always)]
66    pub fn mdiv(&self) -> MdivR {
67        MdivR::new((self.bits & 0xffff) as u16)
68    }
69    #[doc = "Bit 31 - Feedback ratio change request."]
70    #[inline(always)]
71    pub fn mreq(&self) -> MreqR {
72        MreqR::new(((self.bits >> 31) & 1) != 0)
73    }
74}
75#[cfg(feature = "debug")]
76impl core::fmt::Debug for R {
77    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
78        f.debug_struct("SPLLMDIV")
79            .field("mdiv", &self.mdiv())
80            .field("mreq", &self.mreq())
81            .finish()
82    }
83}
84impl W {
85    #[doc = "Bits 0:15 - Feedback divider ratio (M-divider)."]
86    #[inline(always)]
87    pub fn mdiv(&mut self) -> MdivW<'_, SpllmdivSpec> {
88        MdivW::new(self, 0)
89    }
90    #[doc = "Bit 31 - Feedback ratio change request."]
91    #[inline(always)]
92    pub fn mreq(&mut self) -> MreqW<'_, SpllmdivSpec> {
93        MreqW::new(self, 31)
94    }
95}
96#[doc = "SPLL M Divider Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spllmdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spllmdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
97pub struct SpllmdivSpec;
98impl crate::RegisterSpec for SpllmdivSpec {
99    type Ux = u32;
100}
101#[doc = "`read()` method returns [`spllmdiv::R`](R) reader structure"]
102impl crate::Readable for SpllmdivSpec {}
103#[doc = "`write(|w| ..)` method takes [`spllmdiv::W`](W) writer structure"]
104impl crate::Writable for SpllmdivSpec {
105    type Safety = crate::Unsafe;
106}
107#[doc = "`reset()` method sets SPLLMDIV to value 0x01"]
108impl crate::Resettable for SpllmdivSpec {
109    const RESET_VALUE: u32 = 0x01;
110}
mcxa_pac/scg0/spllmdiv.rs

mcxa_pac/scg0/
spllmdiv.rs
