mcxa_pac/scg0/
sirctrim.rs

1#[doc = "Register `SIRCTRIM` reader"]
2pub type R = crate::R<SirctrimSpec>;
3#[doc = "Register `SIRCTRIM` writer"]
4pub type W = crate::W<SirctrimSpec>;
5#[doc = "Field `CCOTRIM` reader - CCO Trim"]
6pub type CcotrimR = crate::FieldReader;
7#[doc = "Field `CCOTRIM` writer - CCO Trim"]
8pub type CcotrimW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `CLTRIM` reader - CL Trim"]
10pub type CltrimR = crate::FieldReader;
11#[doc = "Field `CLTRIM` writer - CL Trim"]
12pub type CltrimW<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `TCTRIM` reader - Trim Temp"]
14pub type TctrimR = crate::FieldReader;
15#[doc = "Field `TCTRIM` writer - Trim Temp"]
16pub type TctrimW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
17#[doc = "Field `FVCHTRIM` reader - Calibrates the replica voltage in FSU for CCO to get well frequency at initial period"]
18pub type FvchtrimR = crate::FieldReader;
19#[doc = "Field `FVCHTRIM` writer - Calibrates the replica voltage in FSU for CCO to get well frequency at initial period"]
20pub type FvchtrimW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
21impl R {
22    #[doc = "Bits 0:5 - CCO Trim"]
23    #[inline(always)]
24    pub fn ccotrim(&self) -> CcotrimR {
25        CcotrimR::new((self.bits & 0x3f) as u8)
26    }
27    #[doc = "Bits 8:13 - CL Trim"]
28    #[inline(always)]
29    pub fn cltrim(&self) -> CltrimR {
30        CltrimR::new(((self.bits >> 8) & 0x3f) as u8)
31    }
32    #[doc = "Bits 16:20 - Trim Temp"]
33    #[inline(always)]
34    pub fn tctrim(&self) -> TctrimR {
35        TctrimR::new(((self.bits >> 16) & 0x1f) as u8)
36    }
37    #[doc = "Bits 24:28 - Calibrates the replica voltage in FSU for CCO to get well frequency at initial period"]
38    #[inline(always)]
39    pub fn fvchtrim(&self) -> FvchtrimR {
40        FvchtrimR::new(((self.bits >> 24) & 0x1f) as u8)
41    }
42}
43#[cfg(feature = "debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("SIRCTRIM")
47            .field("ccotrim", &self.ccotrim())
48            .field("cltrim", &self.cltrim())
49            .field("tctrim", &self.tctrim())
50            .field("fvchtrim", &self.fvchtrim())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:5 - CCO Trim"]
56    #[inline(always)]
57    pub fn ccotrim(&mut self) -> CcotrimW<'_, SirctrimSpec> {
58        CcotrimW::new(self, 0)
59    }
60    #[doc = "Bits 8:13 - CL Trim"]
61    #[inline(always)]
62    pub fn cltrim(&mut self) -> CltrimW<'_, SirctrimSpec> {
63        CltrimW::new(self, 8)
64    }
65    #[doc = "Bits 16:20 - Trim Temp"]
66    #[inline(always)]
67    pub fn tctrim(&mut self) -> TctrimW<'_, SirctrimSpec> {
68        TctrimW::new(self, 16)
69    }
70    #[doc = "Bits 24:28 - Calibrates the replica voltage in FSU for CCO to get well frequency at initial period"]
71    #[inline(always)]
72    pub fn fvchtrim(&mut self) -> FvchtrimW<'_, SirctrimSpec> {
73        FvchtrimW::new(self, 24)
74    }
75}
76#[doc = "SIRC Trim Register\n\nYou can [`read`](crate::Reg::read) this register and get [`sirctrim::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sirctrim::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct SirctrimSpec;
78impl crate::RegisterSpec for SirctrimSpec {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`sirctrim::R`](R) reader structure"]
82impl crate::Readable for SirctrimSpec {}
83#[doc = "`write(|w| ..)` method takes [`sirctrim::W`](W) writer structure"]
84impl crate::Writable for SirctrimSpec {
85    type Safety = crate::Unsafe;
86}
87#[doc = "`reset()` method sets SIRCTRIM to value 0"]
88impl crate::Resettable for SirctrimSpec {}
mcxa_pac/scg0/sirctrim.rs

mcxa_pac/scg0/
sirctrim.rs
