1#[doc = "Register `ROSCCSR` reader"]
2pub type R = crate::R<RosccsrSpec>;
3#[doc = "Register `ROSCCSR` writer"]
4pub type W = crate::W<RosccsrSpec>;
5#[doc = "Lock Register\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Lk {
9 #[doc = "0: Control Status Register can be written"]
10 WriteEnabled = 0,
11 #[doc = "1: Control Status Register cannot be written"]
12 WriteDisabled = 1,
13}
14impl From<Lk> for bool {
15 #[inline(always)]
16 fn from(variant: Lk) -> Self {
17 variant as u8 != 0
18 }
19}
20#[doc = "Field `LK` reader - Lock Register"]
21pub type LkR = crate::BitReader<Lk>;
22impl LkR {
23 #[doc = "Get enumerated values variant"]
24 #[inline(always)]
25 pub const fn variant(&self) -> Lk {
26 match self.bits {
27 false => Lk::WriteEnabled,
28 true => Lk::WriteDisabled,
29 }
30 }
31 #[doc = "Control Status Register can be written"]
32 #[inline(always)]
33 pub fn is_write_enabled(&self) -> bool {
34 *self == Lk::WriteEnabled
35 }
36 #[doc = "Control Status Register cannot be written"]
37 #[inline(always)]
38 pub fn is_write_disabled(&self) -> bool {
39 *self == Lk::WriteDisabled
40 }
41}
42#[doc = "Field `LK` writer - Lock Register"]
43pub type LkW<'a, REG> = crate::BitWriter<'a, REG, Lk>;
44impl<'a, REG> LkW<'a, REG>
45where
46 REG: crate::Writable + crate::RegisterSpec,
47{
48 #[doc = "Control Status Register can be written"]
49 #[inline(always)]
50 pub fn write_enabled(self) -> &'a mut crate::W<REG> {
51 self.variant(Lk::WriteEnabled)
52 }
53 #[doc = "Control Status Register cannot be written"]
54 #[inline(always)]
55 pub fn write_disabled(self) -> &'a mut crate::W<REG> {
56 self.variant(Lk::WriteDisabled)
57 }
58}
59#[doc = "ROSC Valid\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Roscvld {
63 #[doc = "0: ROSC is not enabled or clock is not valid"]
64 DisabledOrNotValid = 0,
65 #[doc = "1: ROSC is enabled and output clock is valid"]
66 EnabledAndValid = 1,
67}
68impl From<Roscvld> for bool {
69 #[inline(always)]
70 fn from(variant: Roscvld) -> Self {
71 variant as u8 != 0
72 }
73}
74#[doc = "Field `ROSCVLD` reader - ROSC Valid"]
75pub type RoscvldR = crate::BitReader<Roscvld>;
76impl RoscvldR {
77 #[doc = "Get enumerated values variant"]
78 #[inline(always)]
79 pub const fn variant(&self) -> Roscvld {
80 match self.bits {
81 false => Roscvld::DisabledOrNotValid,
82 true => Roscvld::EnabledAndValid,
83 }
84 }
85 #[doc = "ROSC is not enabled or clock is not valid"]
86 #[inline(always)]
87 pub fn is_disabled_or_not_valid(&self) -> bool {
88 *self == Roscvld::DisabledOrNotValid
89 }
90 #[doc = "ROSC is enabled and output clock is valid"]
91 #[inline(always)]
92 pub fn is_enabled_and_valid(&self) -> bool {
93 *self == Roscvld::EnabledAndValid
94 }
95}
96#[doc = "ROSC Selected\n\nValue on reset: 0"]
97#[cfg_attr(feature = "defmt", derive(defmt::Format))]
98#[derive(Clone, Copy, Debug, PartialEq, Eq)]
99pub enum Roscsel {
100 #[doc = "0: ROSC is not the system clock source"]
101 NotRosc = 0,
102 #[doc = "1: ROSC is the system clock source"]
103 Rosc = 1,
104}
105impl From<Roscsel> for bool {
106 #[inline(always)]
107 fn from(variant: Roscsel) -> Self {
108 variant as u8 != 0
109 }
110}
111#[doc = "Field `ROSCSEL` reader - ROSC Selected"]
112pub type RoscselR = crate::BitReader<Roscsel>;
113impl RoscselR {
114 #[doc = "Get enumerated values variant"]
115 #[inline(always)]
116 pub const fn variant(&self) -> Roscsel {
117 match self.bits {
118 false => Roscsel::NotRosc,
119 true => Roscsel::Rosc,
120 }
121 }
122 #[doc = "ROSC is not the system clock source"]
123 #[inline(always)]
124 pub fn is_not_rosc(&self) -> bool {
125 *self == Roscsel::NotRosc
126 }
127 #[doc = "ROSC is the system clock source"]
128 #[inline(always)]
129 pub fn is_rosc(&self) -> bool {
130 *self == Roscsel::Rosc
131 }
132}
133#[doc = "ROSC Clock Error\n\nValue on reset: 0"]
134#[cfg_attr(feature = "defmt", derive(defmt::Format))]
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136pub enum Roscerr {
137 #[doc = "0: ROSC Clock has not detected an error"]
138 DisabledOrNoError = 0,
139 #[doc = "1: ROSC Clock has detected an error"]
140 EnabledAndError = 1,
141}
142impl From<Roscerr> for bool {
143 #[inline(always)]
144 fn from(variant: Roscerr) -> Self {
145 variant as u8 != 0
146 }
147}
148#[doc = "Field `ROSCERR` reader - ROSC Clock Error"]
149pub type RoscerrR = crate::BitReader<Roscerr>;
150impl RoscerrR {
151 #[doc = "Get enumerated values variant"]
152 #[inline(always)]
153 pub const fn variant(&self) -> Roscerr {
154 match self.bits {
155 false => Roscerr::DisabledOrNoError,
156 true => Roscerr::EnabledAndError,
157 }
158 }
159 #[doc = "ROSC Clock has not detected an error"]
160 #[inline(always)]
161 pub fn is_disabled_or_no_error(&self) -> bool {
162 *self == Roscerr::DisabledOrNoError
163 }
164 #[doc = "ROSC Clock has detected an error"]
165 #[inline(always)]
166 pub fn is_enabled_and_error(&self) -> bool {
167 *self == Roscerr::EnabledAndError
168 }
169}
170#[doc = "Field `ROSCERR` writer - ROSC Clock Error"]
171pub type RoscerrW<'a, REG> = crate::BitWriter1C<'a, REG, Roscerr>;
172impl<'a, REG> RoscerrW<'a, REG>
173where
174 REG: crate::Writable + crate::RegisterSpec,
175{
176 #[doc = "ROSC Clock has not detected an error"]
177 #[inline(always)]
178 pub fn disabled_or_no_error(self) -> &'a mut crate::W<REG> {
179 self.variant(Roscerr::DisabledOrNoError)
180 }
181 #[doc = "ROSC Clock has detected an error"]
182 #[inline(always)]
183 pub fn enabled_and_error(self) -> &'a mut crate::W<REG> {
184 self.variant(Roscerr::EnabledAndError)
185 }
186}
187impl R {
188 #[doc = "Bit 23 - Lock Register"]
189 #[inline(always)]
190 pub fn lk(&self) -> LkR {
191 LkR::new(((self.bits >> 23) & 1) != 0)
192 }
193 #[doc = "Bit 24 - ROSC Valid"]
194 #[inline(always)]
195 pub fn roscvld(&self) -> RoscvldR {
196 RoscvldR::new(((self.bits >> 24) & 1) != 0)
197 }
198 #[doc = "Bit 25 - ROSC Selected"]
199 #[inline(always)]
200 pub fn roscsel(&self) -> RoscselR {
201 RoscselR::new(((self.bits >> 25) & 1) != 0)
202 }
203 #[doc = "Bit 26 - ROSC Clock Error"]
204 #[inline(always)]
205 pub fn roscerr(&self) -> RoscerrR {
206 RoscerrR::new(((self.bits >> 26) & 1) != 0)
207 }
208}
209#[cfg(feature = "debug")]
210impl core::fmt::Debug for R {
211 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
212 f.debug_struct("ROSCCSR")
213 .field("lk", &self.lk())
214 .field("roscvld", &self.roscvld())
215 .field("roscsel", &self.roscsel())
216 .field("roscerr", &self.roscerr())
217 .finish()
218 }
219}
220impl W {
221 #[doc = "Bit 23 - Lock Register"]
222 #[inline(always)]
223 pub fn lk(&mut self) -> LkW<'_, RosccsrSpec> {
224 LkW::new(self, 23)
225 }
226 #[doc = "Bit 26 - ROSC Clock Error"]
227 #[inline(always)]
228 pub fn roscerr(&mut self) -> RoscerrW<'_, RosccsrSpec> {
229 RoscerrW::new(self, 26)
230 }
231}
232#[doc = "ROSC Control Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`rosccsr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rosccsr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
233pub struct RosccsrSpec;
234impl crate::RegisterSpec for RosccsrSpec {
235 type Ux = u32;
236}
237#[doc = "`read()` method returns [`rosccsr::R`](R) reader structure"]
238impl crate::Readable for RosccsrSpec {}
239#[doc = "`write(|w| ..)` method takes [`rosccsr::W`](W) writer structure"]
240impl crate::Writable for RosccsrSpec {
241 type Safety = crate::Unsafe;
242 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400_0000;
243}
244#[doc = "`reset()` method sets ROSCCSR to value 0"]
245impl crate::Resettable for RosccsrSpec {}