mcxa_pac/ostimer0/
osevent_ctrl.rs

1#[doc = "Register `OSEVENT_CTRL` reader"]
2pub type R = crate::R<OseventCtrlSpec>;
3#[doc = "Register `OSEVENT_CTRL` writer"]
4pub type W = crate::W<OseventCtrlSpec>;
5#[doc = "Field `OSTIMER_INTRFLAG` reader - Interrupt Flag"]
6pub type OstimerIntrflagR = crate::BitReader;
7#[doc = "Field `OSTIMER_INTRFLAG` writer - Interrupt Flag"]
8pub type OstimerIntrflagW<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Interrupt or Wake-Up Request\n\nValue on reset: 0"]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum OstimerIntena {
13    #[doc = "0: Interrupts blocked"]
14    InterruptsBlocked = 0,
15    #[doc = "1: Interrupts enabled"]
16    InterruptsEnabled = 1,
17}
18impl From<OstimerIntena> for bool {
19    #[inline(always)]
20    fn from(variant: OstimerIntena) -> Self {
21        variant as u8 != 0
22    }
23}
24#[doc = "Field `OSTIMER_INTENA` reader - Interrupt or Wake-Up Request"]
25pub type OstimerIntenaR = crate::BitReader<OstimerIntena>;
26impl OstimerIntenaR {
27    #[doc = "Get enumerated values variant"]
28    #[inline(always)]
29    pub const fn variant(&self) -> OstimerIntena {
30        match self.bits {
31            false => OstimerIntena::InterruptsBlocked,
32            true => OstimerIntena::InterruptsEnabled,
33        }
34    }
35    #[doc = "Interrupts blocked"]
36    #[inline(always)]
37    pub fn is_interrupts_blocked(&self) -> bool {
38        *self == OstimerIntena::InterruptsBlocked
39    }
40    #[doc = "Interrupts enabled"]
41    #[inline(always)]
42    pub fn is_interrupts_enabled(&self) -> bool {
43        *self == OstimerIntena::InterruptsEnabled
44    }
45}
46#[doc = "Field `OSTIMER_INTENA` writer - Interrupt or Wake-Up Request"]
47pub type OstimerIntenaW<'a, REG> = crate::BitWriter<'a, REG, OstimerIntena>;
48impl<'a, REG> OstimerIntenaW<'a, REG>
49where
50    REG: crate::Writable + crate::RegisterSpec,
51{
52    #[doc = "Interrupts blocked"]
53    #[inline(always)]
54    pub fn interrupts_blocked(self) -> &'a mut crate::W<REG> {
55        self.variant(OstimerIntena::InterruptsBlocked)
56    }
57    #[doc = "Interrupts enabled"]
58    #[inline(always)]
59    pub fn interrupts_enabled(self) -> &'a mut crate::W<REG> {
60        self.variant(OstimerIntena::InterruptsEnabled)
61    }
62}
63#[doc = "Field `MATCH_WR_RDY` reader - EVTimer Match Write Ready"]
64pub type MatchWrRdyR = crate::BitReader;
65#[doc = "Debug Enable\n\nValue on reset: 1"]
66#[cfg_attr(feature = "defmt", derive(defmt::Format))]
67#[derive(Clone, Copy, Debug, PartialEq, Eq)]
68pub enum DebugEn {
69    #[doc = "0: Disables"]
70    Disable = 0,
71    #[doc = "1: Enables"]
72    Enable = 1,
73}
74impl From<DebugEn> for bool {
75    #[inline(always)]
76    fn from(variant: DebugEn) -> Self {
77        variant as u8 != 0
78    }
79}
80#[doc = "Field `DEBUG_EN` reader - Debug Enable"]
81pub type DebugEnR = crate::BitReader<DebugEn>;
82impl DebugEnR {
83    #[doc = "Get enumerated values variant"]
84    #[inline(always)]
85    pub const fn variant(&self) -> DebugEn {
86        match self.bits {
87            false => DebugEn::Disable,
88            true => DebugEn::Enable,
89        }
90    }
91    #[doc = "Disables"]
92    #[inline(always)]
93    pub fn is_disable(&self) -> bool {
94        *self == DebugEn::Disable
95    }
96    #[doc = "Enables"]
97    #[inline(always)]
98    pub fn is_enable(&self) -> bool {
99        *self == DebugEn::Enable
100    }
101}
102#[doc = "Field `DEBUG_EN` writer - Debug Enable"]
103pub type DebugEnW<'a, REG> = crate::BitWriter<'a, REG, DebugEn>;
104impl<'a, REG> DebugEnW<'a, REG>
105where
106    REG: crate::Writable + crate::RegisterSpec,
107{
108    #[doc = "Disables"]
109    #[inline(always)]
110    pub fn disable(self) -> &'a mut crate::W<REG> {
111        self.variant(DebugEn::Disable)
112    }
113    #[doc = "Enables"]
114    #[inline(always)]
115    pub fn enable(self) -> &'a mut crate::W<REG> {
116        self.variant(DebugEn::Enable)
117    }
118}
119impl R {
120    #[doc = "Bit 0 - Interrupt Flag"]
121    #[inline(always)]
122    pub fn ostimer_intrflag(&self) -> OstimerIntrflagR {
123        OstimerIntrflagR::new((self.bits & 1) != 0)
124    }
125    #[doc = "Bit 1 - Interrupt or Wake-Up Request"]
126    #[inline(always)]
127    pub fn ostimer_intena(&self) -> OstimerIntenaR {
128        OstimerIntenaR::new(((self.bits >> 1) & 1) != 0)
129    }
130    #[doc = "Bit 2 - EVTimer Match Write Ready"]
131    #[inline(always)]
132    pub fn match_wr_rdy(&self) -> MatchWrRdyR {
133        MatchWrRdyR::new(((self.bits >> 2) & 1) != 0)
134    }
135    #[doc = "Bit 3 - Debug Enable"]
136    #[inline(always)]
137    pub fn debug_en(&self) -> DebugEnR {
138        DebugEnR::new(((self.bits >> 3) & 1) != 0)
139    }
140}
141#[cfg(feature = "debug")]
142impl core::fmt::Debug for R {
143    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
144        f.debug_struct("OSEVENT_CTRL")
145            .field("ostimer_intrflag", &self.ostimer_intrflag())
146            .field("ostimer_intena", &self.ostimer_intena())
147            .field("match_wr_rdy", &self.match_wr_rdy())
148            .field("debug_en", &self.debug_en())
149            .finish()
150    }
151}
152impl W {
153    #[doc = "Bit 0 - Interrupt Flag"]
154    #[inline(always)]
155    pub fn ostimer_intrflag(&mut self) -> OstimerIntrflagW<'_, OseventCtrlSpec> {
156        OstimerIntrflagW::new(self, 0)
157    }
158    #[doc = "Bit 1 - Interrupt or Wake-Up Request"]
159    #[inline(always)]
160    pub fn ostimer_intena(&mut self) -> OstimerIntenaW<'_, OseventCtrlSpec> {
161        OstimerIntenaW::new(self, 1)
162    }
163    #[doc = "Bit 3 - Debug Enable"]
164    #[inline(always)]
165    pub fn debug_en(&mut self) -> DebugEnW<'_, OseventCtrlSpec> {
166        DebugEnW::new(self, 3)
167    }
168}
169#[doc = "OSTIMER Control for CPU\n\nYou can [`read`](crate::Reg::read) this register and get [`osevent_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`osevent_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
170pub struct OseventCtrlSpec;
171impl crate::RegisterSpec for OseventCtrlSpec {
172    type Ux = u32;
173}
174#[doc = "`read()` method returns [`osevent_ctrl::R`](R) reader structure"]
175impl crate::Readable for OseventCtrlSpec {}
176#[doc = "`write(|w| ..)` method takes [`osevent_ctrl::W`](W) writer structure"]
177impl crate::Writable for OseventCtrlSpec {
178    type Safety = crate::Unsafe;
179    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01;
180}
181#[doc = "`reset()` method sets OSEVENT_CTRL to value 0x08"]
182impl crate::Resettable for OseventCtrlSpec {
183    const RESET_VALUE: u32 = 0x08;
184}
mcxa_pac/ostimer0/osevent_ctrl.rs

mcxa_pac/ostimer0/
osevent_ctrl.rs
