mcxa_pac/mrcc0/
mrcc_glb_acc1.rs

1#[doc = "Register `MRCC_GLB_ACC1` reader"]
2pub type R = crate::R<MrccGlbAcc1Spec>;
3#[doc = "Register `MRCC_GLB_ACC1` writer"]
4pub type W = crate::W<MrccGlbAcc1Spec>;
5#[doc = "FLEXPWM1\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Flexpwm1 {
9    #[doc = "0: Automatic clock gating is disabled"]
10    Disabled = 0,
11    #[doc = "1: Automatic clock gating is enabled"]
12    Enabled = 1,
13}
14impl From<Flexpwm1> for bool {
15    #[inline(always)]
16    fn from(variant: Flexpwm1) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `FLEXPWM1` reader - FLEXPWM1"]
21pub type Flexpwm1R = crate::BitReader<Flexpwm1>;
22impl Flexpwm1R {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Flexpwm1 {
26        match self.bits {
27            false => Flexpwm1::Disabled,
28            true => Flexpwm1::Enabled,
29        }
30    }
31    #[doc = "Automatic clock gating is disabled"]
32    #[inline(always)]
33    pub fn is_disabled(&self) -> bool {
34        *self == Flexpwm1::Disabled
35    }
36    #[doc = "Automatic clock gating is enabled"]
37    #[inline(always)]
38    pub fn is_enabled(&self) -> bool {
39        *self == Flexpwm1::Enabled
40    }
41}
42#[doc = "Field `FLEXPWM1` writer - FLEXPWM1"]
43pub type Flexpwm1W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm1>;
44impl<'a, REG> Flexpwm1W<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Automatic clock gating is disabled"]
49    #[inline(always)]
50    pub fn disabled(self) -> &'a mut crate::W<REG> {
51        self.variant(Flexpwm1::Disabled)
52    }
53    #[doc = "Automatic clock gating is enabled"]
54    #[inline(always)]
55    pub fn enabled(self) -> &'a mut crate::W<REG> {
56        self.variant(Flexpwm1::Enabled)
57    }
58}
59#[doc = "OSTIMER0\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Ostimer0 {
63    #[doc = "0: Automatic clock gating is disabled"]
64    Disabled = 0,
65    #[doc = "1: Automatic clock gating is enabled"]
66    Enabled = 1,
67}
68impl From<Ostimer0> for bool {
69    #[inline(always)]
70    fn from(variant: Ostimer0) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `OSTIMER0` reader - OSTIMER0"]
75pub type Ostimer0R = crate::BitReader<Ostimer0>;
76impl Ostimer0R {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Ostimer0 {
80        match self.bits {
81            false => Ostimer0::Disabled,
82            true => Ostimer0::Enabled,
83        }
84    }
85    #[doc = "Automatic clock gating is disabled"]
86    #[inline(always)]
87    pub fn is_disabled(&self) -> bool {
88        *self == Ostimer0::Disabled
89    }
90    #[doc = "Automatic clock gating is enabled"]
91    #[inline(always)]
92    pub fn is_enabled(&self) -> bool {
93        *self == Ostimer0::Enabled
94    }
95}
96#[doc = "Field `OSTIMER0` writer - OSTIMER0"]
97pub type Ostimer0W<'a, REG> = crate::BitWriter<'a, REG, Ostimer0>;
98impl<'a, REG> Ostimer0W<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Automatic clock gating is disabled"]
103    #[inline(always)]
104    pub fn disabled(self) -> &'a mut crate::W<REG> {
105        self.variant(Ostimer0::Disabled)
106    }
107    #[doc = "Automatic clock gating is enabled"]
108    #[inline(always)]
109    pub fn enabled(self) -> &'a mut crate::W<REG> {
110        self.variant(Ostimer0::Enabled)
111    }
112}
113#[doc = "ADC0\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Adc0 {
117    #[doc = "0: Automatic clock gating is disabled"]
118    Disabled = 0,
119    #[doc = "1: Automatic clock gating is enabled"]
120    Enabled = 1,
121}
122impl From<Adc0> for bool {
123    #[inline(always)]
124    fn from(variant: Adc0) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `ADC0` reader - ADC0"]
129pub type Adc0R = crate::BitReader<Adc0>;
130impl Adc0R {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Adc0 {
134        match self.bits {
135            false => Adc0::Disabled,
136            true => Adc0::Enabled,
137        }
138    }
139    #[doc = "Automatic clock gating is disabled"]
140    #[inline(always)]
141    pub fn is_disabled(&self) -> bool {
142        *self == Adc0::Disabled
143    }
144    #[doc = "Automatic clock gating is enabled"]
145    #[inline(always)]
146    pub fn is_enabled(&self) -> bool {
147        *self == Adc0::Enabled
148    }
149}
150#[doc = "Field `ADC0` writer - ADC0"]
151pub type Adc0W<'a, REG> = crate::BitWriter<'a, REG, Adc0>;
152impl<'a, REG> Adc0W<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Automatic clock gating is disabled"]
157    #[inline(always)]
158    pub fn disabled(self) -> &'a mut crate::W<REG> {
159        self.variant(Adc0::Disabled)
160    }
161    #[doc = "Automatic clock gating is enabled"]
162    #[inline(always)]
163    pub fn enabled(self) -> &'a mut crate::W<REG> {
164        self.variant(Adc0::Enabled)
165    }
166}
167#[doc = "ADC1\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Adc1 {
171    #[doc = "0: Automatic clock gating is disabled"]
172    Disabled = 0,
173    #[doc = "1: Automatic clock gating is enabled"]
174    Enabled = 1,
175}
176impl From<Adc1> for bool {
177    #[inline(always)]
178    fn from(variant: Adc1) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `ADC1` reader - ADC1"]
183pub type Adc1R = crate::BitReader<Adc1>;
184impl Adc1R {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Adc1 {
188        match self.bits {
189            false => Adc1::Disabled,
190            true => Adc1::Enabled,
191        }
192    }
193    #[doc = "Automatic clock gating is disabled"]
194    #[inline(always)]
195    pub fn is_disabled(&self) -> bool {
196        *self == Adc1::Disabled
197    }
198    #[doc = "Automatic clock gating is enabled"]
199    #[inline(always)]
200    pub fn is_enabled(&self) -> bool {
201        *self == Adc1::Enabled
202    }
203}
204#[doc = "Field `ADC1` writer - ADC1"]
205pub type Adc1W<'a, REG> = crate::BitWriter<'a, REG, Adc1>;
206impl<'a, REG> Adc1W<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Automatic clock gating is disabled"]
211    #[inline(always)]
212    pub fn disabled(self) -> &'a mut crate::W<REG> {
213        self.variant(Adc1::Disabled)
214    }
215    #[doc = "Automatic clock gating is enabled"]
216    #[inline(always)]
217    pub fn enabled(self) -> &'a mut crate::W<REG> {
218        self.variant(Adc1::Enabled)
219    }
220}
221#[doc = "CMP0\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum Cmp0 {
225    #[doc = "0: Automatic clock gating is disabled"]
226    Disabled = 0,
227    #[doc = "1: Automatic clock gating is enabled"]
228    Enabled = 1,
229}
230impl From<Cmp0> for bool {
231    #[inline(always)]
232    fn from(variant: Cmp0) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `CMP0` reader - CMP0"]
237pub type Cmp0R = crate::BitReader<Cmp0>;
238impl Cmp0R {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> Cmp0 {
242        match self.bits {
243            false => Cmp0::Disabled,
244            true => Cmp0::Enabled,
245        }
246    }
247    #[doc = "Automatic clock gating is disabled"]
248    #[inline(always)]
249    pub fn is_disabled(&self) -> bool {
250        *self == Cmp0::Disabled
251    }
252    #[doc = "Automatic clock gating is enabled"]
253    #[inline(always)]
254    pub fn is_enabled(&self) -> bool {
255        *self == Cmp0::Enabled
256    }
257}
258#[doc = "Field `CMP0` writer - CMP0"]
259pub type Cmp0W<'a, REG> = crate::BitWriter<'a, REG, Cmp0>;
260impl<'a, REG> Cmp0W<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263{
264    #[doc = "Automatic clock gating is disabled"]
265    #[inline(always)]
266    pub fn disabled(self) -> &'a mut crate::W<REG> {
267        self.variant(Cmp0::Disabled)
268    }
269    #[doc = "Automatic clock gating is enabled"]
270    #[inline(always)]
271    pub fn enabled(self) -> &'a mut crate::W<REG> {
272        self.variant(Cmp0::Enabled)
273    }
274}
275#[doc = "CMP1\n\nValue on reset: 0"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum Cmp1 {
279    #[doc = "0: Automatic clock gating is disabled"]
280    Disabled = 0,
281    #[doc = "1: Automatic clock gating is enabled"]
282    Enabled = 1,
283}
284impl From<Cmp1> for bool {
285    #[inline(always)]
286    fn from(variant: Cmp1) -> Self {
287        variant as u8 != 0
288    }
289}
290#[doc = "Field `CMP1` reader - CMP1"]
291pub type Cmp1R = crate::BitReader<Cmp1>;
292impl Cmp1R {
293    #[doc = "Get enumerated values variant"]
294    #[inline(always)]
295    pub const fn variant(&self) -> Cmp1 {
296        match self.bits {
297            false => Cmp1::Disabled,
298            true => Cmp1::Enabled,
299        }
300    }
301    #[doc = "Automatic clock gating is disabled"]
302    #[inline(always)]
303    pub fn is_disabled(&self) -> bool {
304        *self == Cmp1::Disabled
305    }
306    #[doc = "Automatic clock gating is enabled"]
307    #[inline(always)]
308    pub fn is_enabled(&self) -> bool {
309        *self == Cmp1::Enabled
310    }
311}
312#[doc = "Field `CMP1` writer - CMP1"]
313pub type Cmp1W<'a, REG> = crate::BitWriter<'a, REG, Cmp1>;
314impl<'a, REG> Cmp1W<'a, REG>
315where
316    REG: crate::Writable + crate::RegisterSpec,
317{
318    #[doc = "Automatic clock gating is disabled"]
319    #[inline(always)]
320    pub fn disabled(self) -> &'a mut crate::W<REG> {
321        self.variant(Cmp1::Disabled)
322    }
323    #[doc = "Automatic clock gating is enabled"]
324    #[inline(always)]
325    pub fn enabled(self) -> &'a mut crate::W<REG> {
326        self.variant(Cmp1::Enabled)
327    }
328}
329#[doc = "CMP2\n\nValue on reset: 0"]
330#[cfg_attr(feature = "defmt", derive(defmt::Format))]
331#[derive(Clone, Copy, Debug, PartialEq, Eq)]
332pub enum Cmp2 {
333    #[doc = "0: Automatic clock gating is disabled"]
334    Disabled = 0,
335    #[doc = "1: Automatic clock gating is enabled"]
336    Enabled = 1,
337}
338impl From<Cmp2> for bool {
339    #[inline(always)]
340    fn from(variant: Cmp2) -> Self {
341        variant as u8 != 0
342    }
343}
344#[doc = "Field `CMP2` reader - CMP2"]
345pub type Cmp2R = crate::BitReader<Cmp2>;
346impl Cmp2R {
347    #[doc = "Get enumerated values variant"]
348    #[inline(always)]
349    pub const fn variant(&self) -> Cmp2 {
350        match self.bits {
351            false => Cmp2::Disabled,
352            true => Cmp2::Enabled,
353        }
354    }
355    #[doc = "Automatic clock gating is disabled"]
356    #[inline(always)]
357    pub fn is_disabled(&self) -> bool {
358        *self == Cmp2::Disabled
359    }
360    #[doc = "Automatic clock gating is enabled"]
361    #[inline(always)]
362    pub fn is_enabled(&self) -> bool {
363        *self == Cmp2::Enabled
364    }
365}
366#[doc = "Field `CMP2` writer - CMP2"]
367pub type Cmp2W<'a, REG> = crate::BitWriter<'a, REG, Cmp2>;
368impl<'a, REG> Cmp2W<'a, REG>
369where
370    REG: crate::Writable + crate::RegisterSpec,
371{
372    #[doc = "Automatic clock gating is disabled"]
373    #[inline(always)]
374    pub fn disabled(self) -> &'a mut crate::W<REG> {
375        self.variant(Cmp2::Disabled)
376    }
377    #[doc = "Automatic clock gating is enabled"]
378    #[inline(always)]
379    pub fn enabled(self) -> &'a mut crate::W<REG> {
380        self.variant(Cmp2::Enabled)
381    }
382}
383#[doc = "DAC0\n\nValue on reset: 0"]
384#[cfg_attr(feature = "defmt", derive(defmt::Format))]
385#[derive(Clone, Copy, Debug, PartialEq, Eq)]
386pub enum Dac0 {
387    #[doc = "0: Automatic clock gating is disabled"]
388    Disabled = 0,
389    #[doc = "1: Automatic clock gating is enabled"]
390    Enabled = 1,
391}
392impl From<Dac0> for bool {
393    #[inline(always)]
394    fn from(variant: Dac0) -> Self {
395        variant as u8 != 0
396    }
397}
398#[doc = "Field `DAC0` reader - DAC0"]
399pub type Dac0R = crate::BitReader<Dac0>;
400impl Dac0R {
401    #[doc = "Get enumerated values variant"]
402    #[inline(always)]
403    pub const fn variant(&self) -> Dac0 {
404        match self.bits {
405            false => Dac0::Disabled,
406            true => Dac0::Enabled,
407        }
408    }
409    #[doc = "Automatic clock gating is disabled"]
410    #[inline(always)]
411    pub fn is_disabled(&self) -> bool {
412        *self == Dac0::Disabled
413    }
414    #[doc = "Automatic clock gating is enabled"]
415    #[inline(always)]
416    pub fn is_enabled(&self) -> bool {
417        *self == Dac0::Enabled
418    }
419}
420#[doc = "Field `DAC0` writer - DAC0"]
421pub type Dac0W<'a, REG> = crate::BitWriter<'a, REG, Dac0>;
422impl<'a, REG> Dac0W<'a, REG>
423where
424    REG: crate::Writable + crate::RegisterSpec,
425{
426    #[doc = "Automatic clock gating is disabled"]
427    #[inline(always)]
428    pub fn disabled(self) -> &'a mut crate::W<REG> {
429        self.variant(Dac0::Disabled)
430    }
431    #[doc = "Automatic clock gating is enabled"]
432    #[inline(always)]
433    pub fn enabled(self) -> &'a mut crate::W<REG> {
434        self.variant(Dac0::Enabled)
435    }
436}
437#[doc = "OPAMP0\n\nValue on reset: 0"]
438#[cfg_attr(feature = "defmt", derive(defmt::Format))]
439#[derive(Clone, Copy, Debug, PartialEq, Eq)]
440pub enum Opamp0 {
441    #[doc = "0: Automatic clock gating is disabled"]
442    Disabled = 0,
443    #[doc = "1: Automatic clock gating is enabled"]
444    Enabled = 1,
445}
446impl From<Opamp0> for bool {
447    #[inline(always)]
448    fn from(variant: Opamp0) -> Self {
449        variant as u8 != 0
450    }
451}
452#[doc = "Field `OPAMP0` reader - OPAMP0"]
453pub type Opamp0R = crate::BitReader<Opamp0>;
454impl Opamp0R {
455    #[doc = "Get enumerated values variant"]
456    #[inline(always)]
457    pub const fn variant(&self) -> Opamp0 {
458        match self.bits {
459            false => Opamp0::Disabled,
460            true => Opamp0::Enabled,
461        }
462    }
463    #[doc = "Automatic clock gating is disabled"]
464    #[inline(always)]
465    pub fn is_disabled(&self) -> bool {
466        *self == Opamp0::Disabled
467    }
468    #[doc = "Automatic clock gating is enabled"]
469    #[inline(always)]
470    pub fn is_enabled(&self) -> bool {
471        *self == Opamp0::Enabled
472    }
473}
474#[doc = "Field `OPAMP0` writer - OPAMP0"]
475pub type Opamp0W<'a, REG> = crate::BitWriter<'a, REG, Opamp0>;
476impl<'a, REG> Opamp0W<'a, REG>
477where
478    REG: crate::Writable + crate::RegisterSpec,
479{
480    #[doc = "Automatic clock gating is disabled"]
481    #[inline(always)]
482    pub fn disabled(self) -> &'a mut crate::W<REG> {
483        self.variant(Opamp0::Disabled)
484    }
485    #[doc = "Automatic clock gating is enabled"]
486    #[inline(always)]
487    pub fn enabled(self) -> &'a mut crate::W<REG> {
488        self.variant(Opamp0::Enabled)
489    }
490}
491#[doc = "OPAMP1\n\nValue on reset: 0"]
492#[cfg_attr(feature = "defmt", derive(defmt::Format))]
493#[derive(Clone, Copy, Debug, PartialEq, Eq)]
494pub enum Opamp1 {
495    #[doc = "0: Automatic clock gating is disabled"]
496    Disabled = 0,
497    #[doc = "1: Automatic clock gating is enabled"]
498    Enabled = 1,
499}
500impl From<Opamp1> for bool {
501    #[inline(always)]
502    fn from(variant: Opamp1) -> Self {
503        variant as u8 != 0
504    }
505}
506#[doc = "Field `OPAMP1` reader - OPAMP1"]
507pub type Opamp1R = crate::BitReader<Opamp1>;
508impl Opamp1R {
509    #[doc = "Get enumerated values variant"]
510    #[inline(always)]
511    pub const fn variant(&self) -> Opamp1 {
512        match self.bits {
513            false => Opamp1::Disabled,
514            true => Opamp1::Enabled,
515        }
516    }
517    #[doc = "Automatic clock gating is disabled"]
518    #[inline(always)]
519    pub fn is_disabled(&self) -> bool {
520        *self == Opamp1::Disabled
521    }
522    #[doc = "Automatic clock gating is enabled"]
523    #[inline(always)]
524    pub fn is_enabled(&self) -> bool {
525        *self == Opamp1::Enabled
526    }
527}
528#[doc = "Field `OPAMP1` writer - OPAMP1"]
529pub type Opamp1W<'a, REG> = crate::BitWriter<'a, REG, Opamp1>;
530impl<'a, REG> Opamp1W<'a, REG>
531where
532    REG: crate::Writable + crate::RegisterSpec,
533{
534    #[doc = "Automatic clock gating is disabled"]
535    #[inline(always)]
536    pub fn disabled(self) -> &'a mut crate::W<REG> {
537        self.variant(Opamp1::Disabled)
538    }
539    #[doc = "Automatic clock gating is enabled"]
540    #[inline(always)]
541    pub fn enabled(self) -> &'a mut crate::W<REG> {
542        self.variant(Opamp1::Enabled)
543    }
544}
545#[doc = "OPAMP2\n\nValue on reset: 0"]
546#[cfg_attr(feature = "defmt", derive(defmt::Format))]
547#[derive(Clone, Copy, Debug, PartialEq, Eq)]
548pub enum Opamp2 {
549    #[doc = "0: Automatic clock gating is disabled"]
550    Disabled = 0,
551    #[doc = "1: Automatic clock gating is enabled"]
552    Enabled = 1,
553}
554impl From<Opamp2> for bool {
555    #[inline(always)]
556    fn from(variant: Opamp2) -> Self {
557        variant as u8 != 0
558    }
559}
560#[doc = "Field `OPAMP2` reader - OPAMP2"]
561pub type Opamp2R = crate::BitReader<Opamp2>;
562impl Opamp2R {
563    #[doc = "Get enumerated values variant"]
564    #[inline(always)]
565    pub const fn variant(&self) -> Opamp2 {
566        match self.bits {
567            false => Opamp2::Disabled,
568            true => Opamp2::Enabled,
569        }
570    }
571    #[doc = "Automatic clock gating is disabled"]
572    #[inline(always)]
573    pub fn is_disabled(&self) -> bool {
574        *self == Opamp2::Disabled
575    }
576    #[doc = "Automatic clock gating is enabled"]
577    #[inline(always)]
578    pub fn is_enabled(&self) -> bool {
579        *self == Opamp2::Enabled
580    }
581}
582#[doc = "Field `OPAMP2` writer - OPAMP2"]
583pub type Opamp2W<'a, REG> = crate::BitWriter<'a, REG, Opamp2>;
584impl<'a, REG> Opamp2W<'a, REG>
585where
586    REG: crate::Writable + crate::RegisterSpec,
587{
588    #[doc = "Automatic clock gating is disabled"]
589    #[inline(always)]
590    pub fn disabled(self) -> &'a mut crate::W<REG> {
591        self.variant(Opamp2::Disabled)
592    }
593    #[doc = "Automatic clock gating is enabled"]
594    #[inline(always)]
595    pub fn enabled(self) -> &'a mut crate::W<REG> {
596        self.variant(Opamp2::Enabled)
597    }
598}
599#[doc = "OPAMP3\n\nValue on reset: 0"]
600#[cfg_attr(feature = "defmt", derive(defmt::Format))]
601#[derive(Clone, Copy, Debug, PartialEq, Eq)]
602pub enum Opamp3 {
603    #[doc = "0: Automatic clock gating is disabled"]
604    Disabled = 0,
605    #[doc = "1: Automatic clock gating is enabled"]
606    Enabled = 1,
607}
608impl From<Opamp3> for bool {
609    #[inline(always)]
610    fn from(variant: Opamp3) -> Self {
611        variant as u8 != 0
612    }
613}
614#[doc = "Field `OPAMP3` reader - OPAMP3"]
615pub type Opamp3R = crate::BitReader<Opamp3>;
616impl Opamp3R {
617    #[doc = "Get enumerated values variant"]
618    #[inline(always)]
619    pub const fn variant(&self) -> Opamp3 {
620        match self.bits {
621            false => Opamp3::Disabled,
622            true => Opamp3::Enabled,
623        }
624    }
625    #[doc = "Automatic clock gating is disabled"]
626    #[inline(always)]
627    pub fn is_disabled(&self) -> bool {
628        *self == Opamp3::Disabled
629    }
630    #[doc = "Automatic clock gating is enabled"]
631    #[inline(always)]
632    pub fn is_enabled(&self) -> bool {
633        *self == Opamp3::Enabled
634    }
635}
636#[doc = "Field `OPAMP3` writer - OPAMP3"]
637pub type Opamp3W<'a, REG> = crate::BitWriter<'a, REG, Opamp3>;
638impl<'a, REG> Opamp3W<'a, REG>
639where
640    REG: crate::Writable + crate::RegisterSpec,
641{
642    #[doc = "Automatic clock gating is disabled"]
643    #[inline(always)]
644    pub fn disabled(self) -> &'a mut crate::W<REG> {
645        self.variant(Opamp3::Disabled)
646    }
647    #[doc = "Automatic clock gating is enabled"]
648    #[inline(always)]
649    pub fn enabled(self) -> &'a mut crate::W<REG> {
650        self.variant(Opamp3::Enabled)
651    }
652}
653#[doc = "PORT0\n\nValue on reset: 0"]
654#[cfg_attr(feature = "defmt", derive(defmt::Format))]
655#[derive(Clone, Copy, Debug, PartialEq, Eq)]
656pub enum Port0 {
657    #[doc = "0: Automatic clock gating is disabled"]
658    Disabled = 0,
659    #[doc = "1: Automatic clock gating is enabled"]
660    Enabled = 1,
661}
662impl From<Port0> for bool {
663    #[inline(always)]
664    fn from(variant: Port0) -> Self {
665        variant as u8 != 0
666    }
667}
668#[doc = "Field `PORT0` reader - PORT0"]
669pub type Port0R = crate::BitReader<Port0>;
670impl Port0R {
671    #[doc = "Get enumerated values variant"]
672    #[inline(always)]
673    pub const fn variant(&self) -> Port0 {
674        match self.bits {
675            false => Port0::Disabled,
676            true => Port0::Enabled,
677        }
678    }
679    #[doc = "Automatic clock gating is disabled"]
680    #[inline(always)]
681    pub fn is_disabled(&self) -> bool {
682        *self == Port0::Disabled
683    }
684    #[doc = "Automatic clock gating is enabled"]
685    #[inline(always)]
686    pub fn is_enabled(&self) -> bool {
687        *self == Port0::Enabled
688    }
689}
690#[doc = "Field `PORT0` writer - PORT0"]
691pub type Port0W<'a, REG> = crate::BitWriter<'a, REG, Port0>;
692impl<'a, REG> Port0W<'a, REG>
693where
694    REG: crate::Writable + crate::RegisterSpec,
695{
696    #[doc = "Automatic clock gating is disabled"]
697    #[inline(always)]
698    pub fn disabled(self) -> &'a mut crate::W<REG> {
699        self.variant(Port0::Disabled)
700    }
701    #[doc = "Automatic clock gating is enabled"]
702    #[inline(always)]
703    pub fn enabled(self) -> &'a mut crate::W<REG> {
704        self.variant(Port0::Enabled)
705    }
706}
707#[doc = "PORT1\n\nValue on reset: 0"]
708#[cfg_attr(feature = "defmt", derive(defmt::Format))]
709#[derive(Clone, Copy, Debug, PartialEq, Eq)]
710pub enum Port1 {
711    #[doc = "0: Automatic clock gating is disabled"]
712    Disabled = 0,
713    #[doc = "1: Automatic clock gating is enabled"]
714    Enabled = 1,
715}
716impl From<Port1> for bool {
717    #[inline(always)]
718    fn from(variant: Port1) -> Self {
719        variant as u8 != 0
720    }
721}
722#[doc = "Field `PORT1` reader - PORT1"]
723pub type Port1R = crate::BitReader<Port1>;
724impl Port1R {
725    #[doc = "Get enumerated values variant"]
726    #[inline(always)]
727    pub const fn variant(&self) -> Port1 {
728        match self.bits {
729            false => Port1::Disabled,
730            true => Port1::Enabled,
731        }
732    }
733    #[doc = "Automatic clock gating is disabled"]
734    #[inline(always)]
735    pub fn is_disabled(&self) -> bool {
736        *self == Port1::Disabled
737    }
738    #[doc = "Automatic clock gating is enabled"]
739    #[inline(always)]
740    pub fn is_enabled(&self) -> bool {
741        *self == Port1::Enabled
742    }
743}
744#[doc = "Field `PORT1` writer - PORT1"]
745pub type Port1W<'a, REG> = crate::BitWriter<'a, REG, Port1>;
746impl<'a, REG> Port1W<'a, REG>
747where
748    REG: crate::Writable + crate::RegisterSpec,
749{
750    #[doc = "Automatic clock gating is disabled"]
751    #[inline(always)]
752    pub fn disabled(self) -> &'a mut crate::W<REG> {
753        self.variant(Port1::Disabled)
754    }
755    #[doc = "Automatic clock gating is enabled"]
756    #[inline(always)]
757    pub fn enabled(self) -> &'a mut crate::W<REG> {
758        self.variant(Port1::Enabled)
759    }
760}
761#[doc = "PORT2\n\nValue on reset: 0"]
762#[cfg_attr(feature = "defmt", derive(defmt::Format))]
763#[derive(Clone, Copy, Debug, PartialEq, Eq)]
764pub enum Port2 {
765    #[doc = "0: Automatic clock gating is disabled"]
766    Disabled = 0,
767    #[doc = "1: Automatic clock gating is enabled"]
768    Enabled = 1,
769}
770impl From<Port2> for bool {
771    #[inline(always)]
772    fn from(variant: Port2) -> Self {
773        variant as u8 != 0
774    }
775}
776#[doc = "Field `PORT2` reader - PORT2"]
777pub type Port2R = crate::BitReader<Port2>;
778impl Port2R {
779    #[doc = "Get enumerated values variant"]
780    #[inline(always)]
781    pub const fn variant(&self) -> Port2 {
782        match self.bits {
783            false => Port2::Disabled,
784            true => Port2::Enabled,
785        }
786    }
787    #[doc = "Automatic clock gating is disabled"]
788    #[inline(always)]
789    pub fn is_disabled(&self) -> bool {
790        *self == Port2::Disabled
791    }
792    #[doc = "Automatic clock gating is enabled"]
793    #[inline(always)]
794    pub fn is_enabled(&self) -> bool {
795        *self == Port2::Enabled
796    }
797}
798#[doc = "Field `PORT2` writer - PORT2"]
799pub type Port2W<'a, REG> = crate::BitWriter<'a, REG, Port2>;
800impl<'a, REG> Port2W<'a, REG>
801where
802    REG: crate::Writable + crate::RegisterSpec,
803{
804    #[doc = "Automatic clock gating is disabled"]
805    #[inline(always)]
806    pub fn disabled(self) -> &'a mut crate::W<REG> {
807        self.variant(Port2::Disabled)
808    }
809    #[doc = "Automatic clock gating is enabled"]
810    #[inline(always)]
811    pub fn enabled(self) -> &'a mut crate::W<REG> {
812        self.variant(Port2::Enabled)
813    }
814}
815#[doc = "PORT3\n\nValue on reset: 0"]
816#[cfg_attr(feature = "defmt", derive(defmt::Format))]
817#[derive(Clone, Copy, Debug, PartialEq, Eq)]
818pub enum Port3 {
819    #[doc = "0: Automatic clock gating is disabled"]
820    Disabled = 0,
821    #[doc = "1: Automatic clock gating is enabled"]
822    Enabled = 1,
823}
824impl From<Port3> for bool {
825    #[inline(always)]
826    fn from(variant: Port3) -> Self {
827        variant as u8 != 0
828    }
829}
830#[doc = "Field `PORT3` reader - PORT3"]
831pub type Port3R = crate::BitReader<Port3>;
832impl Port3R {
833    #[doc = "Get enumerated values variant"]
834    #[inline(always)]
835    pub const fn variant(&self) -> Port3 {
836        match self.bits {
837            false => Port3::Disabled,
838            true => Port3::Enabled,
839        }
840    }
841    #[doc = "Automatic clock gating is disabled"]
842    #[inline(always)]
843    pub fn is_disabled(&self) -> bool {
844        *self == Port3::Disabled
845    }
846    #[doc = "Automatic clock gating is enabled"]
847    #[inline(always)]
848    pub fn is_enabled(&self) -> bool {
849        *self == Port3::Enabled
850    }
851}
852#[doc = "Field `PORT3` writer - PORT3"]
853pub type Port3W<'a, REG> = crate::BitWriter<'a, REG, Port3>;
854impl<'a, REG> Port3W<'a, REG>
855where
856    REG: crate::Writable + crate::RegisterSpec,
857{
858    #[doc = "Automatic clock gating is disabled"]
859    #[inline(always)]
860    pub fn disabled(self) -> &'a mut crate::W<REG> {
861        self.variant(Port3::Disabled)
862    }
863    #[doc = "Automatic clock gating is enabled"]
864    #[inline(always)]
865    pub fn enabled(self) -> &'a mut crate::W<REG> {
866        self.variant(Port3::Enabled)
867    }
868}
869#[doc = "PORT4\n\nValue on reset: 0"]
870#[cfg_attr(feature = "defmt", derive(defmt::Format))]
871#[derive(Clone, Copy, Debug, PartialEq, Eq)]
872pub enum Port4 {
873    #[doc = "0: Automatic clock gating is disabled"]
874    Disabled = 0,
875    #[doc = "1: Automatic clock gating is enabled"]
876    Enabled = 1,
877}
878impl From<Port4> for bool {
879    #[inline(always)]
880    fn from(variant: Port4) -> Self {
881        variant as u8 != 0
882    }
883}
884#[doc = "Field `PORT4` reader - PORT4"]
885pub type Port4R = crate::BitReader<Port4>;
886impl Port4R {
887    #[doc = "Get enumerated values variant"]
888    #[inline(always)]
889    pub const fn variant(&self) -> Port4 {
890        match self.bits {
891            false => Port4::Disabled,
892            true => Port4::Enabled,
893        }
894    }
895    #[doc = "Automatic clock gating is disabled"]
896    #[inline(always)]
897    pub fn is_disabled(&self) -> bool {
898        *self == Port4::Disabled
899    }
900    #[doc = "Automatic clock gating is enabled"]
901    #[inline(always)]
902    pub fn is_enabled(&self) -> bool {
903        *self == Port4::Enabled
904    }
905}
906#[doc = "Field `PORT4` writer - PORT4"]
907pub type Port4W<'a, REG> = crate::BitWriter<'a, REG, Port4>;
908impl<'a, REG> Port4W<'a, REG>
909where
910    REG: crate::Writable + crate::RegisterSpec,
911{
912    #[doc = "Automatic clock gating is disabled"]
913    #[inline(always)]
914    pub fn disabled(self) -> &'a mut crate::W<REG> {
915        self.variant(Port4::Disabled)
916    }
917    #[doc = "Automatic clock gating is enabled"]
918    #[inline(always)]
919    pub fn enabled(self) -> &'a mut crate::W<REG> {
920        self.variant(Port4::Enabled)
921    }
922}
923#[doc = "SLCD0\n\nValue on reset: 0"]
924#[cfg_attr(feature = "defmt", derive(defmt::Format))]
925#[derive(Clone, Copy, Debug, PartialEq, Eq)]
926pub enum Slcd0 {
927    #[doc = "0: Automatic clock gating is disabled"]
928    Disabled = 0,
929    #[doc = "1: Automatic clock gating is enabled"]
930    Enabled = 1,
931}
932impl From<Slcd0> for bool {
933    #[inline(always)]
934    fn from(variant: Slcd0) -> Self {
935        variant as u8 != 0
936    }
937}
938#[doc = "Field `SLCD0` reader - SLCD0"]
939pub type Slcd0R = crate::BitReader<Slcd0>;
940impl Slcd0R {
941    #[doc = "Get enumerated values variant"]
942    #[inline(always)]
943    pub const fn variant(&self) -> Slcd0 {
944        match self.bits {
945            false => Slcd0::Disabled,
946            true => Slcd0::Enabled,
947        }
948    }
949    #[doc = "Automatic clock gating is disabled"]
950    #[inline(always)]
951    pub fn is_disabled(&self) -> bool {
952        *self == Slcd0::Disabled
953    }
954    #[doc = "Automatic clock gating is enabled"]
955    #[inline(always)]
956    pub fn is_enabled(&self) -> bool {
957        *self == Slcd0::Enabled
958    }
959}
960#[doc = "Field `SLCD0` writer - SLCD0"]
961pub type Slcd0W<'a, REG> = crate::BitWriter<'a, REG, Slcd0>;
962impl<'a, REG> Slcd0W<'a, REG>
963where
964    REG: crate::Writable + crate::RegisterSpec,
965{
966    #[doc = "Automatic clock gating is disabled"]
967    #[inline(always)]
968    pub fn disabled(self) -> &'a mut crate::W<REG> {
969        self.variant(Slcd0::Disabled)
970    }
971    #[doc = "Automatic clock gating is enabled"]
972    #[inline(always)]
973    pub fn enabled(self) -> &'a mut crate::W<REG> {
974        self.variant(Slcd0::Enabled)
975    }
976}
977#[doc = "FLEXCAN0\n\nValue on reset: 0"]
978#[cfg_attr(feature = "defmt", derive(defmt::Format))]
979#[derive(Clone, Copy, Debug, PartialEq, Eq)]
980pub enum Flexcan0 {
981    #[doc = "0: Automatic clock gating is disabled"]
982    Disabled = 0,
983    #[doc = "1: Automatic clock gating is enabled"]
984    Enabled = 1,
985}
986impl From<Flexcan0> for bool {
987    #[inline(always)]
988    fn from(variant: Flexcan0) -> Self {
989        variant as u8 != 0
990    }
991}
992#[doc = "Field `FLEXCAN0` reader - FLEXCAN0"]
993pub type Flexcan0R = crate::BitReader<Flexcan0>;
994impl Flexcan0R {
995    #[doc = "Get enumerated values variant"]
996    #[inline(always)]
997    pub const fn variant(&self) -> Flexcan0 {
998        match self.bits {
999            false => Flexcan0::Disabled,
1000            true => Flexcan0::Enabled,
1001        }
1002    }
1003    #[doc = "Automatic clock gating is disabled"]
1004    #[inline(always)]
1005    pub fn is_disabled(&self) -> bool {
1006        *self == Flexcan0::Disabled
1007    }
1008    #[doc = "Automatic clock gating is enabled"]
1009    #[inline(always)]
1010    pub fn is_enabled(&self) -> bool {
1011        *self == Flexcan0::Enabled
1012    }
1013}
1014#[doc = "Field `FLEXCAN0` writer - FLEXCAN0"]
1015pub type Flexcan0W<'a, REG> = crate::BitWriter<'a, REG, Flexcan0>;
1016impl<'a, REG> Flexcan0W<'a, REG>
1017where
1018    REG: crate::Writable + crate::RegisterSpec,
1019{
1020    #[doc = "Automatic clock gating is disabled"]
1021    #[inline(always)]
1022    pub fn disabled(self) -> &'a mut crate::W<REG> {
1023        self.variant(Flexcan0::Disabled)
1024    }
1025    #[doc = "Automatic clock gating is enabled"]
1026    #[inline(always)]
1027    pub fn enabled(self) -> &'a mut crate::W<REG> {
1028        self.variant(Flexcan0::Enabled)
1029    }
1030}
1031#[doc = "FLEXCAN1\n\nValue on reset: 0"]
1032#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1033#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1034pub enum Flexcan1 {
1035    #[doc = "0: Automatic clock gating is disabled"]
1036    Disabled = 0,
1037    #[doc = "1: Automatic clock gating is enabled"]
1038    Enabled = 1,
1039}
1040impl From<Flexcan1> for bool {
1041    #[inline(always)]
1042    fn from(variant: Flexcan1) -> Self {
1043        variant as u8 != 0
1044    }
1045}
1046#[doc = "Field `FLEXCAN1` reader - FLEXCAN1"]
1047pub type Flexcan1R = crate::BitReader<Flexcan1>;
1048impl Flexcan1R {
1049    #[doc = "Get enumerated values variant"]
1050    #[inline(always)]
1051    pub const fn variant(&self) -> Flexcan1 {
1052        match self.bits {
1053            false => Flexcan1::Disabled,
1054            true => Flexcan1::Enabled,
1055        }
1056    }
1057    #[doc = "Automatic clock gating is disabled"]
1058    #[inline(always)]
1059    pub fn is_disabled(&self) -> bool {
1060        *self == Flexcan1::Disabled
1061    }
1062    #[doc = "Automatic clock gating is enabled"]
1063    #[inline(always)]
1064    pub fn is_enabled(&self) -> bool {
1065        *self == Flexcan1::Enabled
1066    }
1067}
1068#[doc = "Field `FLEXCAN1` writer - FLEXCAN1"]
1069pub type Flexcan1W<'a, REG> = crate::BitWriter<'a, REG, Flexcan1>;
1070impl<'a, REG> Flexcan1W<'a, REG>
1071where
1072    REG: crate::Writable + crate::RegisterSpec,
1073{
1074    #[doc = "Automatic clock gating is disabled"]
1075    #[inline(always)]
1076    pub fn disabled(self) -> &'a mut crate::W<REG> {
1077        self.variant(Flexcan1::Disabled)
1078    }
1079    #[doc = "Automatic clock gating is enabled"]
1080    #[inline(always)]
1081    pub fn enabled(self) -> &'a mut crate::W<REG> {
1082        self.variant(Flexcan1::Enabled)
1083    }
1084}
1085#[doc = "LPI2C2\n\nValue on reset: 0"]
1086#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1087#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1088pub enum Lpi2c2 {
1089    #[doc = "0: Automatic clock gating is disabled"]
1090    Disabled = 0,
1091    #[doc = "1: Automatic clock gating is enabled"]
1092    Enabled = 1,
1093}
1094impl From<Lpi2c2> for bool {
1095    #[inline(always)]
1096    fn from(variant: Lpi2c2) -> Self {
1097        variant as u8 != 0
1098    }
1099}
1100#[doc = "Field `LPI2C2` reader - LPI2C2"]
1101pub type Lpi2c2R = crate::BitReader<Lpi2c2>;
1102impl Lpi2c2R {
1103    #[doc = "Get enumerated values variant"]
1104    #[inline(always)]
1105    pub const fn variant(&self) -> Lpi2c2 {
1106        match self.bits {
1107            false => Lpi2c2::Disabled,
1108            true => Lpi2c2::Enabled,
1109        }
1110    }
1111    #[doc = "Automatic clock gating is disabled"]
1112    #[inline(always)]
1113    pub fn is_disabled(&self) -> bool {
1114        *self == Lpi2c2::Disabled
1115    }
1116    #[doc = "Automatic clock gating is enabled"]
1117    #[inline(always)]
1118    pub fn is_enabled(&self) -> bool {
1119        *self == Lpi2c2::Enabled
1120    }
1121}
1122#[doc = "Field `LPI2C2` writer - LPI2C2"]
1123pub type Lpi2c2W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c2>;
1124impl<'a, REG> Lpi2c2W<'a, REG>
1125where
1126    REG: crate::Writable + crate::RegisterSpec,
1127{
1128    #[doc = "Automatic clock gating is disabled"]
1129    #[inline(always)]
1130    pub fn disabled(self) -> &'a mut crate::W<REG> {
1131        self.variant(Lpi2c2::Disabled)
1132    }
1133    #[doc = "Automatic clock gating is enabled"]
1134    #[inline(always)]
1135    pub fn enabled(self) -> &'a mut crate::W<REG> {
1136        self.variant(Lpi2c2::Enabled)
1137    }
1138}
1139#[doc = "LPI2C3\n\nValue on reset: 0"]
1140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1142pub enum Lpi2c3 {
1143    #[doc = "0: Automatic clock gating is disabled"]
1144    Disabled = 0,
1145    #[doc = "1: Automatic clock gating is enabled"]
1146    Enabled = 1,
1147}
1148impl From<Lpi2c3> for bool {
1149    #[inline(always)]
1150    fn from(variant: Lpi2c3) -> Self {
1151        variant as u8 != 0
1152    }
1153}
1154#[doc = "Field `LPI2C3` reader - LPI2C3"]
1155pub type Lpi2c3R = crate::BitReader<Lpi2c3>;
1156impl Lpi2c3R {
1157    #[doc = "Get enumerated values variant"]
1158    #[inline(always)]
1159    pub const fn variant(&self) -> Lpi2c3 {
1160        match self.bits {
1161            false => Lpi2c3::Disabled,
1162            true => Lpi2c3::Enabled,
1163        }
1164    }
1165    #[doc = "Automatic clock gating is disabled"]
1166    #[inline(always)]
1167    pub fn is_disabled(&self) -> bool {
1168        *self == Lpi2c3::Disabled
1169    }
1170    #[doc = "Automatic clock gating is enabled"]
1171    #[inline(always)]
1172    pub fn is_enabled(&self) -> bool {
1173        *self == Lpi2c3::Enabled
1174    }
1175}
1176#[doc = "Field `LPI2C3` writer - LPI2C3"]
1177pub type Lpi2c3W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c3>;
1178impl<'a, REG> Lpi2c3W<'a, REG>
1179where
1180    REG: crate::Writable + crate::RegisterSpec,
1181{
1182    #[doc = "Automatic clock gating is disabled"]
1183    #[inline(always)]
1184    pub fn disabled(self) -> &'a mut crate::W<REG> {
1185        self.variant(Lpi2c3::Disabled)
1186    }
1187    #[doc = "Automatic clock gating is enabled"]
1188    #[inline(always)]
1189    pub fn enabled(self) -> &'a mut crate::W<REG> {
1190        self.variant(Lpi2c3::Enabled)
1191    }
1192}
1193#[doc = "LPUART5\n\nValue on reset: 0"]
1194#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1195#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1196pub enum Lpuart5 {
1197    #[doc = "0: Automatic clock gating is disabled"]
1198    Disabled = 0,
1199    #[doc = "1: Automatic clock gating is enabled"]
1200    Enabled = 1,
1201}
1202impl From<Lpuart5> for bool {
1203    #[inline(always)]
1204    fn from(variant: Lpuart5) -> Self {
1205        variant as u8 != 0
1206    }
1207}
1208#[doc = "Field `LPUART5` reader - LPUART5"]
1209pub type Lpuart5R = crate::BitReader<Lpuart5>;
1210impl Lpuart5R {
1211    #[doc = "Get enumerated values variant"]
1212    #[inline(always)]
1213    pub const fn variant(&self) -> Lpuart5 {
1214        match self.bits {
1215            false => Lpuart5::Disabled,
1216            true => Lpuart5::Enabled,
1217        }
1218    }
1219    #[doc = "Automatic clock gating is disabled"]
1220    #[inline(always)]
1221    pub fn is_disabled(&self) -> bool {
1222        *self == Lpuart5::Disabled
1223    }
1224    #[doc = "Automatic clock gating is enabled"]
1225    #[inline(always)]
1226    pub fn is_enabled(&self) -> bool {
1227        *self == Lpuart5::Enabled
1228    }
1229}
1230#[doc = "Field `LPUART5` writer - LPUART5"]
1231pub type Lpuart5W<'a, REG> = crate::BitWriter<'a, REG, Lpuart5>;
1232impl<'a, REG> Lpuart5W<'a, REG>
1233where
1234    REG: crate::Writable + crate::RegisterSpec,
1235{
1236    #[doc = "Automatic clock gating is disabled"]
1237    #[inline(always)]
1238    pub fn disabled(self) -> &'a mut crate::W<REG> {
1239        self.variant(Lpuart5::Disabled)
1240    }
1241    #[doc = "Automatic clock gating is enabled"]
1242    #[inline(always)]
1243    pub fn enabled(self) -> &'a mut crate::W<REG> {
1244        self.variant(Lpuart5::Enabled)
1245    }
1246}
1247#[doc = "PKC0\n\nValue on reset: 0"]
1248#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1249#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1250pub enum Pkc0 {
1251    #[doc = "0: Automatic clock gating is disabled"]
1252    Disabled = 0,
1253    #[doc = "1: Automatic clock gating is enabled"]
1254    Enabled = 1,
1255}
1256impl From<Pkc0> for bool {
1257    #[inline(always)]
1258    fn from(variant: Pkc0) -> Self {
1259        variant as u8 != 0
1260    }
1261}
1262#[doc = "Field `PKC0` reader - PKC0"]
1263pub type Pkc0R = crate::BitReader<Pkc0>;
1264impl Pkc0R {
1265    #[doc = "Get enumerated values variant"]
1266    #[inline(always)]
1267    pub const fn variant(&self) -> Pkc0 {
1268        match self.bits {
1269            false => Pkc0::Disabled,
1270            true => Pkc0::Enabled,
1271        }
1272    }
1273    #[doc = "Automatic clock gating is disabled"]
1274    #[inline(always)]
1275    pub fn is_disabled(&self) -> bool {
1276        *self == Pkc0::Disabled
1277    }
1278    #[doc = "Automatic clock gating is enabled"]
1279    #[inline(always)]
1280    pub fn is_enabled(&self) -> bool {
1281        *self == Pkc0::Enabled
1282    }
1283}
1284#[doc = "Field `PKC0` writer - PKC0"]
1285pub type Pkc0W<'a, REG> = crate::BitWriter<'a, REG, Pkc0>;
1286impl<'a, REG> Pkc0W<'a, REG>
1287where
1288    REG: crate::Writable + crate::RegisterSpec,
1289{
1290    #[doc = "Automatic clock gating is disabled"]
1291    #[inline(always)]
1292    pub fn disabled(self) -> &'a mut crate::W<REG> {
1293        self.variant(Pkc0::Disabled)
1294    }
1295    #[doc = "Automatic clock gating is enabled"]
1296    #[inline(always)]
1297    pub fn enabled(self) -> &'a mut crate::W<REG> {
1298        self.variant(Pkc0::Enabled)
1299    }
1300}
1301#[doc = "SGI0\n\nValue on reset: 0"]
1302#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1303#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1304pub enum Sgi0 {
1305    #[doc = "0: Automatic clock gating is disabled"]
1306    Disabled = 0,
1307    #[doc = "1: Automatic clock gating is enabled"]
1308    Enabled = 1,
1309}
1310impl From<Sgi0> for bool {
1311    #[inline(always)]
1312    fn from(variant: Sgi0) -> Self {
1313        variant as u8 != 0
1314    }
1315}
1316#[doc = "Field `SGI0` reader - SGI0"]
1317pub type Sgi0R = crate::BitReader<Sgi0>;
1318impl Sgi0R {
1319    #[doc = "Get enumerated values variant"]
1320    #[inline(always)]
1321    pub const fn variant(&self) -> Sgi0 {
1322        match self.bits {
1323            false => Sgi0::Disabled,
1324            true => Sgi0::Enabled,
1325        }
1326    }
1327    #[doc = "Automatic clock gating is disabled"]
1328    #[inline(always)]
1329    pub fn is_disabled(&self) -> bool {
1330        *self == Sgi0::Disabled
1331    }
1332    #[doc = "Automatic clock gating is enabled"]
1333    #[inline(always)]
1334    pub fn is_enabled(&self) -> bool {
1335        *self == Sgi0::Enabled
1336    }
1337}
1338#[doc = "Field `SGI0` writer - SGI0"]
1339pub type Sgi0W<'a, REG> = crate::BitWriter<'a, REG, Sgi0>;
1340impl<'a, REG> Sgi0W<'a, REG>
1341where
1342    REG: crate::Writable + crate::RegisterSpec,
1343{
1344    #[doc = "Automatic clock gating is disabled"]
1345    #[inline(always)]
1346    pub fn disabled(self) -> &'a mut crate::W<REG> {
1347        self.variant(Sgi0::Disabled)
1348    }
1349    #[doc = "Automatic clock gating is enabled"]
1350    #[inline(always)]
1351    pub fn enabled(self) -> &'a mut crate::W<REG> {
1352        self.variant(Sgi0::Enabled)
1353    }
1354}
1355#[doc = "TRNG0\n\nValue on reset: 0"]
1356#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1357#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1358pub enum Trng0 {
1359    #[doc = "0: Automatic clock gating is disabled"]
1360    Disabled = 0,
1361    #[doc = "1: Automatic clock gating is enabled"]
1362    Enabled = 1,
1363}
1364impl From<Trng0> for bool {
1365    #[inline(always)]
1366    fn from(variant: Trng0) -> Self {
1367        variant as u8 != 0
1368    }
1369}
1370#[doc = "Field `TRNG0` reader - TRNG0"]
1371pub type Trng0R = crate::BitReader<Trng0>;
1372impl Trng0R {
1373    #[doc = "Get enumerated values variant"]
1374    #[inline(always)]
1375    pub const fn variant(&self) -> Trng0 {
1376        match self.bits {
1377            false => Trng0::Disabled,
1378            true => Trng0::Enabled,
1379        }
1380    }
1381    #[doc = "Automatic clock gating is disabled"]
1382    #[inline(always)]
1383    pub fn is_disabled(&self) -> bool {
1384        *self == Trng0::Disabled
1385    }
1386    #[doc = "Automatic clock gating is enabled"]
1387    #[inline(always)]
1388    pub fn is_enabled(&self) -> bool {
1389        *self == Trng0::Enabled
1390    }
1391}
1392#[doc = "Field `TRNG0` writer - TRNG0"]
1393pub type Trng0W<'a, REG> = crate::BitWriter<'a, REG, Trng0>;
1394impl<'a, REG> Trng0W<'a, REG>
1395where
1396    REG: crate::Writable + crate::RegisterSpec,
1397{
1398    #[doc = "Automatic clock gating is disabled"]
1399    #[inline(always)]
1400    pub fn disabled(self) -> &'a mut crate::W<REG> {
1401        self.variant(Trng0::Disabled)
1402    }
1403    #[doc = "Automatic clock gating is enabled"]
1404    #[inline(always)]
1405    pub fn enabled(self) -> &'a mut crate::W<REG> {
1406        self.variant(Trng0::Enabled)
1407    }
1408}
1409#[doc = "UDF0\n\nValue on reset: 0"]
1410#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1411#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1412pub enum Udf0 {
1413    #[doc = "0: Automatic clock gating is disabled"]
1414    Disabled = 0,
1415    #[doc = "1: Automatic clock gating is enabled"]
1416    Enabled = 1,
1417}
1418impl From<Udf0> for bool {
1419    #[inline(always)]
1420    fn from(variant: Udf0) -> Self {
1421        variant as u8 != 0
1422    }
1423}
1424#[doc = "Field `UDF0` reader - UDF0"]
1425pub type Udf0R = crate::BitReader<Udf0>;
1426impl Udf0R {
1427    #[doc = "Get enumerated values variant"]
1428    #[inline(always)]
1429    pub const fn variant(&self) -> Udf0 {
1430        match self.bits {
1431            false => Udf0::Disabled,
1432            true => Udf0::Enabled,
1433        }
1434    }
1435    #[doc = "Automatic clock gating is disabled"]
1436    #[inline(always)]
1437    pub fn is_disabled(&self) -> bool {
1438        *self == Udf0::Disabled
1439    }
1440    #[doc = "Automatic clock gating is enabled"]
1441    #[inline(always)]
1442    pub fn is_enabled(&self) -> bool {
1443        *self == Udf0::Enabled
1444    }
1445}
1446#[doc = "Field `UDF0` writer - UDF0"]
1447pub type Udf0W<'a, REG> = crate::BitWriter<'a, REG, Udf0>;
1448impl<'a, REG> Udf0W<'a, REG>
1449where
1450    REG: crate::Writable + crate::RegisterSpec,
1451{
1452    #[doc = "Automatic clock gating is disabled"]
1453    #[inline(always)]
1454    pub fn disabled(self) -> &'a mut crate::W<REG> {
1455        self.variant(Udf0::Disabled)
1456    }
1457    #[doc = "Automatic clock gating is enabled"]
1458    #[inline(always)]
1459    pub fn enabled(self) -> &'a mut crate::W<REG> {
1460        self.variant(Udf0::Enabled)
1461    }
1462}
1463#[doc = "ADC2\n\nValue on reset: 0"]
1464#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1465#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1466pub enum Adc2 {
1467    #[doc = "0: Automatic clock gating is disabled"]
1468    Disabled = 0,
1469    #[doc = "1: Automatic clock gating is enabled"]
1470    Enabled = 1,
1471}
1472impl From<Adc2> for bool {
1473    #[inline(always)]
1474    fn from(variant: Adc2) -> Self {
1475        variant as u8 != 0
1476    }
1477}
1478#[doc = "Field `ADC2` reader - ADC2"]
1479pub type Adc2R = crate::BitReader<Adc2>;
1480impl Adc2R {
1481    #[doc = "Get enumerated values variant"]
1482    #[inline(always)]
1483    pub const fn variant(&self) -> Adc2 {
1484        match self.bits {
1485            false => Adc2::Disabled,
1486            true => Adc2::Enabled,
1487        }
1488    }
1489    #[doc = "Automatic clock gating is disabled"]
1490    #[inline(always)]
1491    pub fn is_disabled(&self) -> bool {
1492        *self == Adc2::Disabled
1493    }
1494    #[doc = "Automatic clock gating is enabled"]
1495    #[inline(always)]
1496    pub fn is_enabled(&self) -> bool {
1497        *self == Adc2::Enabled
1498    }
1499}
1500#[doc = "Field `ADC2` writer - ADC2"]
1501pub type Adc2W<'a, REG> = crate::BitWriter<'a, REG, Adc2>;
1502impl<'a, REG> Adc2W<'a, REG>
1503where
1504    REG: crate::Writable + crate::RegisterSpec,
1505{
1506    #[doc = "Automatic clock gating is disabled"]
1507    #[inline(always)]
1508    pub fn disabled(self) -> &'a mut crate::W<REG> {
1509        self.variant(Adc2::Disabled)
1510    }
1511    #[doc = "Automatic clock gating is enabled"]
1512    #[inline(always)]
1513    pub fn enabled(self) -> &'a mut crate::W<REG> {
1514        self.variant(Adc2::Enabled)
1515    }
1516}
1517#[doc = "ADC3\n\nValue on reset: 0"]
1518#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1519#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1520pub enum Adc3 {
1521    #[doc = "0: Automatic clock gating is disabled"]
1522    Disabled = 0,
1523    #[doc = "1: Automatic clock gating is enabled"]
1524    Enabled = 1,
1525}
1526impl From<Adc3> for bool {
1527    #[inline(always)]
1528    fn from(variant: Adc3) -> Self {
1529        variant as u8 != 0
1530    }
1531}
1532#[doc = "Field `ADC3` reader - ADC3"]
1533pub type Adc3R = crate::BitReader<Adc3>;
1534impl Adc3R {
1535    #[doc = "Get enumerated values variant"]
1536    #[inline(always)]
1537    pub const fn variant(&self) -> Adc3 {
1538        match self.bits {
1539            false => Adc3::Disabled,
1540            true => Adc3::Enabled,
1541        }
1542    }
1543    #[doc = "Automatic clock gating is disabled"]
1544    #[inline(always)]
1545    pub fn is_disabled(&self) -> bool {
1546        *self == Adc3::Disabled
1547    }
1548    #[doc = "Automatic clock gating is enabled"]
1549    #[inline(always)]
1550    pub fn is_enabled(&self) -> bool {
1551        *self == Adc3::Enabled
1552    }
1553}
1554#[doc = "Field `ADC3` writer - ADC3"]
1555pub type Adc3W<'a, REG> = crate::BitWriter<'a, REG, Adc3>;
1556impl<'a, REG> Adc3W<'a, REG>
1557where
1558    REG: crate::Writable + crate::RegisterSpec,
1559{
1560    #[doc = "Automatic clock gating is disabled"]
1561    #[inline(always)]
1562    pub fn disabled(self) -> &'a mut crate::W<REG> {
1563        self.variant(Adc3::Disabled)
1564    }
1565    #[doc = "Automatic clock gating is enabled"]
1566    #[inline(always)]
1567    pub fn enabled(self) -> &'a mut crate::W<REG> {
1568        self.variant(Adc3::Enabled)
1569    }
1570}
1571impl R {
1572    #[doc = "Bit 0 - FLEXPWM1"]
1573    #[inline(always)]
1574    pub fn flexpwm1(&self) -> Flexpwm1R {
1575        Flexpwm1R::new((self.bits & 1) != 0)
1576    }
1577    #[doc = "Bit 1 - OSTIMER0"]
1578    #[inline(always)]
1579    pub fn ostimer0(&self) -> Ostimer0R {
1580        Ostimer0R::new(((self.bits >> 1) & 1) != 0)
1581    }
1582    #[doc = "Bit 2 - ADC0"]
1583    #[inline(always)]
1584    pub fn adc0(&self) -> Adc0R {
1585        Adc0R::new(((self.bits >> 2) & 1) != 0)
1586    }
1587    #[doc = "Bit 3 - ADC1"]
1588    #[inline(always)]
1589    pub fn adc1(&self) -> Adc1R {
1590        Adc1R::new(((self.bits >> 3) & 1) != 0)
1591    }
1592    #[doc = "Bit 4 - CMP0"]
1593    #[inline(always)]
1594    pub fn cmp0(&self) -> Cmp0R {
1595        Cmp0R::new(((self.bits >> 4) & 1) != 0)
1596    }
1597    #[doc = "Bit 5 - CMP1"]
1598    #[inline(always)]
1599    pub fn cmp1(&self) -> Cmp1R {
1600        Cmp1R::new(((self.bits >> 5) & 1) != 0)
1601    }
1602    #[doc = "Bit 6 - CMP2"]
1603    #[inline(always)]
1604    pub fn cmp2(&self) -> Cmp2R {
1605        Cmp2R::new(((self.bits >> 6) & 1) != 0)
1606    }
1607    #[doc = "Bit 7 - DAC0"]
1608    #[inline(always)]
1609    pub fn dac0(&self) -> Dac0R {
1610        Dac0R::new(((self.bits >> 7) & 1) != 0)
1611    }
1612    #[doc = "Bit 8 - OPAMP0"]
1613    #[inline(always)]
1614    pub fn opamp0(&self) -> Opamp0R {
1615        Opamp0R::new(((self.bits >> 8) & 1) != 0)
1616    }
1617    #[doc = "Bit 9 - OPAMP1"]
1618    #[inline(always)]
1619    pub fn opamp1(&self) -> Opamp1R {
1620        Opamp1R::new(((self.bits >> 9) & 1) != 0)
1621    }
1622    #[doc = "Bit 10 - OPAMP2"]
1623    #[inline(always)]
1624    pub fn opamp2(&self) -> Opamp2R {
1625        Opamp2R::new(((self.bits >> 10) & 1) != 0)
1626    }
1627    #[doc = "Bit 11 - OPAMP3"]
1628    #[inline(always)]
1629    pub fn opamp3(&self) -> Opamp3R {
1630        Opamp3R::new(((self.bits >> 11) & 1) != 0)
1631    }
1632    #[doc = "Bit 12 - PORT0"]
1633    #[inline(always)]
1634    pub fn port0(&self) -> Port0R {
1635        Port0R::new(((self.bits >> 12) & 1) != 0)
1636    }
1637    #[doc = "Bit 13 - PORT1"]
1638    #[inline(always)]
1639    pub fn port1(&self) -> Port1R {
1640        Port1R::new(((self.bits >> 13) & 1) != 0)
1641    }
1642    #[doc = "Bit 14 - PORT2"]
1643    #[inline(always)]
1644    pub fn port2(&self) -> Port2R {
1645        Port2R::new(((self.bits >> 14) & 1) != 0)
1646    }
1647    #[doc = "Bit 15 - PORT3"]
1648    #[inline(always)]
1649    pub fn port3(&self) -> Port3R {
1650        Port3R::new(((self.bits >> 15) & 1) != 0)
1651    }
1652    #[doc = "Bit 16 - PORT4"]
1653    #[inline(always)]
1654    pub fn port4(&self) -> Port4R {
1655        Port4R::new(((self.bits >> 16) & 1) != 0)
1656    }
1657    #[doc = "Bit 17 - SLCD0"]
1658    #[inline(always)]
1659    pub fn slcd0(&self) -> Slcd0R {
1660        Slcd0R::new(((self.bits >> 17) & 1) != 0)
1661    }
1662    #[doc = "Bit 18 - FLEXCAN0"]
1663    #[inline(always)]
1664    pub fn flexcan0(&self) -> Flexcan0R {
1665        Flexcan0R::new(((self.bits >> 18) & 1) != 0)
1666    }
1667    #[doc = "Bit 19 - FLEXCAN1"]
1668    #[inline(always)]
1669    pub fn flexcan1(&self) -> Flexcan1R {
1670        Flexcan1R::new(((self.bits >> 19) & 1) != 0)
1671    }
1672    #[doc = "Bit 20 - LPI2C2"]
1673    #[inline(always)]
1674    pub fn lpi2c2(&self) -> Lpi2c2R {
1675        Lpi2c2R::new(((self.bits >> 20) & 1) != 0)
1676    }
1677    #[doc = "Bit 21 - LPI2C3"]
1678    #[inline(always)]
1679    pub fn lpi2c3(&self) -> Lpi2c3R {
1680        Lpi2c3R::new(((self.bits >> 21) & 1) != 0)
1681    }
1682    #[doc = "Bit 22 - LPUART5"]
1683    #[inline(always)]
1684    pub fn lpuart5(&self) -> Lpuart5R {
1685        Lpuart5R::new(((self.bits >> 22) & 1) != 0)
1686    }
1687    #[doc = "Bit 24 - PKC0"]
1688    #[inline(always)]
1689    pub fn pkc0(&self) -> Pkc0R {
1690        Pkc0R::new(((self.bits >> 24) & 1) != 0)
1691    }
1692    #[doc = "Bit 25 - SGI0"]
1693    #[inline(always)]
1694    pub fn sgi0(&self) -> Sgi0R {
1695        Sgi0R::new(((self.bits >> 25) & 1) != 0)
1696    }
1697    #[doc = "Bit 26 - TRNG0"]
1698    #[inline(always)]
1699    pub fn trng0(&self) -> Trng0R {
1700        Trng0R::new(((self.bits >> 26) & 1) != 0)
1701    }
1702    #[doc = "Bit 27 - UDF0"]
1703    #[inline(always)]
1704    pub fn udf0(&self) -> Udf0R {
1705        Udf0R::new(((self.bits >> 27) & 1) != 0)
1706    }
1707    #[doc = "Bit 28 - ADC2"]
1708    #[inline(always)]
1709    pub fn adc2(&self) -> Adc2R {
1710        Adc2R::new(((self.bits >> 28) & 1) != 0)
1711    }
1712    #[doc = "Bit 29 - ADC3"]
1713    #[inline(always)]
1714    pub fn adc3(&self) -> Adc3R {
1715        Adc3R::new(((self.bits >> 29) & 1) != 0)
1716    }
1717}
1718#[cfg(feature = "debug")]
1719impl core::fmt::Debug for R {
1720    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1721        f.debug_struct("MRCC_GLB_ACC1")
1722            .field("flexpwm1", &self.flexpwm1())
1723            .field("ostimer0", &self.ostimer0())
1724            .field("adc0", &self.adc0())
1725            .field("adc1", &self.adc1())
1726            .field("cmp0", &self.cmp0())
1727            .field("cmp1", &self.cmp1())
1728            .field("cmp2", &self.cmp2())
1729            .field("dac0", &self.dac0())
1730            .field("opamp0", &self.opamp0())
1731            .field("opamp1", &self.opamp1())
1732            .field("opamp2", &self.opamp2())
1733            .field("opamp3", &self.opamp3())
1734            .field("port0", &self.port0())
1735            .field("port1", &self.port1())
1736            .field("port2", &self.port2())
1737            .field("port3", &self.port3())
1738            .field("port4", &self.port4())
1739            .field("slcd0", &self.slcd0())
1740            .field("flexcan0", &self.flexcan0())
1741            .field("flexcan1", &self.flexcan1())
1742            .field("lpi2c2", &self.lpi2c2())
1743            .field("lpi2c3", &self.lpi2c3())
1744            .field("lpuart5", &self.lpuart5())
1745            .field("pkc0", &self.pkc0())
1746            .field("sgi0", &self.sgi0())
1747            .field("trng0", &self.trng0())
1748            .field("udf0", &self.udf0())
1749            .field("adc2", &self.adc2())
1750            .field("adc3", &self.adc3())
1751            .finish()
1752    }
1753}
1754impl W {
1755    #[doc = "Bit 0 - FLEXPWM1"]
1756    #[inline(always)]
1757    pub fn flexpwm1(&mut self) -> Flexpwm1W<'_, MrccGlbAcc1Spec> {
1758        Flexpwm1W::new(self, 0)
1759    }
1760    #[doc = "Bit 1 - OSTIMER0"]
1761    #[inline(always)]
1762    pub fn ostimer0(&mut self) -> Ostimer0W<'_, MrccGlbAcc1Spec> {
1763        Ostimer0W::new(self, 1)
1764    }
1765    #[doc = "Bit 2 - ADC0"]
1766    #[inline(always)]
1767    pub fn adc0(&mut self) -> Adc0W<'_, MrccGlbAcc1Spec> {
1768        Adc0W::new(self, 2)
1769    }
1770    #[doc = "Bit 3 - ADC1"]
1771    #[inline(always)]
1772    pub fn adc1(&mut self) -> Adc1W<'_, MrccGlbAcc1Spec> {
1773        Adc1W::new(self, 3)
1774    }
1775    #[doc = "Bit 4 - CMP0"]
1776    #[inline(always)]
1777    pub fn cmp0(&mut self) -> Cmp0W<'_, MrccGlbAcc1Spec> {
1778        Cmp0W::new(self, 4)
1779    }
1780    #[doc = "Bit 5 - CMP1"]
1781    #[inline(always)]
1782    pub fn cmp1(&mut self) -> Cmp1W<'_, MrccGlbAcc1Spec> {
1783        Cmp1W::new(self, 5)
1784    }
1785    #[doc = "Bit 6 - CMP2"]
1786    #[inline(always)]
1787    pub fn cmp2(&mut self) -> Cmp2W<'_, MrccGlbAcc1Spec> {
1788        Cmp2W::new(self, 6)
1789    }
1790    #[doc = "Bit 7 - DAC0"]
1791    #[inline(always)]
1792    pub fn dac0(&mut self) -> Dac0W<'_, MrccGlbAcc1Spec> {
1793        Dac0W::new(self, 7)
1794    }
1795    #[doc = "Bit 8 - OPAMP0"]
1796    #[inline(always)]
1797    pub fn opamp0(&mut self) -> Opamp0W<'_, MrccGlbAcc1Spec> {
1798        Opamp0W::new(self, 8)
1799    }
1800    #[doc = "Bit 9 - OPAMP1"]
1801    #[inline(always)]
1802    pub fn opamp1(&mut self) -> Opamp1W<'_, MrccGlbAcc1Spec> {
1803        Opamp1W::new(self, 9)
1804    }
1805    #[doc = "Bit 10 - OPAMP2"]
1806    #[inline(always)]
1807    pub fn opamp2(&mut self) -> Opamp2W<'_, MrccGlbAcc1Spec> {
1808        Opamp2W::new(self, 10)
1809    }
1810    #[doc = "Bit 11 - OPAMP3"]
1811    #[inline(always)]
1812    pub fn opamp3(&mut self) -> Opamp3W<'_, MrccGlbAcc1Spec> {
1813        Opamp3W::new(self, 11)
1814    }
1815    #[doc = "Bit 12 - PORT0"]
1816    #[inline(always)]
1817    pub fn port0(&mut self) -> Port0W<'_, MrccGlbAcc1Spec> {
1818        Port0W::new(self, 12)
1819    }
1820    #[doc = "Bit 13 - PORT1"]
1821    #[inline(always)]
1822    pub fn port1(&mut self) -> Port1W<'_, MrccGlbAcc1Spec> {
1823        Port1W::new(self, 13)
1824    }
1825    #[doc = "Bit 14 - PORT2"]
1826    #[inline(always)]
1827    pub fn port2(&mut self) -> Port2W<'_, MrccGlbAcc1Spec> {
1828        Port2W::new(self, 14)
1829    }
1830    #[doc = "Bit 15 - PORT3"]
1831    #[inline(always)]
1832    pub fn port3(&mut self) -> Port3W<'_, MrccGlbAcc1Spec> {
1833        Port3W::new(self, 15)
1834    }
1835    #[doc = "Bit 16 - PORT4"]
1836    #[inline(always)]
1837    pub fn port4(&mut self) -> Port4W<'_, MrccGlbAcc1Spec> {
1838        Port4W::new(self, 16)
1839    }
1840    #[doc = "Bit 17 - SLCD0"]
1841    #[inline(always)]
1842    pub fn slcd0(&mut self) -> Slcd0W<'_, MrccGlbAcc1Spec> {
1843        Slcd0W::new(self, 17)
1844    }
1845    #[doc = "Bit 18 - FLEXCAN0"]
1846    #[inline(always)]
1847    pub fn flexcan0(&mut self) -> Flexcan0W<'_, MrccGlbAcc1Spec> {
1848        Flexcan0W::new(self, 18)
1849    }
1850    #[doc = "Bit 19 - FLEXCAN1"]
1851    #[inline(always)]
1852    pub fn flexcan1(&mut self) -> Flexcan1W<'_, MrccGlbAcc1Spec> {
1853        Flexcan1W::new(self, 19)
1854    }
1855    #[doc = "Bit 20 - LPI2C2"]
1856    #[inline(always)]
1857    pub fn lpi2c2(&mut self) -> Lpi2c2W<'_, MrccGlbAcc1Spec> {
1858        Lpi2c2W::new(self, 20)
1859    }
1860    #[doc = "Bit 21 - LPI2C3"]
1861    #[inline(always)]
1862    pub fn lpi2c3(&mut self) -> Lpi2c3W<'_, MrccGlbAcc1Spec> {
1863        Lpi2c3W::new(self, 21)
1864    }
1865    #[doc = "Bit 22 - LPUART5"]
1866    #[inline(always)]
1867    pub fn lpuart5(&mut self) -> Lpuart5W<'_, MrccGlbAcc1Spec> {
1868        Lpuart5W::new(self, 22)
1869    }
1870    #[doc = "Bit 24 - PKC0"]
1871    #[inline(always)]
1872    pub fn pkc0(&mut self) -> Pkc0W<'_, MrccGlbAcc1Spec> {
1873        Pkc0W::new(self, 24)
1874    }
1875    #[doc = "Bit 25 - SGI0"]
1876    #[inline(always)]
1877    pub fn sgi0(&mut self) -> Sgi0W<'_, MrccGlbAcc1Spec> {
1878        Sgi0W::new(self, 25)
1879    }
1880    #[doc = "Bit 26 - TRNG0"]
1881    #[inline(always)]
1882    pub fn trng0(&mut self) -> Trng0W<'_, MrccGlbAcc1Spec> {
1883        Trng0W::new(self, 26)
1884    }
1885    #[doc = "Bit 27 - UDF0"]
1886    #[inline(always)]
1887    pub fn udf0(&mut self) -> Udf0W<'_, MrccGlbAcc1Spec> {
1888        Udf0W::new(self, 27)
1889    }
1890    #[doc = "Bit 28 - ADC2"]
1891    #[inline(always)]
1892    pub fn adc2(&mut self) -> Adc2W<'_, MrccGlbAcc1Spec> {
1893        Adc2W::new(self, 28)
1894    }
1895    #[doc = "Bit 29 - ADC3"]
1896    #[inline(always)]
1897    pub fn adc3(&mut self) -> Adc3W<'_, MrccGlbAcc1Spec> {
1898        Adc3W::new(self, 29)
1899    }
1900}
1901#[doc = "Control Automatic Clock Gating 1\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1902pub struct MrccGlbAcc1Spec;
1903impl crate::RegisterSpec for MrccGlbAcc1Spec {
1904    type Ux = u32;
1905}
1906#[doc = "`read()` method returns [`mrcc_glb_acc1::R`](R) reader structure"]
1907impl crate::Readable for MrccGlbAcc1Spec {}
1908#[doc = "`write(|w| ..)` method takes [`mrcc_glb_acc1::W`](W) writer structure"]
1909impl crate::Writable for MrccGlbAcc1Spec {
1910    type Safety = crate::Unsafe;
1911}
1912#[doc = "`reset()` method sets MRCC_GLB_ACC1 to value 0"]
1913impl crate::Resettable for MrccGlbAcc1Spec {}
mcxa_pac/mrcc0/mrcc_glb_acc1.rs

mcxa_pac/mrcc0/
mrcc_glb_acc1.rs
