mcxa_pac/mrcc0/
mrcc_glb_acc0.rs

1#[doc = "Register `MRCC_GLB_ACC0` reader"]
2pub type R = crate::R<MrccGlbAcc0Spec>;
3#[doc = "Register `MRCC_GLB_ACC0` writer"]
4pub type W = crate::W<MrccGlbAcc0Spec>;
5#[doc = "INPUTMUX0\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Inputmux0 {
9    #[doc = "0: Automatic clock gating is disabled"]
10    Disabled = 0,
11    #[doc = "1: Automatic clock gating is enabled"]
12    Enabled = 1,
13}
14impl From<Inputmux0> for bool {
15    #[inline(always)]
16    fn from(variant: Inputmux0) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `INPUTMUX0` reader - INPUTMUX0"]
21pub type Inputmux0R = crate::BitReader<Inputmux0>;
22impl Inputmux0R {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Inputmux0 {
26        match self.bits {
27            false => Inputmux0::Disabled,
28            true => Inputmux0::Enabled,
29        }
30    }
31    #[doc = "Automatic clock gating is disabled"]
32    #[inline(always)]
33    pub fn is_disabled(&self) -> bool {
34        *self == Inputmux0::Disabled
35    }
36    #[doc = "Automatic clock gating is enabled"]
37    #[inline(always)]
38    pub fn is_enabled(&self) -> bool {
39        *self == Inputmux0::Enabled
40    }
41}
42#[doc = "Field `INPUTMUX0` writer - INPUTMUX0"]
43pub type Inputmux0W<'a, REG> = crate::BitWriter<'a, REG, Inputmux0>;
44impl<'a, REG> Inputmux0W<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Automatic clock gating is disabled"]
49    #[inline(always)]
50    pub fn disabled(self) -> &'a mut crate::W<REG> {
51        self.variant(Inputmux0::Disabled)
52    }
53    #[doc = "Automatic clock gating is enabled"]
54    #[inline(always)]
55    pub fn enabled(self) -> &'a mut crate::W<REG> {
56        self.variant(Inputmux0::Enabled)
57    }
58}
59#[doc = "I3C0\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum I3c0 {
63    #[doc = "0: Automatic clock gating is disabled"]
64    Disabled = 0,
65    #[doc = "1: Automatic clock gating is enabled"]
66    Enabled = 1,
67}
68impl From<I3c0> for bool {
69    #[inline(always)]
70    fn from(variant: I3c0) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `I3C0` reader - I3C0"]
75pub type I3c0R = crate::BitReader<I3c0>;
76impl I3c0R {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> I3c0 {
80        match self.bits {
81            false => I3c0::Disabled,
82            true => I3c0::Enabled,
83        }
84    }
85    #[doc = "Automatic clock gating is disabled"]
86    #[inline(always)]
87    pub fn is_disabled(&self) -> bool {
88        *self == I3c0::Disabled
89    }
90    #[doc = "Automatic clock gating is enabled"]
91    #[inline(always)]
92    pub fn is_enabled(&self) -> bool {
93        *self == I3c0::Enabled
94    }
95}
96#[doc = "Field `I3C0` writer - I3C0"]
97pub type I3c0W<'a, REG> = crate::BitWriter<'a, REG, I3c0>;
98impl<'a, REG> I3c0W<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "Automatic clock gating is disabled"]
103    #[inline(always)]
104    pub fn disabled(self) -> &'a mut crate::W<REG> {
105        self.variant(I3c0::Disabled)
106    }
107    #[doc = "Automatic clock gating is enabled"]
108    #[inline(always)]
109    pub fn enabled(self) -> &'a mut crate::W<REG> {
110        self.variant(I3c0::Enabled)
111    }
112}
113#[doc = "CTIMER0\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Ctimer0 {
117    #[doc = "0: Automatic clock gating is disabled"]
118    Disabled = 0,
119    #[doc = "1: Automatic clock gating is enabled"]
120    Enabled = 1,
121}
122impl From<Ctimer0> for bool {
123    #[inline(always)]
124    fn from(variant: Ctimer0) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `CTIMER0` reader - CTIMER0"]
129pub type Ctimer0R = crate::BitReader<Ctimer0>;
130impl Ctimer0R {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Ctimer0 {
134        match self.bits {
135            false => Ctimer0::Disabled,
136            true => Ctimer0::Enabled,
137        }
138    }
139    #[doc = "Automatic clock gating is disabled"]
140    #[inline(always)]
141    pub fn is_disabled(&self) -> bool {
142        *self == Ctimer0::Disabled
143    }
144    #[doc = "Automatic clock gating is enabled"]
145    #[inline(always)]
146    pub fn is_enabled(&self) -> bool {
147        *self == Ctimer0::Enabled
148    }
149}
150#[doc = "Field `CTIMER0` writer - CTIMER0"]
151pub type Ctimer0W<'a, REG> = crate::BitWriter<'a, REG, Ctimer0>;
152impl<'a, REG> Ctimer0W<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Automatic clock gating is disabled"]
157    #[inline(always)]
158    pub fn disabled(self) -> &'a mut crate::W<REG> {
159        self.variant(Ctimer0::Disabled)
160    }
161    #[doc = "Automatic clock gating is enabled"]
162    #[inline(always)]
163    pub fn enabled(self) -> &'a mut crate::W<REG> {
164        self.variant(Ctimer0::Enabled)
165    }
166}
167#[doc = "CTIMER1\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Ctimer1 {
171    #[doc = "0: Automatic clock gating is disabled"]
172    Disabled = 0,
173    #[doc = "1: Automatic clock gating is enabled"]
174    Enabled = 1,
175}
176impl From<Ctimer1> for bool {
177    #[inline(always)]
178    fn from(variant: Ctimer1) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `CTIMER1` reader - CTIMER1"]
183pub type Ctimer1R = crate::BitReader<Ctimer1>;
184impl Ctimer1R {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Ctimer1 {
188        match self.bits {
189            false => Ctimer1::Disabled,
190            true => Ctimer1::Enabled,
191        }
192    }
193    #[doc = "Automatic clock gating is disabled"]
194    #[inline(always)]
195    pub fn is_disabled(&self) -> bool {
196        *self == Ctimer1::Disabled
197    }
198    #[doc = "Automatic clock gating is enabled"]
199    #[inline(always)]
200    pub fn is_enabled(&self) -> bool {
201        *self == Ctimer1::Enabled
202    }
203}
204#[doc = "Field `CTIMER1` writer - CTIMER1"]
205pub type Ctimer1W<'a, REG> = crate::BitWriter<'a, REG, Ctimer1>;
206impl<'a, REG> Ctimer1W<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Automatic clock gating is disabled"]
211    #[inline(always)]
212    pub fn disabled(self) -> &'a mut crate::W<REG> {
213        self.variant(Ctimer1::Disabled)
214    }
215    #[doc = "Automatic clock gating is enabled"]
216    #[inline(always)]
217    pub fn enabled(self) -> &'a mut crate::W<REG> {
218        self.variant(Ctimer1::Enabled)
219    }
220}
221#[doc = "CTIMER2\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum Ctimer2 {
225    #[doc = "0: Automatic clock gating is disabled"]
226    Disabled = 0,
227    #[doc = "1: Automatic clock gating is enabled"]
228    Enabled = 1,
229}
230impl From<Ctimer2> for bool {
231    #[inline(always)]
232    fn from(variant: Ctimer2) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `CTIMER2` reader - CTIMER2"]
237pub type Ctimer2R = crate::BitReader<Ctimer2>;
238impl Ctimer2R {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> Ctimer2 {
242        match self.bits {
243            false => Ctimer2::Disabled,
244            true => Ctimer2::Enabled,
245        }
246    }
247    #[doc = "Automatic clock gating is disabled"]
248    #[inline(always)]
249    pub fn is_disabled(&self) -> bool {
250        *self == Ctimer2::Disabled
251    }
252    #[doc = "Automatic clock gating is enabled"]
253    #[inline(always)]
254    pub fn is_enabled(&self) -> bool {
255        *self == Ctimer2::Enabled
256    }
257}
258#[doc = "Field `CTIMER2` writer - CTIMER2"]
259pub type Ctimer2W<'a, REG> = crate::BitWriter<'a, REG, Ctimer2>;
260impl<'a, REG> Ctimer2W<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263{
264    #[doc = "Automatic clock gating is disabled"]
265    #[inline(always)]
266    pub fn disabled(self) -> &'a mut crate::W<REG> {
267        self.variant(Ctimer2::Disabled)
268    }
269    #[doc = "Automatic clock gating is enabled"]
270    #[inline(always)]
271    pub fn enabled(self) -> &'a mut crate::W<REG> {
272        self.variant(Ctimer2::Enabled)
273    }
274}
275#[doc = "CTIMER3\n\nValue on reset: 0"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum Ctimer3 {
279    #[doc = "0: Automatic clock gating is disabled"]
280    Disabled = 0,
281    #[doc = "1: Automatic clock gating is enabled"]
282    Enabled = 1,
283}
284impl From<Ctimer3> for bool {
285    #[inline(always)]
286    fn from(variant: Ctimer3) -> Self {
287        variant as u8 != 0
288    }
289}
290#[doc = "Field `CTIMER3` reader - CTIMER3"]
291pub type Ctimer3R = crate::BitReader<Ctimer3>;
292impl Ctimer3R {
293    #[doc = "Get enumerated values variant"]
294    #[inline(always)]
295    pub const fn variant(&self) -> Ctimer3 {
296        match self.bits {
297            false => Ctimer3::Disabled,
298            true => Ctimer3::Enabled,
299        }
300    }
301    #[doc = "Automatic clock gating is disabled"]
302    #[inline(always)]
303    pub fn is_disabled(&self) -> bool {
304        *self == Ctimer3::Disabled
305    }
306    #[doc = "Automatic clock gating is enabled"]
307    #[inline(always)]
308    pub fn is_enabled(&self) -> bool {
309        *self == Ctimer3::Enabled
310    }
311}
312#[doc = "Field `CTIMER3` writer - CTIMER3"]
313pub type Ctimer3W<'a, REG> = crate::BitWriter<'a, REG, Ctimer3>;
314impl<'a, REG> Ctimer3W<'a, REG>
315where
316    REG: crate::Writable + crate::RegisterSpec,
317{
318    #[doc = "Automatic clock gating is disabled"]
319    #[inline(always)]
320    pub fn disabled(self) -> &'a mut crate::W<REG> {
321        self.variant(Ctimer3::Disabled)
322    }
323    #[doc = "Automatic clock gating is enabled"]
324    #[inline(always)]
325    pub fn enabled(self) -> &'a mut crate::W<REG> {
326        self.variant(Ctimer3::Enabled)
327    }
328}
329#[doc = "CTIMER4\n\nValue on reset: 0"]
330#[cfg_attr(feature = "defmt", derive(defmt::Format))]
331#[derive(Clone, Copy, Debug, PartialEq, Eq)]
332pub enum Ctimer4 {
333    #[doc = "0: Automatic clock gating is disabled"]
334    Disabled = 0,
335    #[doc = "1: Automatic clock gating is enabled"]
336    Enabled = 1,
337}
338impl From<Ctimer4> for bool {
339    #[inline(always)]
340    fn from(variant: Ctimer4) -> Self {
341        variant as u8 != 0
342    }
343}
344#[doc = "Field `CTIMER4` reader - CTIMER4"]
345pub type Ctimer4R = crate::BitReader<Ctimer4>;
346impl Ctimer4R {
347    #[doc = "Get enumerated values variant"]
348    #[inline(always)]
349    pub const fn variant(&self) -> Ctimer4 {
350        match self.bits {
351            false => Ctimer4::Disabled,
352            true => Ctimer4::Enabled,
353        }
354    }
355    #[doc = "Automatic clock gating is disabled"]
356    #[inline(always)]
357    pub fn is_disabled(&self) -> bool {
358        *self == Ctimer4::Disabled
359    }
360    #[doc = "Automatic clock gating is enabled"]
361    #[inline(always)]
362    pub fn is_enabled(&self) -> bool {
363        *self == Ctimer4::Enabled
364    }
365}
366#[doc = "Field `CTIMER4` writer - CTIMER4"]
367pub type Ctimer4W<'a, REG> = crate::BitWriter<'a, REG, Ctimer4>;
368impl<'a, REG> Ctimer4W<'a, REG>
369where
370    REG: crate::Writable + crate::RegisterSpec,
371{
372    #[doc = "Automatic clock gating is disabled"]
373    #[inline(always)]
374    pub fn disabled(self) -> &'a mut crate::W<REG> {
375        self.variant(Ctimer4::Disabled)
376    }
377    #[doc = "Automatic clock gating is enabled"]
378    #[inline(always)]
379    pub fn enabled(self) -> &'a mut crate::W<REG> {
380        self.variant(Ctimer4::Enabled)
381    }
382}
383#[doc = "FREQME\n\nValue on reset: 0"]
384#[cfg_attr(feature = "defmt", derive(defmt::Format))]
385#[derive(Clone, Copy, Debug, PartialEq, Eq)]
386pub enum Freqme {
387    #[doc = "0: Automatic clock gating is disabled"]
388    Disabled = 0,
389    #[doc = "1: Automatic clock gating is enabled"]
390    Enabled = 1,
391}
392impl From<Freqme> for bool {
393    #[inline(always)]
394    fn from(variant: Freqme) -> Self {
395        variant as u8 != 0
396    }
397}
398#[doc = "Field `FREQME` reader - FREQME"]
399pub type FreqmeR = crate::BitReader<Freqme>;
400impl FreqmeR {
401    #[doc = "Get enumerated values variant"]
402    #[inline(always)]
403    pub const fn variant(&self) -> Freqme {
404        match self.bits {
405            false => Freqme::Disabled,
406            true => Freqme::Enabled,
407        }
408    }
409    #[doc = "Automatic clock gating is disabled"]
410    #[inline(always)]
411    pub fn is_disabled(&self) -> bool {
412        *self == Freqme::Disabled
413    }
414    #[doc = "Automatic clock gating is enabled"]
415    #[inline(always)]
416    pub fn is_enabled(&self) -> bool {
417        *self == Freqme::Enabled
418    }
419}
420#[doc = "Field `FREQME` writer - FREQME"]
421pub type FreqmeW<'a, REG> = crate::BitWriter<'a, REG, Freqme>;
422impl<'a, REG> FreqmeW<'a, REG>
423where
424    REG: crate::Writable + crate::RegisterSpec,
425{
426    #[doc = "Automatic clock gating is disabled"]
427    #[inline(always)]
428    pub fn disabled(self) -> &'a mut crate::W<REG> {
429        self.variant(Freqme::Disabled)
430    }
431    #[doc = "Automatic clock gating is enabled"]
432    #[inline(always)]
433    pub fn enabled(self) -> &'a mut crate::W<REG> {
434        self.variant(Freqme::Enabled)
435    }
436}
437#[doc = "UTICK0\n\nValue on reset: 0"]
438#[cfg_attr(feature = "defmt", derive(defmt::Format))]
439#[derive(Clone, Copy, Debug, PartialEq, Eq)]
440pub enum Utick0 {
441    #[doc = "0: Automatic clock gating is disabled"]
442    Disabled = 0,
443    #[doc = "1: Automatic clock gating is enabled"]
444    Enabled = 1,
445}
446impl From<Utick0> for bool {
447    #[inline(always)]
448    fn from(variant: Utick0) -> Self {
449        variant as u8 != 0
450    }
451}
452#[doc = "Field `UTICK0` reader - UTICK0"]
453pub type Utick0R = crate::BitReader<Utick0>;
454impl Utick0R {
455    #[doc = "Get enumerated values variant"]
456    #[inline(always)]
457    pub const fn variant(&self) -> Utick0 {
458        match self.bits {
459            false => Utick0::Disabled,
460            true => Utick0::Enabled,
461        }
462    }
463    #[doc = "Automatic clock gating is disabled"]
464    #[inline(always)]
465    pub fn is_disabled(&self) -> bool {
466        *self == Utick0::Disabled
467    }
468    #[doc = "Automatic clock gating is enabled"]
469    #[inline(always)]
470    pub fn is_enabled(&self) -> bool {
471        *self == Utick0::Enabled
472    }
473}
474#[doc = "Field `UTICK0` writer - UTICK0"]
475pub type Utick0W<'a, REG> = crate::BitWriter<'a, REG, Utick0>;
476impl<'a, REG> Utick0W<'a, REG>
477where
478    REG: crate::Writable + crate::RegisterSpec,
479{
480    #[doc = "Automatic clock gating is disabled"]
481    #[inline(always)]
482    pub fn disabled(self) -> &'a mut crate::W<REG> {
483        self.variant(Utick0::Disabled)
484    }
485    #[doc = "Automatic clock gating is enabled"]
486    #[inline(always)]
487    pub fn enabled(self) -> &'a mut crate::W<REG> {
488        self.variant(Utick0::Enabled)
489    }
490}
491#[doc = "WWDT0\n\nValue on reset: 1"]
492#[cfg_attr(feature = "defmt", derive(defmt::Format))]
493#[derive(Clone, Copy, Debug, PartialEq, Eq)]
494pub enum Wwdt0 {
495    #[doc = "0: Automatic clock gating is disabled"]
496    Disabled = 0,
497    #[doc = "1: Automatic clock gating is enabled"]
498    Enabled = 1,
499}
500impl From<Wwdt0> for bool {
501    #[inline(always)]
502    fn from(variant: Wwdt0) -> Self {
503        variant as u8 != 0
504    }
505}
506#[doc = "Field `WWDT0` reader - WWDT0"]
507pub type Wwdt0R = crate::BitReader<Wwdt0>;
508impl Wwdt0R {
509    #[doc = "Get enumerated values variant"]
510    #[inline(always)]
511    pub const fn variant(&self) -> Wwdt0 {
512        match self.bits {
513            false => Wwdt0::Disabled,
514            true => Wwdt0::Enabled,
515        }
516    }
517    #[doc = "Automatic clock gating is disabled"]
518    #[inline(always)]
519    pub fn is_disabled(&self) -> bool {
520        *self == Wwdt0::Disabled
521    }
522    #[doc = "Automatic clock gating is enabled"]
523    #[inline(always)]
524    pub fn is_enabled(&self) -> bool {
525        *self == Wwdt0::Enabled
526    }
527}
528#[doc = "Field `WWDT0` writer - WWDT0"]
529pub type Wwdt0W<'a, REG> = crate::BitWriter<'a, REG, Wwdt0>;
530impl<'a, REG> Wwdt0W<'a, REG>
531where
532    REG: crate::Writable + crate::RegisterSpec,
533{
534    #[doc = "Automatic clock gating is disabled"]
535    #[inline(always)]
536    pub fn disabled(self) -> &'a mut crate::W<REG> {
537        self.variant(Wwdt0::Disabled)
538    }
539    #[doc = "Automatic clock gating is enabled"]
540    #[inline(always)]
541    pub fn enabled(self) -> &'a mut crate::W<REG> {
542        self.variant(Wwdt0::Enabled)
543    }
544}
545#[doc = "SMARTDMA0\n\nValue on reset: 0"]
546#[cfg_attr(feature = "defmt", derive(defmt::Format))]
547#[derive(Clone, Copy, Debug, PartialEq, Eq)]
548pub enum Smartdma0 {
549    #[doc = "0: Automatic clock gating is disabled"]
550    Disabled = 0,
551    #[doc = "1: Automatic clock gating is enabled"]
552    Enabled = 1,
553}
554impl From<Smartdma0> for bool {
555    #[inline(always)]
556    fn from(variant: Smartdma0) -> Self {
557        variant as u8 != 0
558    }
559}
560#[doc = "Field `SMARTDMA0` reader - SMARTDMA0"]
561pub type Smartdma0R = crate::BitReader<Smartdma0>;
562impl Smartdma0R {
563    #[doc = "Get enumerated values variant"]
564    #[inline(always)]
565    pub const fn variant(&self) -> Smartdma0 {
566        match self.bits {
567            false => Smartdma0::Disabled,
568            true => Smartdma0::Enabled,
569        }
570    }
571    #[doc = "Automatic clock gating is disabled"]
572    #[inline(always)]
573    pub fn is_disabled(&self) -> bool {
574        *self == Smartdma0::Disabled
575    }
576    #[doc = "Automatic clock gating is enabled"]
577    #[inline(always)]
578    pub fn is_enabled(&self) -> bool {
579        *self == Smartdma0::Enabled
580    }
581}
582#[doc = "Field `SMARTDMA0` writer - SMARTDMA0"]
583pub type Smartdma0W<'a, REG> = crate::BitWriter<'a, REG, Smartdma0>;
584impl<'a, REG> Smartdma0W<'a, REG>
585where
586    REG: crate::Writable + crate::RegisterSpec,
587{
588    #[doc = "Automatic clock gating is disabled"]
589    #[inline(always)]
590    pub fn disabled(self) -> &'a mut crate::W<REG> {
591        self.variant(Smartdma0::Disabled)
592    }
593    #[doc = "Automatic clock gating is enabled"]
594    #[inline(always)]
595    pub fn enabled(self) -> &'a mut crate::W<REG> {
596        self.variant(Smartdma0::Enabled)
597    }
598}
599#[doc = "DMA0\n\nValue on reset: 0"]
600#[cfg_attr(feature = "defmt", derive(defmt::Format))]
601#[derive(Clone, Copy, Debug, PartialEq, Eq)]
602pub enum Dma0 {
603    #[doc = "0: Automatic clock gating is disabled"]
604    Disabled = 0,
605    #[doc = "1: Automatic clock gating is enabled"]
606    Enabled = 1,
607}
608impl From<Dma0> for bool {
609    #[inline(always)]
610    fn from(variant: Dma0) -> Self {
611        variant as u8 != 0
612    }
613}
614#[doc = "Field `DMA0` reader - DMA0"]
615pub type Dma0R = crate::BitReader<Dma0>;
616impl Dma0R {
617    #[doc = "Get enumerated values variant"]
618    #[inline(always)]
619    pub const fn variant(&self) -> Dma0 {
620        match self.bits {
621            false => Dma0::Disabled,
622            true => Dma0::Enabled,
623        }
624    }
625    #[doc = "Automatic clock gating is disabled"]
626    #[inline(always)]
627    pub fn is_disabled(&self) -> bool {
628        *self == Dma0::Disabled
629    }
630    #[doc = "Automatic clock gating is enabled"]
631    #[inline(always)]
632    pub fn is_enabled(&self) -> bool {
633        *self == Dma0::Enabled
634    }
635}
636#[doc = "Field `DMA0` writer - DMA0"]
637pub type Dma0W<'a, REG> = crate::BitWriter<'a, REG, Dma0>;
638impl<'a, REG> Dma0W<'a, REG>
639where
640    REG: crate::Writable + crate::RegisterSpec,
641{
642    #[doc = "Automatic clock gating is disabled"]
643    #[inline(always)]
644    pub fn disabled(self) -> &'a mut crate::W<REG> {
645        self.variant(Dma0::Disabled)
646    }
647    #[doc = "Automatic clock gating is enabled"]
648    #[inline(always)]
649    pub fn enabled(self) -> &'a mut crate::W<REG> {
650        self.variant(Dma0::Enabled)
651    }
652}
653#[doc = "AOI0\n\nValue on reset: 0"]
654#[cfg_attr(feature = "defmt", derive(defmt::Format))]
655#[derive(Clone, Copy, Debug, PartialEq, Eq)]
656pub enum Aoi0 {
657    #[doc = "0: Automatic clock gating is disabled"]
658    Disabled = 0,
659    #[doc = "1: Automatic clock gating is enabled"]
660    Enabled = 1,
661}
662impl From<Aoi0> for bool {
663    #[inline(always)]
664    fn from(variant: Aoi0) -> Self {
665        variant as u8 != 0
666    }
667}
668#[doc = "Field `AOI0` reader - AOI0"]
669pub type Aoi0R = crate::BitReader<Aoi0>;
670impl Aoi0R {
671    #[doc = "Get enumerated values variant"]
672    #[inline(always)]
673    pub const fn variant(&self) -> Aoi0 {
674        match self.bits {
675            false => Aoi0::Disabled,
676            true => Aoi0::Enabled,
677        }
678    }
679    #[doc = "Automatic clock gating is disabled"]
680    #[inline(always)]
681    pub fn is_disabled(&self) -> bool {
682        *self == Aoi0::Disabled
683    }
684    #[doc = "Automatic clock gating is enabled"]
685    #[inline(always)]
686    pub fn is_enabled(&self) -> bool {
687        *self == Aoi0::Enabled
688    }
689}
690#[doc = "Field `AOI0` writer - AOI0"]
691pub type Aoi0W<'a, REG> = crate::BitWriter<'a, REG, Aoi0>;
692impl<'a, REG> Aoi0W<'a, REG>
693where
694    REG: crate::Writable + crate::RegisterSpec,
695{
696    #[doc = "Automatic clock gating is disabled"]
697    #[inline(always)]
698    pub fn disabled(self) -> &'a mut crate::W<REG> {
699        self.variant(Aoi0::Disabled)
700    }
701    #[doc = "Automatic clock gating is enabled"]
702    #[inline(always)]
703    pub fn enabled(self) -> &'a mut crate::W<REG> {
704        self.variant(Aoi0::Enabled)
705    }
706}
707#[doc = "CRC0\n\nValue on reset: 0"]
708#[cfg_attr(feature = "defmt", derive(defmt::Format))]
709#[derive(Clone, Copy, Debug, PartialEq, Eq)]
710pub enum Crc0 {
711    #[doc = "0: Automatic clock gating is disabled"]
712    Disabled = 0,
713    #[doc = "1: Automatic clock gating is enabled"]
714    Enabled = 1,
715}
716impl From<Crc0> for bool {
717    #[inline(always)]
718    fn from(variant: Crc0) -> Self {
719        variant as u8 != 0
720    }
721}
722#[doc = "Field `CRC0` reader - CRC0"]
723pub type Crc0R = crate::BitReader<Crc0>;
724impl Crc0R {
725    #[doc = "Get enumerated values variant"]
726    #[inline(always)]
727    pub const fn variant(&self) -> Crc0 {
728        match self.bits {
729            false => Crc0::Disabled,
730            true => Crc0::Enabled,
731        }
732    }
733    #[doc = "Automatic clock gating is disabled"]
734    #[inline(always)]
735    pub fn is_disabled(&self) -> bool {
736        *self == Crc0::Disabled
737    }
738    #[doc = "Automatic clock gating is enabled"]
739    #[inline(always)]
740    pub fn is_enabled(&self) -> bool {
741        *self == Crc0::Enabled
742    }
743}
744#[doc = "Field `CRC0` writer - CRC0"]
745pub type Crc0W<'a, REG> = crate::BitWriter<'a, REG, Crc0>;
746impl<'a, REG> Crc0W<'a, REG>
747where
748    REG: crate::Writable + crate::RegisterSpec,
749{
750    #[doc = "Automatic clock gating is disabled"]
751    #[inline(always)]
752    pub fn disabled(self) -> &'a mut crate::W<REG> {
753        self.variant(Crc0::Disabled)
754    }
755    #[doc = "Automatic clock gating is enabled"]
756    #[inline(always)]
757    pub fn enabled(self) -> &'a mut crate::W<REG> {
758        self.variant(Crc0::Enabled)
759    }
760}
761#[doc = "EIM0\n\nValue on reset: 0"]
762#[cfg_attr(feature = "defmt", derive(defmt::Format))]
763#[derive(Clone, Copy, Debug, PartialEq, Eq)]
764pub enum Eim0 {
765    #[doc = "0: Automatic clock gating is disabled"]
766    Disabled = 0,
767    #[doc = "1: Automatic clock gating is enabled"]
768    Enabled = 1,
769}
770impl From<Eim0> for bool {
771    #[inline(always)]
772    fn from(variant: Eim0) -> Self {
773        variant as u8 != 0
774    }
775}
776#[doc = "Field `EIM0` reader - EIM0"]
777pub type Eim0R = crate::BitReader<Eim0>;
778impl Eim0R {
779    #[doc = "Get enumerated values variant"]
780    #[inline(always)]
781    pub const fn variant(&self) -> Eim0 {
782        match self.bits {
783            false => Eim0::Disabled,
784            true => Eim0::Enabled,
785        }
786    }
787    #[doc = "Automatic clock gating is disabled"]
788    #[inline(always)]
789    pub fn is_disabled(&self) -> bool {
790        *self == Eim0::Disabled
791    }
792    #[doc = "Automatic clock gating is enabled"]
793    #[inline(always)]
794    pub fn is_enabled(&self) -> bool {
795        *self == Eim0::Enabled
796    }
797}
798#[doc = "Field `EIM0` writer - EIM0"]
799pub type Eim0W<'a, REG> = crate::BitWriter<'a, REG, Eim0>;
800impl<'a, REG> Eim0W<'a, REG>
801where
802    REG: crate::Writable + crate::RegisterSpec,
803{
804    #[doc = "Automatic clock gating is disabled"]
805    #[inline(always)]
806    pub fn disabled(self) -> &'a mut crate::W<REG> {
807        self.variant(Eim0::Disabled)
808    }
809    #[doc = "Automatic clock gating is enabled"]
810    #[inline(always)]
811    pub fn enabled(self) -> &'a mut crate::W<REG> {
812        self.variant(Eim0::Enabled)
813    }
814}
815#[doc = "ERM0\n\nValue on reset: 0"]
816#[cfg_attr(feature = "defmt", derive(defmt::Format))]
817#[derive(Clone, Copy, Debug, PartialEq, Eq)]
818pub enum Erm0 {
819    #[doc = "0: Automatic clock gating is disabled"]
820    Disabled = 0,
821    #[doc = "1: Automatic clock gating is enabled"]
822    Enabled = 1,
823}
824impl From<Erm0> for bool {
825    #[inline(always)]
826    fn from(variant: Erm0) -> Self {
827        variant as u8 != 0
828    }
829}
830#[doc = "Field `ERM0` reader - ERM0"]
831pub type Erm0R = crate::BitReader<Erm0>;
832impl Erm0R {
833    #[doc = "Get enumerated values variant"]
834    #[inline(always)]
835    pub const fn variant(&self) -> Erm0 {
836        match self.bits {
837            false => Erm0::Disabled,
838            true => Erm0::Enabled,
839        }
840    }
841    #[doc = "Automatic clock gating is disabled"]
842    #[inline(always)]
843    pub fn is_disabled(&self) -> bool {
844        *self == Erm0::Disabled
845    }
846    #[doc = "Automatic clock gating is enabled"]
847    #[inline(always)]
848    pub fn is_enabled(&self) -> bool {
849        *self == Erm0::Enabled
850    }
851}
852#[doc = "Field `ERM0` writer - ERM0"]
853pub type Erm0W<'a, REG> = crate::BitWriter<'a, REG, Erm0>;
854impl<'a, REG> Erm0W<'a, REG>
855where
856    REG: crate::Writable + crate::RegisterSpec,
857{
858    #[doc = "Automatic clock gating is disabled"]
859    #[inline(always)]
860    pub fn disabled(self) -> &'a mut crate::W<REG> {
861        self.variant(Erm0::Disabled)
862    }
863    #[doc = "Automatic clock gating is enabled"]
864    #[inline(always)]
865    pub fn enabled(self) -> &'a mut crate::W<REG> {
866        self.variant(Erm0::Enabled)
867    }
868}
869#[doc = "FMC\n\nValue on reset: 1"]
870#[cfg_attr(feature = "defmt", derive(defmt::Format))]
871#[derive(Clone, Copy, Debug, PartialEq, Eq)]
872pub enum Fmc {
873    #[doc = "0: Automatic clock gating is disabled"]
874    Disabled = 0,
875    #[doc = "1: Automatic clock gating is enabled"]
876    Enabled = 1,
877}
878impl From<Fmc> for bool {
879    #[inline(always)]
880    fn from(variant: Fmc) -> Self {
881        variant as u8 != 0
882    }
883}
884#[doc = "Field `FMC` reader - FMC"]
885pub type FmcR = crate::BitReader<Fmc>;
886impl FmcR {
887    #[doc = "Get enumerated values variant"]
888    #[inline(always)]
889    pub const fn variant(&self) -> Fmc {
890        match self.bits {
891            false => Fmc::Disabled,
892            true => Fmc::Enabled,
893        }
894    }
895    #[doc = "Automatic clock gating is disabled"]
896    #[inline(always)]
897    pub fn is_disabled(&self) -> bool {
898        *self == Fmc::Disabled
899    }
900    #[doc = "Automatic clock gating is enabled"]
901    #[inline(always)]
902    pub fn is_enabled(&self) -> bool {
903        *self == Fmc::Enabled
904    }
905}
906#[doc = "Field `FMC` writer - FMC"]
907pub type FmcW<'a, REG> = crate::BitWriter<'a, REG, Fmc>;
908impl<'a, REG> FmcW<'a, REG>
909where
910    REG: crate::Writable + crate::RegisterSpec,
911{
912    #[doc = "Automatic clock gating is disabled"]
913    #[inline(always)]
914    pub fn disabled(self) -> &'a mut crate::W<REG> {
915        self.variant(Fmc::Disabled)
916    }
917    #[doc = "Automatic clock gating is enabled"]
918    #[inline(always)]
919    pub fn enabled(self) -> &'a mut crate::W<REG> {
920        self.variant(Fmc::Enabled)
921    }
922}
923#[doc = "AOI1\n\nValue on reset: 0"]
924#[cfg_attr(feature = "defmt", derive(defmt::Format))]
925#[derive(Clone, Copy, Debug, PartialEq, Eq)]
926pub enum Aoi1 {
927    #[doc = "0: Automatic clock gating is disabled"]
928    Disabled = 0,
929    #[doc = "1: Automatic clock gating is enabled"]
930    Enabled = 1,
931}
932impl From<Aoi1> for bool {
933    #[inline(always)]
934    fn from(variant: Aoi1) -> Self {
935        variant as u8 != 0
936    }
937}
938#[doc = "Field `AOI1` reader - AOI1"]
939pub type Aoi1R = crate::BitReader<Aoi1>;
940impl Aoi1R {
941    #[doc = "Get enumerated values variant"]
942    #[inline(always)]
943    pub const fn variant(&self) -> Aoi1 {
944        match self.bits {
945            false => Aoi1::Disabled,
946            true => Aoi1::Enabled,
947        }
948    }
949    #[doc = "Automatic clock gating is disabled"]
950    #[inline(always)]
951    pub fn is_disabled(&self) -> bool {
952        *self == Aoi1::Disabled
953    }
954    #[doc = "Automatic clock gating is enabled"]
955    #[inline(always)]
956    pub fn is_enabled(&self) -> bool {
957        *self == Aoi1::Enabled
958    }
959}
960#[doc = "Field `AOI1` writer - AOI1"]
961pub type Aoi1W<'a, REG> = crate::BitWriter<'a, REG, Aoi1>;
962impl<'a, REG> Aoi1W<'a, REG>
963where
964    REG: crate::Writable + crate::RegisterSpec,
965{
966    #[doc = "Automatic clock gating is disabled"]
967    #[inline(always)]
968    pub fn disabled(self) -> &'a mut crate::W<REG> {
969        self.variant(Aoi1::Disabled)
970    }
971    #[doc = "Automatic clock gating is enabled"]
972    #[inline(always)]
973    pub fn enabled(self) -> &'a mut crate::W<REG> {
974        self.variant(Aoi1::Enabled)
975    }
976}
977#[doc = "FLEXIO0\n\nValue on reset: 0"]
978#[cfg_attr(feature = "defmt", derive(defmt::Format))]
979#[derive(Clone, Copy, Debug, PartialEq, Eq)]
980pub enum Flexio0 {
981    #[doc = "0: Automatic clock gating is disabled"]
982    Disabled = 0,
983    #[doc = "1: Automatic clock gating is enabled"]
984    Enabled = 1,
985}
986impl From<Flexio0> for bool {
987    #[inline(always)]
988    fn from(variant: Flexio0) -> Self {
989        variant as u8 != 0
990    }
991}
992#[doc = "Field `FLEXIO0` reader - FLEXIO0"]
993pub type Flexio0R = crate::BitReader<Flexio0>;
994impl Flexio0R {
995    #[doc = "Get enumerated values variant"]
996    #[inline(always)]
997    pub const fn variant(&self) -> Flexio0 {
998        match self.bits {
999            false => Flexio0::Disabled,
1000            true => Flexio0::Enabled,
1001        }
1002    }
1003    #[doc = "Automatic clock gating is disabled"]
1004    #[inline(always)]
1005    pub fn is_disabled(&self) -> bool {
1006        *self == Flexio0::Disabled
1007    }
1008    #[doc = "Automatic clock gating is enabled"]
1009    #[inline(always)]
1010    pub fn is_enabled(&self) -> bool {
1011        *self == Flexio0::Enabled
1012    }
1013}
1014#[doc = "Field `FLEXIO0` writer - FLEXIO0"]
1015pub type Flexio0W<'a, REG> = crate::BitWriter<'a, REG, Flexio0>;
1016impl<'a, REG> Flexio0W<'a, REG>
1017where
1018    REG: crate::Writable + crate::RegisterSpec,
1019{
1020    #[doc = "Automatic clock gating is disabled"]
1021    #[inline(always)]
1022    pub fn disabled(self) -> &'a mut crate::W<REG> {
1023        self.variant(Flexio0::Disabled)
1024    }
1025    #[doc = "Automatic clock gating is enabled"]
1026    #[inline(always)]
1027    pub fn enabled(self) -> &'a mut crate::W<REG> {
1028        self.variant(Flexio0::Enabled)
1029    }
1030}
1031#[doc = "LPI2C0\n\nValue on reset: 0"]
1032#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1033#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1034pub enum Lpi2c0 {
1035    #[doc = "0: Automatic clock gating is disabled"]
1036    Disabled = 0,
1037    #[doc = "1: Automatic clock gating is enabled"]
1038    Enabled = 1,
1039}
1040impl From<Lpi2c0> for bool {
1041    #[inline(always)]
1042    fn from(variant: Lpi2c0) -> Self {
1043        variant as u8 != 0
1044    }
1045}
1046#[doc = "Field `LPI2C0` reader - LPI2C0"]
1047pub type Lpi2c0R = crate::BitReader<Lpi2c0>;
1048impl Lpi2c0R {
1049    #[doc = "Get enumerated values variant"]
1050    #[inline(always)]
1051    pub const fn variant(&self) -> Lpi2c0 {
1052        match self.bits {
1053            false => Lpi2c0::Disabled,
1054            true => Lpi2c0::Enabled,
1055        }
1056    }
1057    #[doc = "Automatic clock gating is disabled"]
1058    #[inline(always)]
1059    pub fn is_disabled(&self) -> bool {
1060        *self == Lpi2c0::Disabled
1061    }
1062    #[doc = "Automatic clock gating is enabled"]
1063    #[inline(always)]
1064    pub fn is_enabled(&self) -> bool {
1065        *self == Lpi2c0::Enabled
1066    }
1067}
1068#[doc = "Field `LPI2C0` writer - LPI2C0"]
1069pub type Lpi2c0W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c0>;
1070impl<'a, REG> Lpi2c0W<'a, REG>
1071where
1072    REG: crate::Writable + crate::RegisterSpec,
1073{
1074    #[doc = "Automatic clock gating is disabled"]
1075    #[inline(always)]
1076    pub fn disabled(self) -> &'a mut crate::W<REG> {
1077        self.variant(Lpi2c0::Disabled)
1078    }
1079    #[doc = "Automatic clock gating is enabled"]
1080    #[inline(always)]
1081    pub fn enabled(self) -> &'a mut crate::W<REG> {
1082        self.variant(Lpi2c0::Enabled)
1083    }
1084}
1085#[doc = "LPI2C1\n\nValue on reset: 0"]
1086#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1087#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1088pub enum Lpi2c1 {
1089    #[doc = "0: Automatic clock gating is disabled"]
1090    Disabled = 0,
1091    #[doc = "1: Automatic clock gating is enabled"]
1092    Enabled = 1,
1093}
1094impl From<Lpi2c1> for bool {
1095    #[inline(always)]
1096    fn from(variant: Lpi2c1) -> Self {
1097        variant as u8 != 0
1098    }
1099}
1100#[doc = "Field `LPI2C1` reader - LPI2C1"]
1101pub type Lpi2c1R = crate::BitReader<Lpi2c1>;
1102impl Lpi2c1R {
1103    #[doc = "Get enumerated values variant"]
1104    #[inline(always)]
1105    pub const fn variant(&self) -> Lpi2c1 {
1106        match self.bits {
1107            false => Lpi2c1::Disabled,
1108            true => Lpi2c1::Enabled,
1109        }
1110    }
1111    #[doc = "Automatic clock gating is disabled"]
1112    #[inline(always)]
1113    pub fn is_disabled(&self) -> bool {
1114        *self == Lpi2c1::Disabled
1115    }
1116    #[doc = "Automatic clock gating is enabled"]
1117    #[inline(always)]
1118    pub fn is_enabled(&self) -> bool {
1119        *self == Lpi2c1::Enabled
1120    }
1121}
1122#[doc = "Field `LPI2C1` writer - LPI2C1"]
1123pub type Lpi2c1W<'a, REG> = crate::BitWriter<'a, REG, Lpi2c1>;
1124impl<'a, REG> Lpi2c1W<'a, REG>
1125where
1126    REG: crate::Writable + crate::RegisterSpec,
1127{
1128    #[doc = "Automatic clock gating is disabled"]
1129    #[inline(always)]
1130    pub fn disabled(self) -> &'a mut crate::W<REG> {
1131        self.variant(Lpi2c1::Disabled)
1132    }
1133    #[doc = "Automatic clock gating is enabled"]
1134    #[inline(always)]
1135    pub fn enabled(self) -> &'a mut crate::W<REG> {
1136        self.variant(Lpi2c1::Enabled)
1137    }
1138}
1139#[doc = "LPSPI0\n\nValue on reset: 0"]
1140#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1141#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1142pub enum Lpspi0 {
1143    #[doc = "0: Automatic clock gating is disabled"]
1144    Disabled = 0,
1145    #[doc = "1: Automatic clock gating is enabled"]
1146    Enabled = 1,
1147}
1148impl From<Lpspi0> for bool {
1149    #[inline(always)]
1150    fn from(variant: Lpspi0) -> Self {
1151        variant as u8 != 0
1152    }
1153}
1154#[doc = "Field `LPSPI0` reader - LPSPI0"]
1155pub type Lpspi0R = crate::BitReader<Lpspi0>;
1156impl Lpspi0R {
1157    #[doc = "Get enumerated values variant"]
1158    #[inline(always)]
1159    pub const fn variant(&self) -> Lpspi0 {
1160        match self.bits {
1161            false => Lpspi0::Disabled,
1162            true => Lpspi0::Enabled,
1163        }
1164    }
1165    #[doc = "Automatic clock gating is disabled"]
1166    #[inline(always)]
1167    pub fn is_disabled(&self) -> bool {
1168        *self == Lpspi0::Disabled
1169    }
1170    #[doc = "Automatic clock gating is enabled"]
1171    #[inline(always)]
1172    pub fn is_enabled(&self) -> bool {
1173        *self == Lpspi0::Enabled
1174    }
1175}
1176#[doc = "Field `LPSPI0` writer - LPSPI0"]
1177pub type Lpspi0W<'a, REG> = crate::BitWriter<'a, REG, Lpspi0>;
1178impl<'a, REG> Lpspi0W<'a, REG>
1179where
1180    REG: crate::Writable + crate::RegisterSpec,
1181{
1182    #[doc = "Automatic clock gating is disabled"]
1183    #[inline(always)]
1184    pub fn disabled(self) -> &'a mut crate::W<REG> {
1185        self.variant(Lpspi0::Disabled)
1186    }
1187    #[doc = "Automatic clock gating is enabled"]
1188    #[inline(always)]
1189    pub fn enabled(self) -> &'a mut crate::W<REG> {
1190        self.variant(Lpspi0::Enabled)
1191    }
1192}
1193#[doc = "LPSPI1\n\nValue on reset: 0"]
1194#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1195#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1196pub enum Lpspi1 {
1197    #[doc = "0: Automatic clock gating is disabled"]
1198    Disabled = 0,
1199    #[doc = "1: Automatic clock gating is enabled"]
1200    Enabled = 1,
1201}
1202impl From<Lpspi1> for bool {
1203    #[inline(always)]
1204    fn from(variant: Lpspi1) -> Self {
1205        variant as u8 != 0
1206    }
1207}
1208#[doc = "Field `LPSPI1` reader - LPSPI1"]
1209pub type Lpspi1R = crate::BitReader<Lpspi1>;
1210impl Lpspi1R {
1211    #[doc = "Get enumerated values variant"]
1212    #[inline(always)]
1213    pub const fn variant(&self) -> Lpspi1 {
1214        match self.bits {
1215            false => Lpspi1::Disabled,
1216            true => Lpspi1::Enabled,
1217        }
1218    }
1219    #[doc = "Automatic clock gating is disabled"]
1220    #[inline(always)]
1221    pub fn is_disabled(&self) -> bool {
1222        *self == Lpspi1::Disabled
1223    }
1224    #[doc = "Automatic clock gating is enabled"]
1225    #[inline(always)]
1226    pub fn is_enabled(&self) -> bool {
1227        *self == Lpspi1::Enabled
1228    }
1229}
1230#[doc = "Field `LPSPI1` writer - LPSPI1"]
1231pub type Lpspi1W<'a, REG> = crate::BitWriter<'a, REG, Lpspi1>;
1232impl<'a, REG> Lpspi1W<'a, REG>
1233where
1234    REG: crate::Writable + crate::RegisterSpec,
1235{
1236    #[doc = "Automatic clock gating is disabled"]
1237    #[inline(always)]
1238    pub fn disabled(self) -> &'a mut crate::W<REG> {
1239        self.variant(Lpspi1::Disabled)
1240    }
1241    #[doc = "Automatic clock gating is enabled"]
1242    #[inline(always)]
1243    pub fn enabled(self) -> &'a mut crate::W<REG> {
1244        self.variant(Lpspi1::Enabled)
1245    }
1246}
1247#[doc = "LPUART0\n\nValue on reset: 0"]
1248#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1249#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1250pub enum Lpuart0 {
1251    #[doc = "0: Automatic clock gating is disabled"]
1252    Disabled = 0,
1253    #[doc = "1: Automatic clock gating is enabled"]
1254    Enabled = 1,
1255}
1256impl From<Lpuart0> for bool {
1257    #[inline(always)]
1258    fn from(variant: Lpuart0) -> Self {
1259        variant as u8 != 0
1260    }
1261}
1262#[doc = "Field `LPUART0` reader - LPUART0"]
1263pub type Lpuart0R = crate::BitReader<Lpuart0>;
1264impl Lpuart0R {
1265    #[doc = "Get enumerated values variant"]
1266    #[inline(always)]
1267    pub const fn variant(&self) -> Lpuart0 {
1268        match self.bits {
1269            false => Lpuart0::Disabled,
1270            true => Lpuart0::Enabled,
1271        }
1272    }
1273    #[doc = "Automatic clock gating is disabled"]
1274    #[inline(always)]
1275    pub fn is_disabled(&self) -> bool {
1276        *self == Lpuart0::Disabled
1277    }
1278    #[doc = "Automatic clock gating is enabled"]
1279    #[inline(always)]
1280    pub fn is_enabled(&self) -> bool {
1281        *self == Lpuart0::Enabled
1282    }
1283}
1284#[doc = "Field `LPUART0` writer - LPUART0"]
1285pub type Lpuart0W<'a, REG> = crate::BitWriter<'a, REG, Lpuart0>;
1286impl<'a, REG> Lpuart0W<'a, REG>
1287where
1288    REG: crate::Writable + crate::RegisterSpec,
1289{
1290    #[doc = "Automatic clock gating is disabled"]
1291    #[inline(always)]
1292    pub fn disabled(self) -> &'a mut crate::W<REG> {
1293        self.variant(Lpuart0::Disabled)
1294    }
1295    #[doc = "Automatic clock gating is enabled"]
1296    #[inline(always)]
1297    pub fn enabled(self) -> &'a mut crate::W<REG> {
1298        self.variant(Lpuart0::Enabled)
1299    }
1300}
1301#[doc = "LPUART1\n\nValue on reset: 0"]
1302#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1303#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1304pub enum Lpuart1 {
1305    #[doc = "0: Automatic clock gating is disabled"]
1306    Disabled = 0,
1307    #[doc = "1: Automatic clock gating is enabled"]
1308    Enabled = 1,
1309}
1310impl From<Lpuart1> for bool {
1311    #[inline(always)]
1312    fn from(variant: Lpuart1) -> Self {
1313        variant as u8 != 0
1314    }
1315}
1316#[doc = "Field `LPUART1` reader - LPUART1"]
1317pub type Lpuart1R = crate::BitReader<Lpuart1>;
1318impl Lpuart1R {
1319    #[doc = "Get enumerated values variant"]
1320    #[inline(always)]
1321    pub const fn variant(&self) -> Lpuart1 {
1322        match self.bits {
1323            false => Lpuart1::Disabled,
1324            true => Lpuart1::Enabled,
1325        }
1326    }
1327    #[doc = "Automatic clock gating is disabled"]
1328    #[inline(always)]
1329    pub fn is_disabled(&self) -> bool {
1330        *self == Lpuart1::Disabled
1331    }
1332    #[doc = "Automatic clock gating is enabled"]
1333    #[inline(always)]
1334    pub fn is_enabled(&self) -> bool {
1335        *self == Lpuart1::Enabled
1336    }
1337}
1338#[doc = "Field `LPUART1` writer - LPUART1"]
1339pub type Lpuart1W<'a, REG> = crate::BitWriter<'a, REG, Lpuart1>;
1340impl<'a, REG> Lpuart1W<'a, REG>
1341where
1342    REG: crate::Writable + crate::RegisterSpec,
1343{
1344    #[doc = "Automatic clock gating is disabled"]
1345    #[inline(always)]
1346    pub fn disabled(self) -> &'a mut crate::W<REG> {
1347        self.variant(Lpuart1::Disabled)
1348    }
1349    #[doc = "Automatic clock gating is enabled"]
1350    #[inline(always)]
1351    pub fn enabled(self) -> &'a mut crate::W<REG> {
1352        self.variant(Lpuart1::Enabled)
1353    }
1354}
1355#[doc = "LPUART2\n\nValue on reset: 0"]
1356#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1357#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1358pub enum Lpuart2 {
1359    #[doc = "0: Automatic clock gating is disabled"]
1360    Disabled = 0,
1361    #[doc = "1: Automatic clock gating is enabled"]
1362    Enabled = 1,
1363}
1364impl From<Lpuart2> for bool {
1365    #[inline(always)]
1366    fn from(variant: Lpuart2) -> Self {
1367        variant as u8 != 0
1368    }
1369}
1370#[doc = "Field `LPUART2` reader - LPUART2"]
1371pub type Lpuart2R = crate::BitReader<Lpuart2>;
1372impl Lpuart2R {
1373    #[doc = "Get enumerated values variant"]
1374    #[inline(always)]
1375    pub const fn variant(&self) -> Lpuart2 {
1376        match self.bits {
1377            false => Lpuart2::Disabled,
1378            true => Lpuart2::Enabled,
1379        }
1380    }
1381    #[doc = "Automatic clock gating is disabled"]
1382    #[inline(always)]
1383    pub fn is_disabled(&self) -> bool {
1384        *self == Lpuart2::Disabled
1385    }
1386    #[doc = "Automatic clock gating is enabled"]
1387    #[inline(always)]
1388    pub fn is_enabled(&self) -> bool {
1389        *self == Lpuart2::Enabled
1390    }
1391}
1392#[doc = "Field `LPUART2` writer - LPUART2"]
1393pub type Lpuart2W<'a, REG> = crate::BitWriter<'a, REG, Lpuart2>;
1394impl<'a, REG> Lpuart2W<'a, REG>
1395where
1396    REG: crate::Writable + crate::RegisterSpec,
1397{
1398    #[doc = "Automatic clock gating is disabled"]
1399    #[inline(always)]
1400    pub fn disabled(self) -> &'a mut crate::W<REG> {
1401        self.variant(Lpuart2::Disabled)
1402    }
1403    #[doc = "Automatic clock gating is enabled"]
1404    #[inline(always)]
1405    pub fn enabled(self) -> &'a mut crate::W<REG> {
1406        self.variant(Lpuart2::Enabled)
1407    }
1408}
1409#[doc = "LPUART3\n\nValue on reset: 0"]
1410#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1411#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1412pub enum Lpuart3 {
1413    #[doc = "0: Automatic clock gating is disabled"]
1414    Disabled = 0,
1415    #[doc = "1: Automatic clock gating is enabled"]
1416    Enabled = 1,
1417}
1418impl From<Lpuart3> for bool {
1419    #[inline(always)]
1420    fn from(variant: Lpuart3) -> Self {
1421        variant as u8 != 0
1422    }
1423}
1424#[doc = "Field `LPUART3` reader - LPUART3"]
1425pub type Lpuart3R = crate::BitReader<Lpuart3>;
1426impl Lpuart3R {
1427    #[doc = "Get enumerated values variant"]
1428    #[inline(always)]
1429    pub const fn variant(&self) -> Lpuart3 {
1430        match self.bits {
1431            false => Lpuart3::Disabled,
1432            true => Lpuart3::Enabled,
1433        }
1434    }
1435    #[doc = "Automatic clock gating is disabled"]
1436    #[inline(always)]
1437    pub fn is_disabled(&self) -> bool {
1438        *self == Lpuart3::Disabled
1439    }
1440    #[doc = "Automatic clock gating is enabled"]
1441    #[inline(always)]
1442    pub fn is_enabled(&self) -> bool {
1443        *self == Lpuart3::Enabled
1444    }
1445}
1446#[doc = "Field `LPUART3` writer - LPUART3"]
1447pub type Lpuart3W<'a, REG> = crate::BitWriter<'a, REG, Lpuart3>;
1448impl<'a, REG> Lpuart3W<'a, REG>
1449where
1450    REG: crate::Writable + crate::RegisterSpec,
1451{
1452    #[doc = "Automatic clock gating is disabled"]
1453    #[inline(always)]
1454    pub fn disabled(self) -> &'a mut crate::W<REG> {
1455        self.variant(Lpuart3::Disabled)
1456    }
1457    #[doc = "Automatic clock gating is enabled"]
1458    #[inline(always)]
1459    pub fn enabled(self) -> &'a mut crate::W<REG> {
1460        self.variant(Lpuart3::Enabled)
1461    }
1462}
1463#[doc = "LPUART4\n\nValue on reset: 0"]
1464#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1465#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1466pub enum Lpuart4 {
1467    #[doc = "0: Automatic clock gating is disabled"]
1468    Disabled = 0,
1469    #[doc = "1: Automatic clock gating is enabled"]
1470    Enabled = 1,
1471}
1472impl From<Lpuart4> for bool {
1473    #[inline(always)]
1474    fn from(variant: Lpuart4) -> Self {
1475        variant as u8 != 0
1476    }
1477}
1478#[doc = "Field `LPUART4` reader - LPUART4"]
1479pub type Lpuart4R = crate::BitReader<Lpuart4>;
1480impl Lpuart4R {
1481    #[doc = "Get enumerated values variant"]
1482    #[inline(always)]
1483    pub const fn variant(&self) -> Lpuart4 {
1484        match self.bits {
1485            false => Lpuart4::Disabled,
1486            true => Lpuart4::Enabled,
1487        }
1488    }
1489    #[doc = "Automatic clock gating is disabled"]
1490    #[inline(always)]
1491    pub fn is_disabled(&self) -> bool {
1492        *self == Lpuart4::Disabled
1493    }
1494    #[doc = "Automatic clock gating is enabled"]
1495    #[inline(always)]
1496    pub fn is_enabled(&self) -> bool {
1497        *self == Lpuart4::Enabled
1498    }
1499}
1500#[doc = "Field `LPUART4` writer - LPUART4"]
1501pub type Lpuart4W<'a, REG> = crate::BitWriter<'a, REG, Lpuart4>;
1502impl<'a, REG> Lpuart4W<'a, REG>
1503where
1504    REG: crate::Writable + crate::RegisterSpec,
1505{
1506    #[doc = "Automatic clock gating is disabled"]
1507    #[inline(always)]
1508    pub fn disabled(self) -> &'a mut crate::W<REG> {
1509        self.variant(Lpuart4::Disabled)
1510    }
1511    #[doc = "Automatic clock gating is enabled"]
1512    #[inline(always)]
1513    pub fn enabled(self) -> &'a mut crate::W<REG> {
1514        self.variant(Lpuart4::Enabled)
1515    }
1516}
1517#[doc = "USB0\n\nValue on reset: 0"]
1518#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1519#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1520pub enum Usb0 {
1521    #[doc = "0: Automatic clock gating is disabled"]
1522    Disabled = 0,
1523    #[doc = "1: Automatic clock gating is enabled"]
1524    Enabled = 1,
1525}
1526impl From<Usb0> for bool {
1527    #[inline(always)]
1528    fn from(variant: Usb0) -> Self {
1529        variant as u8 != 0
1530    }
1531}
1532#[doc = "Field `USB0` reader - USB0"]
1533pub type Usb0R = crate::BitReader<Usb0>;
1534impl Usb0R {
1535    #[doc = "Get enumerated values variant"]
1536    #[inline(always)]
1537    pub const fn variant(&self) -> Usb0 {
1538        match self.bits {
1539            false => Usb0::Disabled,
1540            true => Usb0::Enabled,
1541        }
1542    }
1543    #[doc = "Automatic clock gating is disabled"]
1544    #[inline(always)]
1545    pub fn is_disabled(&self) -> bool {
1546        *self == Usb0::Disabled
1547    }
1548    #[doc = "Automatic clock gating is enabled"]
1549    #[inline(always)]
1550    pub fn is_enabled(&self) -> bool {
1551        *self == Usb0::Enabled
1552    }
1553}
1554#[doc = "Field `USB0` writer - USB0"]
1555pub type Usb0W<'a, REG> = crate::BitWriter<'a, REG, Usb0>;
1556impl<'a, REG> Usb0W<'a, REG>
1557where
1558    REG: crate::Writable + crate::RegisterSpec,
1559{
1560    #[doc = "Automatic clock gating is disabled"]
1561    #[inline(always)]
1562    pub fn disabled(self) -> &'a mut crate::W<REG> {
1563        self.variant(Usb0::Disabled)
1564    }
1565    #[doc = "Automatic clock gating is enabled"]
1566    #[inline(always)]
1567    pub fn enabled(self) -> &'a mut crate::W<REG> {
1568        self.variant(Usb0::Enabled)
1569    }
1570}
1571#[doc = "QDC0\n\nValue on reset: 0"]
1572#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1573#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1574pub enum Qdc0 {
1575    #[doc = "0: Automatic clock gating is disabled"]
1576    Disabled = 0,
1577    #[doc = "1: Automatic clock gating is enabled"]
1578    Enabled = 1,
1579}
1580impl From<Qdc0> for bool {
1581    #[inline(always)]
1582    fn from(variant: Qdc0) -> Self {
1583        variant as u8 != 0
1584    }
1585}
1586#[doc = "Field `QDC0` reader - QDC0"]
1587pub type Qdc0R = crate::BitReader<Qdc0>;
1588impl Qdc0R {
1589    #[doc = "Get enumerated values variant"]
1590    #[inline(always)]
1591    pub const fn variant(&self) -> Qdc0 {
1592        match self.bits {
1593            false => Qdc0::Disabled,
1594            true => Qdc0::Enabled,
1595        }
1596    }
1597    #[doc = "Automatic clock gating is disabled"]
1598    #[inline(always)]
1599    pub fn is_disabled(&self) -> bool {
1600        *self == Qdc0::Disabled
1601    }
1602    #[doc = "Automatic clock gating is enabled"]
1603    #[inline(always)]
1604    pub fn is_enabled(&self) -> bool {
1605        *self == Qdc0::Enabled
1606    }
1607}
1608#[doc = "Field `QDC0` writer - QDC0"]
1609pub type Qdc0W<'a, REG> = crate::BitWriter<'a, REG, Qdc0>;
1610impl<'a, REG> Qdc0W<'a, REG>
1611where
1612    REG: crate::Writable + crate::RegisterSpec,
1613{
1614    #[doc = "Automatic clock gating is disabled"]
1615    #[inline(always)]
1616    pub fn disabled(self) -> &'a mut crate::W<REG> {
1617        self.variant(Qdc0::Disabled)
1618    }
1619    #[doc = "Automatic clock gating is enabled"]
1620    #[inline(always)]
1621    pub fn enabled(self) -> &'a mut crate::W<REG> {
1622        self.variant(Qdc0::Enabled)
1623    }
1624}
1625#[doc = "QDC1\n\nValue on reset: 0"]
1626#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1627#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1628pub enum Qdc1 {
1629    #[doc = "0: Automatic clock gating is disabled"]
1630    Disabled = 0,
1631    #[doc = "1: Automatic clock gating is enabled"]
1632    Enabled = 1,
1633}
1634impl From<Qdc1> for bool {
1635    #[inline(always)]
1636    fn from(variant: Qdc1) -> Self {
1637        variant as u8 != 0
1638    }
1639}
1640#[doc = "Field `QDC1` reader - QDC1"]
1641pub type Qdc1R = crate::BitReader<Qdc1>;
1642impl Qdc1R {
1643    #[doc = "Get enumerated values variant"]
1644    #[inline(always)]
1645    pub const fn variant(&self) -> Qdc1 {
1646        match self.bits {
1647            false => Qdc1::Disabled,
1648            true => Qdc1::Enabled,
1649        }
1650    }
1651    #[doc = "Automatic clock gating is disabled"]
1652    #[inline(always)]
1653    pub fn is_disabled(&self) -> bool {
1654        *self == Qdc1::Disabled
1655    }
1656    #[doc = "Automatic clock gating is enabled"]
1657    #[inline(always)]
1658    pub fn is_enabled(&self) -> bool {
1659        *self == Qdc1::Enabled
1660    }
1661}
1662#[doc = "Field `QDC1` writer - QDC1"]
1663pub type Qdc1W<'a, REG> = crate::BitWriter<'a, REG, Qdc1>;
1664impl<'a, REG> Qdc1W<'a, REG>
1665where
1666    REG: crate::Writable + crate::RegisterSpec,
1667{
1668    #[doc = "Automatic clock gating is disabled"]
1669    #[inline(always)]
1670    pub fn disabled(self) -> &'a mut crate::W<REG> {
1671        self.variant(Qdc1::Disabled)
1672    }
1673    #[doc = "Automatic clock gating is enabled"]
1674    #[inline(always)]
1675    pub fn enabled(self) -> &'a mut crate::W<REG> {
1676        self.variant(Qdc1::Enabled)
1677    }
1678}
1679#[doc = "FLEXPWM0\n\nValue on reset: 0"]
1680#[cfg_attr(feature = "defmt", derive(defmt::Format))]
1681#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1682pub enum Flexpwm0 {
1683    #[doc = "0: Automatic clock gating is disabled"]
1684    Disabled = 0,
1685    #[doc = "1: Automatic clock gating is enabled"]
1686    Enabled = 1,
1687}
1688impl From<Flexpwm0> for bool {
1689    #[inline(always)]
1690    fn from(variant: Flexpwm0) -> Self {
1691        variant as u8 != 0
1692    }
1693}
1694#[doc = "Field `FLEXPWM0` reader - FLEXPWM0"]
1695pub type Flexpwm0R = crate::BitReader<Flexpwm0>;
1696impl Flexpwm0R {
1697    #[doc = "Get enumerated values variant"]
1698    #[inline(always)]
1699    pub const fn variant(&self) -> Flexpwm0 {
1700        match self.bits {
1701            false => Flexpwm0::Disabled,
1702            true => Flexpwm0::Enabled,
1703        }
1704    }
1705    #[doc = "Automatic clock gating is disabled"]
1706    #[inline(always)]
1707    pub fn is_disabled(&self) -> bool {
1708        *self == Flexpwm0::Disabled
1709    }
1710    #[doc = "Automatic clock gating is enabled"]
1711    #[inline(always)]
1712    pub fn is_enabled(&self) -> bool {
1713        *self == Flexpwm0::Enabled
1714    }
1715}
1716#[doc = "Field `FLEXPWM0` writer - FLEXPWM0"]
1717pub type Flexpwm0W<'a, REG> = crate::BitWriter<'a, REG, Flexpwm0>;
1718impl<'a, REG> Flexpwm0W<'a, REG>
1719where
1720    REG: crate::Writable + crate::RegisterSpec,
1721{
1722    #[doc = "Automatic clock gating is disabled"]
1723    #[inline(always)]
1724    pub fn disabled(self) -> &'a mut crate::W<REG> {
1725        self.variant(Flexpwm0::Disabled)
1726    }
1727    #[doc = "Automatic clock gating is enabled"]
1728    #[inline(always)]
1729    pub fn enabled(self) -> &'a mut crate::W<REG> {
1730        self.variant(Flexpwm0::Enabled)
1731    }
1732}
1733impl R {
1734    #[doc = "Bit 0 - INPUTMUX0"]
1735    #[inline(always)]
1736    pub fn inputmux0(&self) -> Inputmux0R {
1737        Inputmux0R::new((self.bits & 1) != 0)
1738    }
1739    #[doc = "Bit 1 - I3C0"]
1740    #[inline(always)]
1741    pub fn i3c0(&self) -> I3c0R {
1742        I3c0R::new(((self.bits >> 1) & 1) != 0)
1743    }
1744    #[doc = "Bit 2 - CTIMER0"]
1745    #[inline(always)]
1746    pub fn ctimer0(&self) -> Ctimer0R {
1747        Ctimer0R::new(((self.bits >> 2) & 1) != 0)
1748    }
1749    #[doc = "Bit 3 - CTIMER1"]
1750    #[inline(always)]
1751    pub fn ctimer1(&self) -> Ctimer1R {
1752        Ctimer1R::new(((self.bits >> 3) & 1) != 0)
1753    }
1754    #[doc = "Bit 4 - CTIMER2"]
1755    #[inline(always)]
1756    pub fn ctimer2(&self) -> Ctimer2R {
1757        Ctimer2R::new(((self.bits >> 4) & 1) != 0)
1758    }
1759    #[doc = "Bit 5 - CTIMER3"]
1760    #[inline(always)]
1761    pub fn ctimer3(&self) -> Ctimer3R {
1762        Ctimer3R::new(((self.bits >> 5) & 1) != 0)
1763    }
1764    #[doc = "Bit 6 - CTIMER4"]
1765    #[inline(always)]
1766    pub fn ctimer4(&self) -> Ctimer4R {
1767        Ctimer4R::new(((self.bits >> 6) & 1) != 0)
1768    }
1769    #[doc = "Bit 7 - FREQME"]
1770    #[inline(always)]
1771    pub fn freqme(&self) -> FreqmeR {
1772        FreqmeR::new(((self.bits >> 7) & 1) != 0)
1773    }
1774    #[doc = "Bit 8 - UTICK0"]
1775    #[inline(always)]
1776    pub fn utick0(&self) -> Utick0R {
1777        Utick0R::new(((self.bits >> 8) & 1) != 0)
1778    }
1779    #[doc = "Bit 9 - WWDT0"]
1780    #[inline(always)]
1781    pub fn wwdt0(&self) -> Wwdt0R {
1782        Wwdt0R::new(((self.bits >> 9) & 1) != 0)
1783    }
1784    #[doc = "Bit 10 - SMARTDMA0"]
1785    #[inline(always)]
1786    pub fn smartdma0(&self) -> Smartdma0R {
1787        Smartdma0R::new(((self.bits >> 10) & 1) != 0)
1788    }
1789    #[doc = "Bit 11 - DMA0"]
1790    #[inline(always)]
1791    pub fn dma0(&self) -> Dma0R {
1792        Dma0R::new(((self.bits >> 11) & 1) != 0)
1793    }
1794    #[doc = "Bit 12 - AOI0"]
1795    #[inline(always)]
1796    pub fn aoi0(&self) -> Aoi0R {
1797        Aoi0R::new(((self.bits >> 12) & 1) != 0)
1798    }
1799    #[doc = "Bit 13 - CRC0"]
1800    #[inline(always)]
1801    pub fn crc0(&self) -> Crc0R {
1802        Crc0R::new(((self.bits >> 13) & 1) != 0)
1803    }
1804    #[doc = "Bit 14 - EIM0"]
1805    #[inline(always)]
1806    pub fn eim0(&self) -> Eim0R {
1807        Eim0R::new(((self.bits >> 14) & 1) != 0)
1808    }
1809    #[doc = "Bit 15 - ERM0"]
1810    #[inline(always)]
1811    pub fn erm0(&self) -> Erm0R {
1812        Erm0R::new(((self.bits >> 15) & 1) != 0)
1813    }
1814    #[doc = "Bit 16 - FMC"]
1815    #[inline(always)]
1816    pub fn fmc(&self) -> FmcR {
1817        FmcR::new(((self.bits >> 16) & 1) != 0)
1818    }
1819    #[doc = "Bit 17 - AOI1"]
1820    #[inline(always)]
1821    pub fn aoi1(&self) -> Aoi1R {
1822        Aoi1R::new(((self.bits >> 17) & 1) != 0)
1823    }
1824    #[doc = "Bit 18 - FLEXIO0"]
1825    #[inline(always)]
1826    pub fn flexio0(&self) -> Flexio0R {
1827        Flexio0R::new(((self.bits >> 18) & 1) != 0)
1828    }
1829    #[doc = "Bit 19 - LPI2C0"]
1830    #[inline(always)]
1831    pub fn lpi2c0(&self) -> Lpi2c0R {
1832        Lpi2c0R::new(((self.bits >> 19) & 1) != 0)
1833    }
1834    #[doc = "Bit 20 - LPI2C1"]
1835    #[inline(always)]
1836    pub fn lpi2c1(&self) -> Lpi2c1R {
1837        Lpi2c1R::new(((self.bits >> 20) & 1) != 0)
1838    }
1839    #[doc = "Bit 21 - LPSPI0"]
1840    #[inline(always)]
1841    pub fn lpspi0(&self) -> Lpspi0R {
1842        Lpspi0R::new(((self.bits >> 21) & 1) != 0)
1843    }
1844    #[doc = "Bit 22 - LPSPI1"]
1845    #[inline(always)]
1846    pub fn lpspi1(&self) -> Lpspi1R {
1847        Lpspi1R::new(((self.bits >> 22) & 1) != 0)
1848    }
1849    #[doc = "Bit 23 - LPUART0"]
1850    #[inline(always)]
1851    pub fn lpuart0(&self) -> Lpuart0R {
1852        Lpuart0R::new(((self.bits >> 23) & 1) != 0)
1853    }
1854    #[doc = "Bit 24 - LPUART1"]
1855    #[inline(always)]
1856    pub fn lpuart1(&self) -> Lpuart1R {
1857        Lpuart1R::new(((self.bits >> 24) & 1) != 0)
1858    }
1859    #[doc = "Bit 25 - LPUART2"]
1860    #[inline(always)]
1861    pub fn lpuart2(&self) -> Lpuart2R {
1862        Lpuart2R::new(((self.bits >> 25) & 1) != 0)
1863    }
1864    #[doc = "Bit 26 - LPUART3"]
1865    #[inline(always)]
1866    pub fn lpuart3(&self) -> Lpuart3R {
1867        Lpuart3R::new(((self.bits >> 26) & 1) != 0)
1868    }
1869    #[doc = "Bit 27 - LPUART4"]
1870    #[inline(always)]
1871    pub fn lpuart4(&self) -> Lpuart4R {
1872        Lpuart4R::new(((self.bits >> 27) & 1) != 0)
1873    }
1874    #[doc = "Bit 28 - USB0"]
1875    #[inline(always)]
1876    pub fn usb0(&self) -> Usb0R {
1877        Usb0R::new(((self.bits >> 28) & 1) != 0)
1878    }
1879    #[doc = "Bit 29 - QDC0"]
1880    #[inline(always)]
1881    pub fn qdc0(&self) -> Qdc0R {
1882        Qdc0R::new(((self.bits >> 29) & 1) != 0)
1883    }
1884    #[doc = "Bit 30 - QDC1"]
1885    #[inline(always)]
1886    pub fn qdc1(&self) -> Qdc1R {
1887        Qdc1R::new(((self.bits >> 30) & 1) != 0)
1888    }
1889    #[doc = "Bit 31 - FLEXPWM0"]
1890    #[inline(always)]
1891    pub fn flexpwm0(&self) -> Flexpwm0R {
1892        Flexpwm0R::new(((self.bits >> 31) & 1) != 0)
1893    }
1894}
1895#[cfg(feature = "debug")]
1896impl core::fmt::Debug for R {
1897    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
1898        f.debug_struct("MRCC_GLB_ACC0")
1899            .field("inputmux0", &self.inputmux0())
1900            .field("i3c0", &self.i3c0())
1901            .field("ctimer0", &self.ctimer0())
1902            .field("ctimer1", &self.ctimer1())
1903            .field("ctimer2", &self.ctimer2())
1904            .field("ctimer3", &self.ctimer3())
1905            .field("ctimer4", &self.ctimer4())
1906            .field("freqme", &self.freqme())
1907            .field("utick0", &self.utick0())
1908            .field("wwdt0", &self.wwdt0())
1909            .field("smartdma0", &self.smartdma0())
1910            .field("dma0", &self.dma0())
1911            .field("aoi0", &self.aoi0())
1912            .field("crc0", &self.crc0())
1913            .field("eim0", &self.eim0())
1914            .field("erm0", &self.erm0())
1915            .field("fmc", &self.fmc())
1916            .field("aoi1", &self.aoi1())
1917            .field("flexio0", &self.flexio0())
1918            .field("lpi2c0", &self.lpi2c0())
1919            .field("lpi2c1", &self.lpi2c1())
1920            .field("lpspi0", &self.lpspi0())
1921            .field("lpspi1", &self.lpspi1())
1922            .field("lpuart0", &self.lpuart0())
1923            .field("lpuart1", &self.lpuart1())
1924            .field("lpuart2", &self.lpuart2())
1925            .field("lpuart3", &self.lpuart3())
1926            .field("lpuart4", &self.lpuart4())
1927            .field("usb0", &self.usb0())
1928            .field("qdc0", &self.qdc0())
1929            .field("qdc1", &self.qdc1())
1930            .field("flexpwm0", &self.flexpwm0())
1931            .finish()
1932    }
1933}
1934impl W {
1935    #[doc = "Bit 0 - INPUTMUX0"]
1936    #[inline(always)]
1937    pub fn inputmux0(&mut self) -> Inputmux0W<'_, MrccGlbAcc0Spec> {
1938        Inputmux0W::new(self, 0)
1939    }
1940    #[doc = "Bit 1 - I3C0"]
1941    #[inline(always)]
1942    pub fn i3c0(&mut self) -> I3c0W<'_, MrccGlbAcc0Spec> {
1943        I3c0W::new(self, 1)
1944    }
1945    #[doc = "Bit 2 - CTIMER0"]
1946    #[inline(always)]
1947    pub fn ctimer0(&mut self) -> Ctimer0W<'_, MrccGlbAcc0Spec> {
1948        Ctimer0W::new(self, 2)
1949    }
1950    #[doc = "Bit 3 - CTIMER1"]
1951    #[inline(always)]
1952    pub fn ctimer1(&mut self) -> Ctimer1W<'_, MrccGlbAcc0Spec> {
1953        Ctimer1W::new(self, 3)
1954    }
1955    #[doc = "Bit 4 - CTIMER2"]
1956    #[inline(always)]
1957    pub fn ctimer2(&mut self) -> Ctimer2W<'_, MrccGlbAcc0Spec> {
1958        Ctimer2W::new(self, 4)
1959    }
1960    #[doc = "Bit 5 - CTIMER3"]
1961    #[inline(always)]
1962    pub fn ctimer3(&mut self) -> Ctimer3W<'_, MrccGlbAcc0Spec> {
1963        Ctimer3W::new(self, 5)
1964    }
1965    #[doc = "Bit 6 - CTIMER4"]
1966    #[inline(always)]
1967    pub fn ctimer4(&mut self) -> Ctimer4W<'_, MrccGlbAcc0Spec> {
1968        Ctimer4W::new(self, 6)
1969    }
1970    #[doc = "Bit 7 - FREQME"]
1971    #[inline(always)]
1972    pub fn freqme(&mut self) -> FreqmeW<'_, MrccGlbAcc0Spec> {
1973        FreqmeW::new(self, 7)
1974    }
1975    #[doc = "Bit 8 - UTICK0"]
1976    #[inline(always)]
1977    pub fn utick0(&mut self) -> Utick0W<'_, MrccGlbAcc0Spec> {
1978        Utick0W::new(self, 8)
1979    }
1980    #[doc = "Bit 9 - WWDT0"]
1981    #[inline(always)]
1982    pub fn wwdt0(&mut self) -> Wwdt0W<'_, MrccGlbAcc0Spec> {
1983        Wwdt0W::new(self, 9)
1984    }
1985    #[doc = "Bit 10 - SMARTDMA0"]
1986    #[inline(always)]
1987    pub fn smartdma0(&mut self) -> Smartdma0W<'_, MrccGlbAcc0Spec> {
1988        Smartdma0W::new(self, 10)
1989    }
1990    #[doc = "Bit 11 - DMA0"]
1991    #[inline(always)]
1992    pub fn dma0(&mut self) -> Dma0W<'_, MrccGlbAcc0Spec> {
1993        Dma0W::new(self, 11)
1994    }
1995    #[doc = "Bit 12 - AOI0"]
1996    #[inline(always)]
1997    pub fn aoi0(&mut self) -> Aoi0W<'_, MrccGlbAcc0Spec> {
1998        Aoi0W::new(self, 12)
1999    }
2000    #[doc = "Bit 13 - CRC0"]
2001    #[inline(always)]
2002    pub fn crc0(&mut self) -> Crc0W<'_, MrccGlbAcc0Spec> {
2003        Crc0W::new(self, 13)
2004    }
2005    #[doc = "Bit 14 - EIM0"]
2006    #[inline(always)]
2007    pub fn eim0(&mut self) -> Eim0W<'_, MrccGlbAcc0Spec> {
2008        Eim0W::new(self, 14)
2009    }
2010    #[doc = "Bit 15 - ERM0"]
2011    #[inline(always)]
2012    pub fn erm0(&mut self) -> Erm0W<'_, MrccGlbAcc0Spec> {
2013        Erm0W::new(self, 15)
2014    }
2015    #[doc = "Bit 16 - FMC"]
2016    #[inline(always)]
2017    pub fn fmc(&mut self) -> FmcW<'_, MrccGlbAcc0Spec> {
2018        FmcW::new(self, 16)
2019    }
2020    #[doc = "Bit 17 - AOI1"]
2021    #[inline(always)]
2022    pub fn aoi1(&mut self) -> Aoi1W<'_, MrccGlbAcc0Spec> {
2023        Aoi1W::new(self, 17)
2024    }
2025    #[doc = "Bit 18 - FLEXIO0"]
2026    #[inline(always)]
2027    pub fn flexio0(&mut self) -> Flexio0W<'_, MrccGlbAcc0Spec> {
2028        Flexio0W::new(self, 18)
2029    }
2030    #[doc = "Bit 19 - LPI2C0"]
2031    #[inline(always)]
2032    pub fn lpi2c0(&mut self) -> Lpi2c0W<'_, MrccGlbAcc0Spec> {
2033        Lpi2c0W::new(self, 19)
2034    }
2035    #[doc = "Bit 20 - LPI2C1"]
2036    #[inline(always)]
2037    pub fn lpi2c1(&mut self) -> Lpi2c1W<'_, MrccGlbAcc0Spec> {
2038        Lpi2c1W::new(self, 20)
2039    }
2040    #[doc = "Bit 21 - LPSPI0"]
2041    #[inline(always)]
2042    pub fn lpspi0(&mut self) -> Lpspi0W<'_, MrccGlbAcc0Spec> {
2043        Lpspi0W::new(self, 21)
2044    }
2045    #[doc = "Bit 22 - LPSPI1"]
2046    #[inline(always)]
2047    pub fn lpspi1(&mut self) -> Lpspi1W<'_, MrccGlbAcc0Spec> {
2048        Lpspi1W::new(self, 22)
2049    }
2050    #[doc = "Bit 23 - LPUART0"]
2051    #[inline(always)]
2052    pub fn lpuart0(&mut self) -> Lpuart0W<'_, MrccGlbAcc0Spec> {
2053        Lpuart0W::new(self, 23)
2054    }
2055    #[doc = "Bit 24 - LPUART1"]
2056    #[inline(always)]
2057    pub fn lpuart1(&mut self) -> Lpuart1W<'_, MrccGlbAcc0Spec> {
2058        Lpuart1W::new(self, 24)
2059    }
2060    #[doc = "Bit 25 - LPUART2"]
2061    #[inline(always)]
2062    pub fn lpuart2(&mut self) -> Lpuart2W<'_, MrccGlbAcc0Spec> {
2063        Lpuart2W::new(self, 25)
2064    }
2065    #[doc = "Bit 26 - LPUART3"]
2066    #[inline(always)]
2067    pub fn lpuart3(&mut self) -> Lpuart3W<'_, MrccGlbAcc0Spec> {
2068        Lpuart3W::new(self, 26)
2069    }
2070    #[doc = "Bit 27 - LPUART4"]
2071    #[inline(always)]
2072    pub fn lpuart4(&mut self) -> Lpuart4W<'_, MrccGlbAcc0Spec> {
2073        Lpuart4W::new(self, 27)
2074    }
2075    #[doc = "Bit 28 - USB0"]
2076    #[inline(always)]
2077    pub fn usb0(&mut self) -> Usb0W<'_, MrccGlbAcc0Spec> {
2078        Usb0W::new(self, 28)
2079    }
2080    #[doc = "Bit 29 - QDC0"]
2081    #[inline(always)]
2082    pub fn qdc0(&mut self) -> Qdc0W<'_, MrccGlbAcc0Spec> {
2083        Qdc0W::new(self, 29)
2084    }
2085    #[doc = "Bit 30 - QDC1"]
2086    #[inline(always)]
2087    pub fn qdc1(&mut self) -> Qdc1W<'_, MrccGlbAcc0Spec> {
2088        Qdc1W::new(self, 30)
2089    }
2090    #[doc = "Bit 31 - FLEXPWM0"]
2091    #[inline(always)]
2092    pub fn flexpwm0(&mut self) -> Flexpwm0W<'_, MrccGlbAcc0Spec> {
2093        Flexpwm0W::new(self, 31)
2094    }
2095}
2096#[doc = "Control Automatic Clock Gating 0\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_glb_acc0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_glb_acc0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
2097pub struct MrccGlbAcc0Spec;
2098impl crate::RegisterSpec for MrccGlbAcc0Spec {
2099    type Ux = u32;
2100}
2101#[doc = "`read()` method returns [`mrcc_glb_acc0::R`](R) reader structure"]
2102impl crate::Readable for MrccGlbAcc0Spec {}
2103#[doc = "`write(|w| ..)` method takes [`mrcc_glb_acc0::W`](W) writer structure"]
2104impl crate::Writable for MrccGlbAcc0Spec {
2105    type Safety = crate::Unsafe;
2106}
2107#[doc = "`reset()` method sets MRCC_GLB_ACC0 to value 0x0001_0200"]
2108impl crate::Resettable for MrccGlbAcc0Spec {
2109    const RESET_VALUE: u32 = 0x0001_0200;
2110}
mcxa_pac/mrcc0/mrcc_glb_acc0.rs

mcxa_pac/mrcc0/
mrcc_glb_acc0.rs
