mcxa_pac/mrcc0/
mrcc_dbg_trace_clksel.rs

1#[doc = "Register `MRCC_DBG_TRACE_CLKSEL` reader"]
2pub type R = crate::R<MrccDbgTraceClkselSpec>;
3#[doc = "Register `MRCC_DBG_TRACE_CLKSEL` writer"]
4pub type W = crate::W<MrccDbgTraceClkselSpec>;
5#[doc = "Functional Clock Mux Select\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Mux {
10    #[doc = "0: CPU_CLK"]
11    ClkrootCpu = 0,
12    #[doc = "1: CLK_1M"]
13    Clkroot1m = 1,
14    #[doc = "2: CLK_16K"]
15    Clkroot16k = 2,
16}
17impl From<Mux> for u8 {
18    #[inline(always)]
19    fn from(variant: Mux) -> Self {
20        variant as _
21    }
22}
23impl crate::FieldSpec for Mux {
24    type Ux = u8;
25}
26impl crate::IsEnum for Mux {}
27#[doc = "Field `MUX` reader - Functional Clock Mux Select"]
28pub type MuxR = crate::FieldReader<Mux>;
29impl MuxR {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<Mux> {
33        match self.bits {
34            0 => Some(Mux::ClkrootCpu),
35            1 => Some(Mux::Clkroot1m),
36            2 => Some(Mux::Clkroot16k),
37            _ => None,
38        }
39    }
40    #[doc = "CPU_CLK"]
41    #[inline(always)]
42    pub fn is_clkroot_cpu(&self) -> bool {
43        *self == Mux::ClkrootCpu
44    }
45    #[doc = "CLK_1M"]
46    #[inline(always)]
47    pub fn is_clkroot_1m(&self) -> bool {
48        *self == Mux::Clkroot1m
49    }
50    #[doc = "CLK_16K"]
51    #[inline(always)]
52    pub fn is_clkroot_16k(&self) -> bool {
53        *self == Mux::Clkroot16k
54    }
55}
56#[doc = "Field `MUX` writer - Functional Clock Mux Select"]
57pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 2, Mux>;
58impl<'a, REG> MuxW<'a, REG>
59where
60    REG: crate::Writable + crate::RegisterSpec,
61    REG::Ux: From<u8>,
62{
63    #[doc = "CPU_CLK"]
64    #[inline(always)]
65    pub fn clkroot_cpu(self) -> &'a mut crate::W<REG> {
66        self.variant(Mux::ClkrootCpu)
67    }
68    #[doc = "CLK_1M"]
69    #[inline(always)]
70    pub fn clkroot_1m(self) -> &'a mut crate::W<REG> {
71        self.variant(Mux::Clkroot1m)
72    }
73    #[doc = "CLK_16K"]
74    #[inline(always)]
75    pub fn clkroot_16k(self) -> &'a mut crate::W<REG> {
76        self.variant(Mux::Clkroot16k)
77    }
78}
79impl R {
80    #[doc = "Bits 0:1 - Functional Clock Mux Select"]
81    #[inline(always)]
82    pub fn mux(&self) -> MuxR {
83        MuxR::new((self.bits & 3) as u8)
84    }
85}
86#[cfg(feature = "debug")]
87impl core::fmt::Debug for R {
88    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
89        f.debug_struct("MRCC_DBG_TRACE_CLKSEL")
90            .field("mux", &self.mux())
91            .finish()
92    }
93}
94impl W {
95    #[doc = "Bits 0:1 - Functional Clock Mux Select"]
96    #[inline(always)]
97    pub fn mux(&mut self) -> MuxW<'_, MrccDbgTraceClkselSpec> {
98        MuxW::new(self, 0)
99    }
100}
101#[doc = "DBG_TRACE clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_dbg_trace_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_dbg_trace_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
102pub struct MrccDbgTraceClkselSpec;
103impl crate::RegisterSpec for MrccDbgTraceClkselSpec {
104    type Ux = u32;
105}
106#[doc = "`read()` method returns [`mrcc_dbg_trace_clksel::R`](R) reader structure"]
107impl crate::Readable for MrccDbgTraceClkselSpec {}
108#[doc = "`write(|w| ..)` method takes [`mrcc_dbg_trace_clksel::W`](W) writer structure"]
109impl crate::Writable for MrccDbgTraceClkselSpec {
110    type Safety = crate::Unsafe;
111}
112#[doc = "`reset()` method sets MRCC_DBG_TRACE_CLKSEL to value 0"]
113impl crate::Resettable for MrccDbgTraceClkselSpec {}
mcxa_pac/mrcc0/mrcc_dbg_trace_clksel.rs

mcxa_pac/mrcc0/
mrcc_dbg_trace_clksel.rs
