mcxa_pac/mrcc0/
mrcc_ctimer4_clksel.rs

1#[doc = "Register `MRCC_CTIMER4_CLKSEL` reader"]
2pub type R = crate::R<MrccCtimer4ClkselSpec>;
3#[doc = "Register `MRCC_CTIMER4_CLKSEL` writer"]
4pub type W = crate::W<MrccCtimer4ClkselSpec>;
5#[doc = "Functional Clock Mux Select\n\nValue on reset: 7"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Mux {
10    #[doc = "0: FRO_LF_DIV"]
11    ClkrootFunc0 = 0,
12    #[doc = "1: FRO_HF_GATED"]
13    ClkrootFunc1 = 1,
14    #[doc = "3: CLK_IN"]
15    ClkrootFunc3 = 3,
16    #[doc = "4: CLK_16K"]
17    ClkrootFunc4 = 4,
18    #[doc = "5: CLK_1M"]
19    ClkrootFunc5 = 5,
20    #[doc = "6: PLL1_CLK_DIV"]
21    ClkrootFunc6 = 6,
22}
23impl From<Mux> for u8 {
24    #[inline(always)]
25    fn from(variant: Mux) -> Self {
26        variant as _
27    }
28}
29impl crate::FieldSpec for Mux {
30    type Ux = u8;
31}
32impl crate::IsEnum for Mux {}
33#[doc = "Field `MUX` reader - Functional Clock Mux Select"]
34pub type MuxR = crate::FieldReader<Mux>;
35impl MuxR {
36    #[doc = "Get enumerated values variant"]
37    #[inline(always)]
38    pub const fn variant(&self) -> Option<Mux> {
39        match self.bits {
40            0 => Some(Mux::ClkrootFunc0),
41            1 => Some(Mux::ClkrootFunc1),
42            3 => Some(Mux::ClkrootFunc3),
43            4 => Some(Mux::ClkrootFunc4),
44            5 => Some(Mux::ClkrootFunc5),
45            6 => Some(Mux::ClkrootFunc6),
46            _ => None,
47        }
48    }
49    #[doc = "FRO_LF_DIV"]
50    #[inline(always)]
51    pub fn is_clkroot_func_0(&self) -> bool {
52        *self == Mux::ClkrootFunc0
53    }
54    #[doc = "FRO_HF_GATED"]
55    #[inline(always)]
56    pub fn is_clkroot_func_1(&self) -> bool {
57        *self == Mux::ClkrootFunc1
58    }
59    #[doc = "CLK_IN"]
60    #[inline(always)]
61    pub fn is_clkroot_func_3(&self) -> bool {
62        *self == Mux::ClkrootFunc3
63    }
64    #[doc = "CLK_16K"]
65    #[inline(always)]
66    pub fn is_clkroot_func_4(&self) -> bool {
67        *self == Mux::ClkrootFunc4
68    }
69    #[doc = "CLK_1M"]
70    #[inline(always)]
71    pub fn is_clkroot_func_5(&self) -> bool {
72        *self == Mux::ClkrootFunc5
73    }
74    #[doc = "PLL1_CLK_DIV"]
75    #[inline(always)]
76    pub fn is_clkroot_func_6(&self) -> bool {
77        *self == Mux::ClkrootFunc6
78    }
79}
80#[doc = "Field `MUX` writer - Functional Clock Mux Select"]
81pub type MuxW<'a, REG> = crate::FieldWriter<'a, REG, 3, Mux>;
82impl<'a, REG> MuxW<'a, REG>
83where
84    REG: crate::Writable + crate::RegisterSpec,
85    REG::Ux: From<u8>,
86{
87    #[doc = "FRO_LF_DIV"]
88    #[inline(always)]
89    pub fn clkroot_func_0(self) -> &'a mut crate::W<REG> {
90        self.variant(Mux::ClkrootFunc0)
91    }
92    #[doc = "FRO_HF_GATED"]
93    #[inline(always)]
94    pub fn clkroot_func_1(self) -> &'a mut crate::W<REG> {
95        self.variant(Mux::ClkrootFunc1)
96    }
97    #[doc = "CLK_IN"]
98    #[inline(always)]
99    pub fn clkroot_func_3(self) -> &'a mut crate::W<REG> {
100        self.variant(Mux::ClkrootFunc3)
101    }
102    #[doc = "CLK_16K"]
103    #[inline(always)]
104    pub fn clkroot_func_4(self) -> &'a mut crate::W<REG> {
105        self.variant(Mux::ClkrootFunc4)
106    }
107    #[doc = "CLK_1M"]
108    #[inline(always)]
109    pub fn clkroot_func_5(self) -> &'a mut crate::W<REG> {
110        self.variant(Mux::ClkrootFunc5)
111    }
112    #[doc = "PLL1_CLK_DIV"]
113    #[inline(always)]
114    pub fn clkroot_func_6(self) -> &'a mut crate::W<REG> {
115        self.variant(Mux::ClkrootFunc6)
116    }
117}
118impl R {
119    #[doc = "Bits 0:2 - Functional Clock Mux Select"]
120    #[inline(always)]
121    pub fn mux(&self) -> MuxR {
122        MuxR::new((self.bits & 7) as u8)
123    }
124}
125#[cfg(feature = "debug")]
126impl core::fmt::Debug for R {
127    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
128        f.debug_struct("MRCC_CTIMER4_CLKSEL").field("mux", &self.mux()).finish()
129    }
130}
131impl W {
132    #[doc = "Bits 0:2 - Functional Clock Mux Select"]
133    #[inline(always)]
134    pub fn mux(&mut self) -> MuxW<'_, MrccCtimer4ClkselSpec> {
135        MuxW::new(self, 0)
136    }
137}
138#[doc = "CTIMER4 clock selection control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer4_clksel::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer4_clksel::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
139pub struct MrccCtimer4ClkselSpec;
140impl crate::RegisterSpec for MrccCtimer4ClkselSpec {
141    type Ux = u32;
142}
143#[doc = "`read()` method returns [`mrcc_ctimer4_clksel::R`](R) reader structure"]
144impl crate::Readable for MrccCtimer4ClkselSpec {}
145#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer4_clksel::W`](W) writer structure"]
146impl crate::Writable for MrccCtimer4ClkselSpec {
147    type Safety = crate::Unsafe;
148}
149#[doc = "`reset()` method sets MRCC_CTIMER4_CLKSEL to value 0x07"]
150impl crate::Resettable for MrccCtimer4ClkselSpec {
151    const RESET_VALUE: u32 = 0x07;
152}
mcxa_pac/mrcc0/mrcc_ctimer4_clksel.rs

mcxa_pac/mrcc0/
mrcc_ctimer4_clksel.rs
