mcxa_pac/mrcc0/
mrcc_ctimer1_clkdiv.rs

1#[doc = "Register `MRCC_CTIMER1_CLKDIV` reader"]
2pub type R = crate::R<MrccCtimer1ClkdivSpec>;
3#[doc = "Register `MRCC_CTIMER1_CLKDIV` writer"]
4pub type W = crate::W<MrccCtimer1ClkdivSpec>;
5#[doc = "Field `DIV` reader - Functional Clock Divider"]
6pub type DivR = crate::FieldReader;
7#[doc = "Field `DIV` writer - Functional Clock Divider"]
8pub type DivW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Reset divider counter\n\nValue on reset: 0"]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum Reset {
13    #[doc = "0: Reset is released/disabled (clock is running)"]
14    Deasserted = 0,
15    #[doc = "1: Reset is active/enabled (clock is NOT running)"]
16    Asserted = 1,
17}
18impl From<Reset> for bool {
19    #[inline(always)]
20    fn from(variant: Reset) -> Self {
21        variant as u8 != 0
22    }
23}
24#[doc = "Field `RESET` writer - Reset divider counter"]
25pub type ResetW<'a, REG> = crate::BitWriter<'a, REG, Reset>;
26impl<'a, REG> ResetW<'a, REG>
27where
28    REG: crate::Writable + crate::RegisterSpec,
29{
30    #[doc = "Reset is released/disabled (clock is running)"]
31    #[inline(always)]
32    pub fn deasserted(self) -> &'a mut crate::W<REG> {
33        self.variant(Reset::Deasserted)
34    }
35    #[doc = "Reset is active/enabled (clock is NOT running)"]
36    #[inline(always)]
37    pub fn asserted(self) -> &'a mut crate::W<REG> {
38        self.variant(Reset::Asserted)
39    }
40}
41#[doc = "Halt divider counter\n\nValue on reset: 1"]
42#[cfg_attr(feature = "defmt", derive(defmt::Format))]
43#[derive(Clone, Copy, Debug, PartialEq, Eq)]
44pub enum Halt {
45    #[doc = "0: Halt is inactive/disabled (clock is running)"]
46    Deasserted = 0,
47    #[doc = "1: Halt is active/enabled (clock is NOT running)"]
48    Asserted = 1,
49}
50impl From<Halt> for bool {
51    #[inline(always)]
52    fn from(variant: Halt) -> Self {
53        variant as u8 != 0
54    }
55}
56#[doc = "Field `HALT` reader - Halt divider counter"]
57pub type HaltR = crate::BitReader<Halt>;
58impl HaltR {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub const fn variant(&self) -> Halt {
62        match self.bits {
63            false => Halt::Deasserted,
64            true => Halt::Asserted,
65        }
66    }
67    #[doc = "Halt is inactive/disabled (clock is running)"]
68    #[inline(always)]
69    pub fn is_deasserted(&self) -> bool {
70        *self == Halt::Deasserted
71    }
72    #[doc = "Halt is active/enabled (clock is NOT running)"]
73    #[inline(always)]
74    pub fn is_asserted(&self) -> bool {
75        *self == Halt::Asserted
76    }
77}
78#[doc = "Field `HALT` writer - Halt divider counter"]
79pub type HaltW<'a, REG> = crate::BitWriter<'a, REG, Halt>;
80impl<'a, REG> HaltW<'a, REG>
81where
82    REG: crate::Writable + crate::RegisterSpec,
83{
84    #[doc = "Halt is inactive/disabled (clock is running)"]
85    #[inline(always)]
86    pub fn deasserted(self) -> &'a mut crate::W<REG> {
87        self.variant(Halt::Deasserted)
88    }
89    #[doc = "Halt is active/enabled (clock is NOT running)"]
90    #[inline(always)]
91    pub fn asserted(self) -> &'a mut crate::W<REG> {
92        self.variant(Halt::Asserted)
93    }
94}
95#[doc = "Divider status flag\n\nValue on reset: 0"]
96#[cfg_attr(feature = "defmt", derive(defmt::Format))]
97#[derive(Clone, Copy, Debug, PartialEq, Eq)]
98pub enum Unstab {
99    #[doc = "0: Clock divider is stable"]
100    Stable = 0,
101    #[doc = "1: Clock divider is unstable"]
102    Unstable = 1,
103}
104impl From<Unstab> for bool {
105    #[inline(always)]
106    fn from(variant: Unstab) -> Self {
107        variant as u8 != 0
108    }
109}
110#[doc = "Field `UNSTAB` reader - Divider status flag"]
111pub type UnstabR = crate::BitReader<Unstab>;
112impl UnstabR {
113    #[doc = "Get enumerated values variant"]
114    #[inline(always)]
115    pub const fn variant(&self) -> Unstab {
116        match self.bits {
117            false => Unstab::Stable,
118            true => Unstab::Unstable,
119        }
120    }
121    #[doc = "Clock divider is stable"]
122    #[inline(always)]
123    pub fn is_stable(&self) -> bool {
124        *self == Unstab::Stable
125    }
126    #[doc = "Clock divider is unstable"]
127    #[inline(always)]
128    pub fn is_unstable(&self) -> bool {
129        *self == Unstab::Unstable
130    }
131}
132impl R {
133    #[doc = "Bits 0:3 - Functional Clock Divider"]
134    #[inline(always)]
135    pub fn div(&self) -> DivR {
136        DivR::new((self.bits & 0x0f) as u8)
137    }
138    #[doc = "Bit 30 - Halt divider counter"]
139    #[inline(always)]
140    pub fn halt(&self) -> HaltR {
141        HaltR::new(((self.bits >> 30) & 1) != 0)
142    }
143    #[doc = "Bit 31 - Divider status flag"]
144    #[inline(always)]
145    pub fn unstab(&self) -> UnstabR {
146        UnstabR::new(((self.bits >> 31) & 1) != 0)
147    }
148}
149#[cfg(feature = "debug")]
150impl core::fmt::Debug for R {
151    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
152        f.debug_struct("MRCC_CTIMER1_CLKDIV")
153            .field("div", &self.div())
154            .field("halt", &self.halt())
155            .field("unstab", &self.unstab())
156            .finish()
157    }
158}
159impl W {
160    #[doc = "Bits 0:3 - Functional Clock Divider"]
161    #[inline(always)]
162    pub fn div(&mut self) -> DivW<'_, MrccCtimer1ClkdivSpec> {
163        DivW::new(self, 0)
164    }
165    #[doc = "Bit 29 - Reset divider counter"]
166    #[inline(always)]
167    pub fn reset(&mut self) -> ResetW<'_, MrccCtimer1ClkdivSpec> {
168        ResetW::new(self, 29)
169    }
170    #[doc = "Bit 30 - Halt divider counter"]
171    #[inline(always)]
172    pub fn halt(&mut self) -> HaltW<'_, MrccCtimer1ClkdivSpec> {
173        HaltW::new(self, 30)
174    }
175}
176#[doc = "CTIMER1 clock divider control\n\nYou can [`read`](crate::Reg::read) this register and get [`mrcc_ctimer1_clkdiv::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mrcc_ctimer1_clkdiv::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
177pub struct MrccCtimer1ClkdivSpec;
178impl crate::RegisterSpec for MrccCtimer1ClkdivSpec {
179    type Ux = u32;
180}
181#[doc = "`read()` method returns [`mrcc_ctimer1_clkdiv::R`](R) reader structure"]
182impl crate::Readable for MrccCtimer1ClkdivSpec {}
183#[doc = "`write(|w| ..)` method takes [`mrcc_ctimer1_clkdiv::W`](W) writer structure"]
184impl crate::Writable for MrccCtimer1ClkdivSpec {
185    type Safety = crate::Unsafe;
186}
187#[doc = "`reset()` method sets MRCC_CTIMER1_CLKDIV to value 0x4000_0000"]
188impl crate::Resettable for MrccCtimer1ClkdivSpec {
189    const RESET_VALUE: u32 = 0x4000_0000;
190}
mcxa_pac/mrcc0/mrcc_ctimer1_clkdiv.rs

mcxa_pac/mrcc0/
mrcc_ctimer1_clkdiv.rs
