mcxa_pac/mau0/
sys_ctlr.rs

1#[doc = "Register `SYS_CTLR` reader"]
2pub type R = crate::R<SysCtlrSpec>;
3#[doc = "Register `SYS_CTLR` writer"]
4pub type W = crate::W<SysCtlrSpec>;
5#[doc = "Automatic Clock Gating Enable\n\nValue on reset: 1"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum AcgEn {
9    #[doc = "0: Disable"]
10    Disable = 0,
11    #[doc = "1: Enable"]
12    Enable = 1,
13}
14impl From<AcgEn> for bool {
15    #[inline(always)]
16    fn from(variant: AcgEn) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `ACG_EN` reader - Automatic Clock Gating Enable"]
21pub type AcgEnR = crate::BitReader<AcgEn>;
22impl AcgEnR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> AcgEn {
26        match self.bits {
27            false => AcgEn::Disable,
28            true => AcgEn::Enable,
29        }
30    }
31    #[doc = "Disable"]
32    #[inline(always)]
33    pub fn is_disable(&self) -> bool {
34        *self == AcgEn::Disable
35    }
36    #[doc = "Enable"]
37    #[inline(always)]
38    pub fn is_enable(&self) -> bool {
39        *self == AcgEn::Enable
40    }
41}
42#[doc = "Field `ACG_EN` writer - Automatic Clock Gating Enable"]
43pub type AcgEnW<'a, REG> = crate::BitWriter<'a, REG, AcgEn>;
44impl<'a, REG> AcgEnW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Disable"]
49    #[inline(always)]
50    pub fn disable(self) -> &'a mut crate::W<REG> {
51        self.variant(AcgEn::Disable)
52    }
53    #[doc = "Enable"]
54    #[inline(always)]
55    pub fn enable(self) -> &'a mut crate::W<REG> {
56        self.variant(AcgEn::Enable)
57    }
58}
59impl R {
60    #[doc = "Bit 0 - Automatic Clock Gating Enable"]
61    #[inline(always)]
62    pub fn acg_en(&self) -> AcgEnR {
63        AcgEnR::new((self.bits & 1) != 0)
64    }
65}
66#[cfg(feature = "debug")]
67impl core::fmt::Debug for R {
68    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
69        f.debug_struct("SYS_CTLR").field("acg_en", &self.acg_en()).finish()
70    }
71}
72impl W {
73    #[doc = "Bit 0 - Automatic Clock Gating Enable"]
74    #[inline(always)]
75    pub fn acg_en(&mut self) -> AcgEnW<'_, SysCtlrSpec> {
76        AcgEnW::new(self, 0)
77    }
78}
79#[doc = "System Control\n\nYou can [`read`](crate::Reg::read) this register and get [`sys_ctlr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sys_ctlr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
80pub struct SysCtlrSpec;
81impl crate::RegisterSpec for SysCtlrSpec {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [`sys_ctlr::R`](R) reader structure"]
85impl crate::Readable for SysCtlrSpec {}
86#[doc = "`write(|w| ..)` method takes [`sys_ctlr::W`](W) writer structure"]
87impl crate::Writable for SysCtlrSpec {
88    type Safety = crate::Unsafe;
89}
90#[doc = "`reset()` method sets SYS_CTLR to value 0x01"]
91impl crate::Resettable for SysCtlrSpec {
92    const RESET_VALUE: u32 = 0x01;
93}
mcxa_pac/mau0/sys_ctlr.rs

mcxa_pac/mau0/
sys_ctlr.rs
