mcxa_pac/lpspi0/
cfgr1.rs

1#[doc = "Register `CFGR1` reader"]
2pub type R = crate::R<Cfgr1Spec>;
3#[doc = "Register `CFGR1` writer"]
4pub type W = crate::W<Cfgr1Spec>;
5#[doc = "Controller Mode\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Master {
9    #[doc = "0: Peripheral mode"]
10    SlaveMode = 0,
11    #[doc = "1: Controller mode"]
12    MasterMode = 1,
13}
14impl From<Master> for bool {
15    #[inline(always)]
16    fn from(variant: Master) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `MASTER` reader - Controller Mode"]
21pub type MasterR = crate::BitReader<Master>;
22impl MasterR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Master {
26        match self.bits {
27            false => Master::SlaveMode,
28            true => Master::MasterMode,
29        }
30    }
31    #[doc = "Peripheral mode"]
32    #[inline(always)]
33    pub fn is_slave_mode(&self) -> bool {
34        *self == Master::SlaveMode
35    }
36    #[doc = "Controller mode"]
37    #[inline(always)]
38    pub fn is_master_mode(&self) -> bool {
39        *self == Master::MasterMode
40    }
41}
42#[doc = "Field `MASTER` writer - Controller Mode"]
43pub type MasterW<'a, REG> = crate::BitWriter<'a, REG, Master>;
44impl<'a, REG> MasterW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Peripheral mode"]
49    #[inline(always)]
50    pub fn slave_mode(self) -> &'a mut crate::W<REG> {
51        self.variant(Master::SlaveMode)
52    }
53    #[doc = "Controller mode"]
54    #[inline(always)]
55    pub fn master_mode(self) -> &'a mut crate::W<REG> {
56        self.variant(Master::MasterMode)
57    }
58}
59#[doc = "Sample Point\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum Sample {
63    #[doc = "0: SCK edge"]
64    OnSckEdge = 0,
65    #[doc = "1: Delayed SCK edge"]
66    OnDelayedSckEdge = 1,
67}
68impl From<Sample> for bool {
69    #[inline(always)]
70    fn from(variant: Sample) -> Self {
71        variant as u8 != 0
72    }
73}
74#[doc = "Field `SAMPLE` reader - Sample Point"]
75pub type SampleR = crate::BitReader<Sample>;
76impl SampleR {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub const fn variant(&self) -> Sample {
80        match self.bits {
81            false => Sample::OnSckEdge,
82            true => Sample::OnDelayedSckEdge,
83        }
84    }
85    #[doc = "SCK edge"]
86    #[inline(always)]
87    pub fn is_on_sck_edge(&self) -> bool {
88        *self == Sample::OnSckEdge
89    }
90    #[doc = "Delayed SCK edge"]
91    #[inline(always)]
92    pub fn is_on_delayed_sck_edge(&self) -> bool {
93        *self == Sample::OnDelayedSckEdge
94    }
95}
96#[doc = "Field `SAMPLE` writer - Sample Point"]
97pub type SampleW<'a, REG> = crate::BitWriter<'a, REG, Sample>;
98impl<'a, REG> SampleW<'a, REG>
99where
100    REG: crate::Writable + crate::RegisterSpec,
101{
102    #[doc = "SCK edge"]
103    #[inline(always)]
104    pub fn on_sck_edge(self) -> &'a mut crate::W<REG> {
105        self.variant(Sample::OnSckEdge)
106    }
107    #[doc = "Delayed SCK edge"]
108    #[inline(always)]
109    pub fn on_delayed_sck_edge(self) -> &'a mut crate::W<REG> {
110        self.variant(Sample::OnDelayedSckEdge)
111    }
112}
113#[doc = "Automatic PCS\n\nValue on reset: 0"]
114#[cfg_attr(feature = "defmt", derive(defmt::Format))]
115#[derive(Clone, Copy, Debug, PartialEq, Eq)]
116pub enum Autopcs {
117    #[doc = "0: Disable"]
118    Disabled = 0,
119    #[doc = "1: Enable"]
120    Enabled = 1,
121}
122impl From<Autopcs> for bool {
123    #[inline(always)]
124    fn from(variant: Autopcs) -> Self {
125        variant as u8 != 0
126    }
127}
128#[doc = "Field `AUTOPCS` reader - Automatic PCS"]
129pub type AutopcsR = crate::BitReader<Autopcs>;
130impl AutopcsR {
131    #[doc = "Get enumerated values variant"]
132    #[inline(always)]
133    pub const fn variant(&self) -> Autopcs {
134        match self.bits {
135            false => Autopcs::Disabled,
136            true => Autopcs::Enabled,
137        }
138    }
139    #[doc = "Disable"]
140    #[inline(always)]
141    pub fn is_disabled(&self) -> bool {
142        *self == Autopcs::Disabled
143    }
144    #[doc = "Enable"]
145    #[inline(always)]
146    pub fn is_enabled(&self) -> bool {
147        *self == Autopcs::Enabled
148    }
149}
150#[doc = "Field `AUTOPCS` writer - Automatic PCS"]
151pub type AutopcsW<'a, REG> = crate::BitWriter<'a, REG, Autopcs>;
152impl<'a, REG> AutopcsW<'a, REG>
153where
154    REG: crate::Writable + crate::RegisterSpec,
155{
156    #[doc = "Disable"]
157    #[inline(always)]
158    pub fn disabled(self) -> &'a mut crate::W<REG> {
159        self.variant(Autopcs::Disabled)
160    }
161    #[doc = "Enable"]
162    #[inline(always)]
163    pub fn enabled(self) -> &'a mut crate::W<REG> {
164        self.variant(Autopcs::Enabled)
165    }
166}
167#[doc = "No Stall\n\nValue on reset: 0"]
168#[cfg_attr(feature = "defmt", derive(defmt::Format))]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum Nostall {
171    #[doc = "0: Disable"]
172    Disable = 0,
173    #[doc = "1: Enable"]
174    Enable = 1,
175}
176impl From<Nostall> for bool {
177    #[inline(always)]
178    fn from(variant: Nostall) -> Self {
179        variant as u8 != 0
180    }
181}
182#[doc = "Field `NOSTALL` reader - No Stall"]
183pub type NostallR = crate::BitReader<Nostall>;
184impl NostallR {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> Nostall {
188        match self.bits {
189            false => Nostall::Disable,
190            true => Nostall::Enable,
191        }
192    }
193    #[doc = "Disable"]
194    #[inline(always)]
195    pub fn is_disable(&self) -> bool {
196        *self == Nostall::Disable
197    }
198    #[doc = "Enable"]
199    #[inline(always)]
200    pub fn is_enable(&self) -> bool {
201        *self == Nostall::Enable
202    }
203}
204#[doc = "Field `NOSTALL` writer - No Stall"]
205pub type NostallW<'a, REG> = crate::BitWriter<'a, REG, Nostall>;
206impl<'a, REG> NostallW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Disable"]
211    #[inline(always)]
212    pub fn disable(self) -> &'a mut crate::W<REG> {
213        self.variant(Nostall::Disable)
214    }
215    #[doc = "Enable"]
216    #[inline(always)]
217    pub fn enable(self) -> &'a mut crate::W<REG> {
218        self.variant(Nostall::Enable)
219    }
220}
221#[doc = "Partial Enable\n\nValue on reset: 0"]
222#[cfg_attr(feature = "defmt", derive(defmt::Format))]
223#[derive(Clone, Copy, Debug, PartialEq, Eq)]
224pub enum Partial {
225    #[doc = "0: Discard"]
226    Discarded = 0,
227    #[doc = "1: Store"]
228    Stored = 1,
229}
230impl From<Partial> for bool {
231    #[inline(always)]
232    fn from(variant: Partial) -> Self {
233        variant as u8 != 0
234    }
235}
236#[doc = "Field `PARTIAL` reader - Partial Enable"]
237pub type PartialR = crate::BitReader<Partial>;
238impl PartialR {
239    #[doc = "Get enumerated values variant"]
240    #[inline(always)]
241    pub const fn variant(&self) -> Partial {
242        match self.bits {
243            false => Partial::Discarded,
244            true => Partial::Stored,
245        }
246    }
247    #[doc = "Discard"]
248    #[inline(always)]
249    pub fn is_discarded(&self) -> bool {
250        *self == Partial::Discarded
251    }
252    #[doc = "Store"]
253    #[inline(always)]
254    pub fn is_stored(&self) -> bool {
255        *self == Partial::Stored
256    }
257}
258#[doc = "Field `PARTIAL` writer - Partial Enable"]
259pub type PartialW<'a, REG> = crate::BitWriter<'a, REG, Partial>;
260impl<'a, REG> PartialW<'a, REG>
261where
262    REG: crate::Writable + crate::RegisterSpec,
263{
264    #[doc = "Discard"]
265    #[inline(always)]
266    pub fn discarded(self) -> &'a mut crate::W<REG> {
267        self.variant(Partial::Discarded)
268    }
269    #[doc = "Store"]
270    #[inline(always)]
271    pub fn stored(self) -> &'a mut crate::W<REG> {
272        self.variant(Partial::Stored)
273    }
274}
275#[doc = "Peripheral Chip Select Polarity\n\nValue on reset: 0"]
276#[cfg_attr(feature = "defmt", derive(defmt::Format))]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278#[repr(u8)]
279pub enum Pcspol {
280    #[doc = "0: Active low"]
281    Discarded = 0,
282    #[doc = "1: Active high"]
283    Stored = 1,
284}
285impl From<Pcspol> for u8 {
286    #[inline(always)]
287    fn from(variant: Pcspol) -> Self {
288        variant as _
289    }
290}
291impl crate::FieldSpec for Pcspol {
292    type Ux = u8;
293}
294impl crate::IsEnum for Pcspol {}
295#[doc = "Field `PCSPOL` reader - Peripheral Chip Select Polarity"]
296pub type PcspolR = crate::FieldReader<Pcspol>;
297impl PcspolR {
298    #[doc = "Get enumerated values variant"]
299    #[inline(always)]
300    pub const fn variant(&self) -> Option<Pcspol> {
301        match self.bits {
302            0 => Some(Pcspol::Discarded),
303            1 => Some(Pcspol::Stored),
304            _ => None,
305        }
306    }
307    #[doc = "Active low"]
308    #[inline(always)]
309    pub fn is_discarded(&self) -> bool {
310        *self == Pcspol::Discarded
311    }
312    #[doc = "Active high"]
313    #[inline(always)]
314    pub fn is_stored(&self) -> bool {
315        *self == Pcspol::Stored
316    }
317}
318#[doc = "Field `PCSPOL` writer - Peripheral Chip Select Polarity"]
319pub type PcspolW<'a, REG> = crate::FieldWriter<'a, REG, 4, Pcspol>;
320impl<'a, REG> PcspolW<'a, REG>
321where
322    REG: crate::Writable + crate::RegisterSpec,
323    REG::Ux: From<u8>,
324{
325    #[doc = "Active low"]
326    #[inline(always)]
327    pub fn discarded(self) -> &'a mut crate::W<REG> {
328        self.variant(Pcspol::Discarded)
329    }
330    #[doc = "Active high"]
331    #[inline(always)]
332    pub fn stored(self) -> &'a mut crate::W<REG> {
333        self.variant(Pcspol::Stored)
334    }
335}
336#[doc = "Match Configuration\n\nValue on reset: 0"]
337#[cfg_attr(feature = "defmt", derive(defmt::Format))]
338#[derive(Clone, Copy, Debug, PartialEq, Eq)]
339#[repr(u8)]
340pub enum Matcfg {
341    #[doc = "0: Match is disabled"]
342    Disabled = 0,
343    #[doc = "2: Match first data word with compare word"]
344    EnabledFirstdatamatch = 2,
345    #[doc = "3: Match any data word with compare word"]
346    EnabledAnydatamatch = 3,
347    #[doc = "4: Sequential match, first data word"]
348    EnabledDatamatch100 = 4,
349    #[doc = "5: Sequential match, any data word"]
350    EnabledDatamatch101 = 5,
351    #[doc = "6: Match first data word (masked) with compare word (masked)"]
352    EnabledDatamatch110 = 6,
353    #[doc = "7: Match any data word (masked) with compare word (masked)"]
354    EnabledDatamatch111 = 7,
355}
356impl From<Matcfg> for u8 {
357    #[inline(always)]
358    fn from(variant: Matcfg) -> Self {
359        variant as _
360    }
361}
362impl crate::FieldSpec for Matcfg {
363    type Ux = u8;
364}
365impl crate::IsEnum for Matcfg {}
366#[doc = "Field `MATCFG` reader - Match Configuration"]
367pub type MatcfgR = crate::FieldReader<Matcfg>;
368impl MatcfgR {
369    #[doc = "Get enumerated values variant"]
370    #[inline(always)]
371    pub const fn variant(&self) -> Option<Matcfg> {
372        match self.bits {
373            0 => Some(Matcfg::Disabled),
374            2 => Some(Matcfg::EnabledFirstdatamatch),
375            3 => Some(Matcfg::EnabledAnydatamatch),
376            4 => Some(Matcfg::EnabledDatamatch100),
377            5 => Some(Matcfg::EnabledDatamatch101),
378            6 => Some(Matcfg::EnabledDatamatch110),
379            7 => Some(Matcfg::EnabledDatamatch111),
380            _ => None,
381        }
382    }
383    #[doc = "Match is disabled"]
384    #[inline(always)]
385    pub fn is_disabled(&self) -> bool {
386        *self == Matcfg::Disabled
387    }
388    #[doc = "Match first data word with compare word"]
389    #[inline(always)]
390    pub fn is_enabled_firstdatamatch(&self) -> bool {
391        *self == Matcfg::EnabledFirstdatamatch
392    }
393    #[doc = "Match any data word with compare word"]
394    #[inline(always)]
395    pub fn is_enabled_anydatamatch(&self) -> bool {
396        *self == Matcfg::EnabledAnydatamatch
397    }
398    #[doc = "Sequential match, first data word"]
399    #[inline(always)]
400    pub fn is_enabled_datamatch_100(&self) -> bool {
401        *self == Matcfg::EnabledDatamatch100
402    }
403    #[doc = "Sequential match, any data word"]
404    #[inline(always)]
405    pub fn is_enabled_datamatch_101(&self) -> bool {
406        *self == Matcfg::EnabledDatamatch101
407    }
408    #[doc = "Match first data word (masked) with compare word (masked)"]
409    #[inline(always)]
410    pub fn is_enabled_datamatch_110(&self) -> bool {
411        *self == Matcfg::EnabledDatamatch110
412    }
413    #[doc = "Match any data word (masked) with compare word (masked)"]
414    #[inline(always)]
415    pub fn is_enabled_datamatch_111(&self) -> bool {
416        *self == Matcfg::EnabledDatamatch111
417    }
418}
419#[doc = "Field `MATCFG` writer - Match Configuration"]
420pub type MatcfgW<'a, REG> = crate::FieldWriter<'a, REG, 3, Matcfg>;
421impl<'a, REG> MatcfgW<'a, REG>
422where
423    REG: crate::Writable + crate::RegisterSpec,
424    REG::Ux: From<u8>,
425{
426    #[doc = "Match is disabled"]
427    #[inline(always)]
428    pub fn disabled(self) -> &'a mut crate::W<REG> {
429        self.variant(Matcfg::Disabled)
430    }
431    #[doc = "Match first data word with compare word"]
432    #[inline(always)]
433    pub fn enabled_firstdatamatch(self) -> &'a mut crate::W<REG> {
434        self.variant(Matcfg::EnabledFirstdatamatch)
435    }
436    #[doc = "Match any data word with compare word"]
437    #[inline(always)]
438    pub fn enabled_anydatamatch(self) -> &'a mut crate::W<REG> {
439        self.variant(Matcfg::EnabledAnydatamatch)
440    }
441    #[doc = "Sequential match, first data word"]
442    #[inline(always)]
443    pub fn enabled_datamatch_100(self) -> &'a mut crate::W<REG> {
444        self.variant(Matcfg::EnabledDatamatch100)
445    }
446    #[doc = "Sequential match, any data word"]
447    #[inline(always)]
448    pub fn enabled_datamatch_101(self) -> &'a mut crate::W<REG> {
449        self.variant(Matcfg::EnabledDatamatch101)
450    }
451    #[doc = "Match first data word (masked) with compare word (masked)"]
452    #[inline(always)]
453    pub fn enabled_datamatch_110(self) -> &'a mut crate::W<REG> {
454        self.variant(Matcfg::EnabledDatamatch110)
455    }
456    #[doc = "Match any data word (masked) with compare word (masked)"]
457    #[inline(always)]
458    pub fn enabled_datamatch_111(self) -> &'a mut crate::W<REG> {
459        self.variant(Matcfg::EnabledDatamatch111)
460    }
461}
462#[doc = "Pin Configuration\n\nValue on reset: 0"]
463#[cfg_attr(feature = "defmt", derive(defmt::Format))]
464#[derive(Clone, Copy, Debug, PartialEq, Eq)]
465#[repr(u8)]
466pub enum Pincfg {
467    #[doc = "0: SIN is used for input data; SOUT is used for output data"]
468    SinInSoutOut = 0,
469    #[doc = "1: SIN is used for both input and output data; only half-duplex serial transfers are supported"]
470    SinBothInOut = 1,
471    #[doc = "2: SOUT is used for both input and output data; only half-duplex serial transfers are supported"]
472    SoutBothInOut = 2,
473    #[doc = "3: SOUT is used for input data; SIN is used for output data"]
474    SoutInSinOut = 3,
475}
476impl From<Pincfg> for u8 {
477    #[inline(always)]
478    fn from(variant: Pincfg) -> Self {
479        variant as _
480    }
481}
482impl crate::FieldSpec for Pincfg {
483    type Ux = u8;
484}
485impl crate::IsEnum for Pincfg {}
486#[doc = "Field `PINCFG` reader - Pin Configuration"]
487pub type PincfgR = crate::FieldReader<Pincfg>;
488impl PincfgR {
489    #[doc = "Get enumerated values variant"]
490    #[inline(always)]
491    pub const fn variant(&self) -> Pincfg {
492        match self.bits {
493            0 => Pincfg::SinInSoutOut,
494            1 => Pincfg::SinBothInOut,
495            2 => Pincfg::SoutBothInOut,
496            3 => Pincfg::SoutInSinOut,
497            _ => unreachable!(),
498        }
499    }
500    #[doc = "SIN is used for input data; SOUT is used for output data"]
501    #[inline(always)]
502    pub fn is_sin_in_sout_out(&self) -> bool {
503        *self == Pincfg::SinInSoutOut
504    }
505    #[doc = "SIN is used for both input and output data; only half-duplex serial transfers are supported"]
506    #[inline(always)]
507    pub fn is_sin_both_in_out(&self) -> bool {
508        *self == Pincfg::SinBothInOut
509    }
510    #[doc = "SOUT is used for both input and output data; only half-duplex serial transfers are supported"]
511    #[inline(always)]
512    pub fn is_sout_both_in_out(&self) -> bool {
513        *self == Pincfg::SoutBothInOut
514    }
515    #[doc = "SOUT is used for input data; SIN is used for output data"]
516    #[inline(always)]
517    pub fn is_sout_in_sin_out(&self) -> bool {
518        *self == Pincfg::SoutInSinOut
519    }
520}
521#[doc = "Field `PINCFG` writer - Pin Configuration"]
522pub type PincfgW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pincfg, crate::Safe>;
523impl<'a, REG> PincfgW<'a, REG>
524where
525    REG: crate::Writable + crate::RegisterSpec,
526    REG::Ux: From<u8>,
527{
528    #[doc = "SIN is used for input data; SOUT is used for output data"]
529    #[inline(always)]
530    pub fn sin_in_sout_out(self) -> &'a mut crate::W<REG> {
531        self.variant(Pincfg::SinInSoutOut)
532    }
533    #[doc = "SIN is used for both input and output data; only half-duplex serial transfers are supported"]
534    #[inline(always)]
535    pub fn sin_both_in_out(self) -> &'a mut crate::W<REG> {
536        self.variant(Pincfg::SinBothInOut)
537    }
538    #[doc = "SOUT is used for both input and output data; only half-duplex serial transfers are supported"]
539    #[inline(always)]
540    pub fn sout_both_in_out(self) -> &'a mut crate::W<REG> {
541        self.variant(Pincfg::SoutBothInOut)
542    }
543    #[doc = "SOUT is used for input data; SIN is used for output data"]
544    #[inline(always)]
545    pub fn sout_in_sin_out(self) -> &'a mut crate::W<REG> {
546        self.variant(Pincfg::SoutInSinOut)
547    }
548}
549#[doc = "Output Configuration\n\nValue on reset: 0"]
550#[cfg_attr(feature = "defmt", derive(defmt::Format))]
551#[derive(Clone, Copy, Debug, PartialEq, Eq)]
552pub enum Outcfg {
553    #[doc = "0: Retain last value"]
554    RetainLastvalue = 0,
555    #[doc = "1: 3-stated"]
556    Tristated = 1,
557}
558impl From<Outcfg> for bool {
559    #[inline(always)]
560    fn from(variant: Outcfg) -> Self {
561        variant as u8 != 0
562    }
563}
564#[doc = "Field `OUTCFG` reader - Output Configuration"]
565pub type OutcfgR = crate::BitReader<Outcfg>;
566impl OutcfgR {
567    #[doc = "Get enumerated values variant"]
568    #[inline(always)]
569    pub const fn variant(&self) -> Outcfg {
570        match self.bits {
571            false => Outcfg::RetainLastvalue,
572            true => Outcfg::Tristated,
573        }
574    }
575    #[doc = "Retain last value"]
576    #[inline(always)]
577    pub fn is_retain_lastvalue(&self) -> bool {
578        *self == Outcfg::RetainLastvalue
579    }
580    #[doc = "3-stated"]
581    #[inline(always)]
582    pub fn is_tristated(&self) -> bool {
583        *self == Outcfg::Tristated
584    }
585}
586#[doc = "Field `OUTCFG` writer - Output Configuration"]
587pub type OutcfgW<'a, REG> = crate::BitWriter<'a, REG, Outcfg>;
588impl<'a, REG> OutcfgW<'a, REG>
589where
590    REG: crate::Writable + crate::RegisterSpec,
591{
592    #[doc = "Retain last value"]
593    #[inline(always)]
594    pub fn retain_lastvalue(self) -> &'a mut crate::W<REG> {
595        self.variant(Outcfg::RetainLastvalue)
596    }
597    #[doc = "3-stated"]
598    #[inline(always)]
599    pub fn tristated(self) -> &'a mut crate::W<REG> {
600        self.variant(Outcfg::Tristated)
601    }
602}
603#[doc = "Peripheral Chip Select Configuration\n\nValue on reset: 0"]
604#[cfg_attr(feature = "defmt", derive(defmt::Format))]
605#[derive(Clone, Copy, Debug, PartialEq, Eq)]
606pub enum Pcscfg {
607    #[doc = "0: PCS\\[3:2\\] configured for chip select function"]
608    ChipSelect = 0,
609    #[doc = "1: PCS\\[3:2\\] configured for half-duplex 4-bit transfers (PCS\\[3:2\\] = DATA\\[3:2\\])"]
610    Halfduplex4bit = 1,
611}
612impl From<Pcscfg> for bool {
613    #[inline(always)]
614    fn from(variant: Pcscfg) -> Self {
615        variant as u8 != 0
616    }
617}
618#[doc = "Field `PCSCFG` reader - Peripheral Chip Select Configuration"]
619pub type PcscfgR = crate::BitReader<Pcscfg>;
620impl PcscfgR {
621    #[doc = "Get enumerated values variant"]
622    #[inline(always)]
623    pub const fn variant(&self) -> Pcscfg {
624        match self.bits {
625            false => Pcscfg::ChipSelect,
626            true => Pcscfg::Halfduplex4bit,
627        }
628    }
629    #[doc = "PCS\\[3:2\\] configured for chip select function"]
630    #[inline(always)]
631    pub fn is_chip_select(&self) -> bool {
632        *self == Pcscfg::ChipSelect
633    }
634    #[doc = "PCS\\[3:2\\] configured for half-duplex 4-bit transfers (PCS\\[3:2\\] = DATA\\[3:2\\])"]
635    #[inline(always)]
636    pub fn is_halfduplex4bit(&self) -> bool {
637        *self == Pcscfg::Halfduplex4bit
638    }
639}
640#[doc = "Field `PCSCFG` writer - Peripheral Chip Select Configuration"]
641pub type PcscfgW<'a, REG> = crate::BitWriter<'a, REG, Pcscfg>;
642impl<'a, REG> PcscfgW<'a, REG>
643where
644    REG: crate::Writable + crate::RegisterSpec,
645{
646    #[doc = "PCS\\[3:2\\] configured for chip select function"]
647    #[inline(always)]
648    pub fn chip_select(self) -> &'a mut crate::W<REG> {
649        self.variant(Pcscfg::ChipSelect)
650    }
651    #[doc = "PCS\\[3:2\\] configured for half-duplex 4-bit transfers (PCS\\[3:2\\] = DATA\\[3:2\\])"]
652    #[inline(always)]
653    pub fn halfduplex4bit(self) -> &'a mut crate::W<REG> {
654        self.variant(Pcscfg::Halfduplex4bit)
655    }
656}
657impl R {
658    #[doc = "Bit 0 - Controller Mode"]
659    #[inline(always)]
660    pub fn master(&self) -> MasterR {
661        MasterR::new((self.bits & 1) != 0)
662    }
663    #[doc = "Bit 1 - Sample Point"]
664    #[inline(always)]
665    pub fn sample(&self) -> SampleR {
666        SampleR::new(((self.bits >> 1) & 1) != 0)
667    }
668    #[doc = "Bit 2 - Automatic PCS"]
669    #[inline(always)]
670    pub fn autopcs(&self) -> AutopcsR {
671        AutopcsR::new(((self.bits >> 2) & 1) != 0)
672    }
673    #[doc = "Bit 3 - No Stall"]
674    #[inline(always)]
675    pub fn nostall(&self) -> NostallR {
676        NostallR::new(((self.bits >> 3) & 1) != 0)
677    }
678    #[doc = "Bit 4 - Partial Enable"]
679    #[inline(always)]
680    pub fn partial(&self) -> PartialR {
681        PartialR::new(((self.bits >> 4) & 1) != 0)
682    }
683    #[doc = "Bits 8:11 - Peripheral Chip Select Polarity"]
684    #[inline(always)]
685    pub fn pcspol(&self) -> PcspolR {
686        PcspolR::new(((self.bits >> 8) & 0x0f) as u8)
687    }
688    #[doc = "Bits 16:18 - Match Configuration"]
689    #[inline(always)]
690    pub fn matcfg(&self) -> MatcfgR {
691        MatcfgR::new(((self.bits >> 16) & 7) as u8)
692    }
693    #[doc = "Bits 24:25 - Pin Configuration"]
694    #[inline(always)]
695    pub fn pincfg(&self) -> PincfgR {
696        PincfgR::new(((self.bits >> 24) & 3) as u8)
697    }
698    #[doc = "Bit 26 - Output Configuration"]
699    #[inline(always)]
700    pub fn outcfg(&self) -> OutcfgR {
701        OutcfgR::new(((self.bits >> 26) & 1) != 0)
702    }
703    #[doc = "Bit 27 - Peripheral Chip Select Configuration"]
704    #[inline(always)]
705    pub fn pcscfg(&self) -> PcscfgR {
706        PcscfgR::new(((self.bits >> 27) & 1) != 0)
707    }
708}
709#[cfg(feature = "debug")]
710impl core::fmt::Debug for R {
711    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
712        f.debug_struct("CFGR1")
713            .field("master", &self.master())
714            .field("sample", &self.sample())
715            .field("autopcs", &self.autopcs())
716            .field("nostall", &self.nostall())
717            .field("partial", &self.partial())
718            .field("pcspol", &self.pcspol())
719            .field("matcfg", &self.matcfg())
720            .field("pincfg", &self.pincfg())
721            .field("outcfg", &self.outcfg())
722            .field("pcscfg", &self.pcscfg())
723            .finish()
724    }
725}
726impl W {
727    #[doc = "Bit 0 - Controller Mode"]
728    #[inline(always)]
729    pub fn master(&mut self) -> MasterW<'_, Cfgr1Spec> {
730        MasterW::new(self, 0)
731    }
732    #[doc = "Bit 1 - Sample Point"]
733    #[inline(always)]
734    pub fn sample(&mut self) -> SampleW<'_, Cfgr1Spec> {
735        SampleW::new(self, 1)
736    }
737    #[doc = "Bit 2 - Automatic PCS"]
738    #[inline(always)]
739    pub fn autopcs(&mut self) -> AutopcsW<'_, Cfgr1Spec> {
740        AutopcsW::new(self, 2)
741    }
742    #[doc = "Bit 3 - No Stall"]
743    #[inline(always)]
744    pub fn nostall(&mut self) -> NostallW<'_, Cfgr1Spec> {
745        NostallW::new(self, 3)
746    }
747    #[doc = "Bit 4 - Partial Enable"]
748    #[inline(always)]
749    pub fn partial(&mut self) -> PartialW<'_, Cfgr1Spec> {
750        PartialW::new(self, 4)
751    }
752    #[doc = "Bits 8:11 - Peripheral Chip Select Polarity"]
753    #[inline(always)]
754    pub fn pcspol(&mut self) -> PcspolW<'_, Cfgr1Spec> {
755        PcspolW::new(self, 8)
756    }
757    #[doc = "Bits 16:18 - Match Configuration"]
758    #[inline(always)]
759    pub fn matcfg(&mut self) -> MatcfgW<'_, Cfgr1Spec> {
760        MatcfgW::new(self, 16)
761    }
762    #[doc = "Bits 24:25 - Pin Configuration"]
763    #[inline(always)]
764    pub fn pincfg(&mut self) -> PincfgW<'_, Cfgr1Spec> {
765        PincfgW::new(self, 24)
766    }
767    #[doc = "Bit 26 - Output Configuration"]
768    #[inline(always)]
769    pub fn outcfg(&mut self) -> OutcfgW<'_, Cfgr1Spec> {
770        OutcfgW::new(self, 26)
771    }
772    #[doc = "Bit 27 - Peripheral Chip Select Configuration"]
773    #[inline(always)]
774    pub fn pcscfg(&mut self) -> PcscfgW<'_, Cfgr1Spec> {
775        PcscfgW::new(self, 27)
776    }
777}
778#[doc = "Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`cfgr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfgr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
779pub struct Cfgr1Spec;
780impl crate::RegisterSpec for Cfgr1Spec {
781    type Ux = u32;
782}
783#[doc = "`read()` method returns [`cfgr1::R`](R) reader structure"]
784impl crate::Readable for Cfgr1Spec {}
785#[doc = "`write(|w| ..)` method takes [`cfgr1::W`](W) writer structure"]
786impl crate::Writable for Cfgr1Spec {
787    type Safety = crate::Unsafe;
788}
789#[doc = "`reset()` method sets CFGR1 to value 0"]
790impl crate::Resettable for Cfgr1Spec {}
mcxa_pac/lpspi0/cfgr1.rs

mcxa_pac/lpspi0/
cfgr1.rs
