mcxa_pac/lpspi0/
ccr1.rs

1#[doc = "Register `CCR1` reader"]
2pub type R = crate::R<Ccr1Spec>;
3#[doc = "Register `CCR1` writer"]
4pub type W = crate::W<Ccr1Spec>;
5#[doc = "Field `SCKSET` reader - SCK Setup"]
6pub type ScksetR = crate::FieldReader;
7#[doc = "Field `SCKSET` writer - SCK Setup"]
8pub type ScksetW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `SCKHLD` reader - SCK Hold"]
10pub type SckhldR = crate::FieldReader;
11#[doc = "Field `SCKHLD` writer - SCK Hold"]
12pub type SckhldW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `PCSPCS` reader - PCS to PCS Delay"]
14pub type PcspcsR = crate::FieldReader;
15#[doc = "Field `PCSPCS` writer - PCS to PCS Delay"]
16pub type PcspcsW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
17#[doc = "Field `SCKSCK` reader - SCK Inter-Frame Delay"]
18pub type ScksckR = crate::FieldReader;
19#[doc = "Field `SCKSCK` writer - SCK Inter-Frame Delay"]
20pub type ScksckW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
21impl R {
22    #[doc = "Bits 0:7 - SCK Setup"]
23    #[inline(always)]
24    pub fn sckset(&self) -> ScksetR {
25        ScksetR::new((self.bits & 0xff) as u8)
26    }
27    #[doc = "Bits 8:15 - SCK Hold"]
28    #[inline(always)]
29    pub fn sckhld(&self) -> SckhldR {
30        SckhldR::new(((self.bits >> 8) & 0xff) as u8)
31    }
32    #[doc = "Bits 16:23 - PCS to PCS Delay"]
33    #[inline(always)]
34    pub fn pcspcs(&self) -> PcspcsR {
35        PcspcsR::new(((self.bits >> 16) & 0xff) as u8)
36    }
37    #[doc = "Bits 24:31 - SCK Inter-Frame Delay"]
38    #[inline(always)]
39    pub fn scksck(&self) -> ScksckR {
40        ScksckR::new(((self.bits >> 24) & 0xff) as u8)
41    }
42}
43#[cfg(feature = "debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("CCR1")
47            .field("sckset", &self.sckset())
48            .field("sckhld", &self.sckhld())
49            .field("pcspcs", &self.pcspcs())
50            .field("scksck", &self.scksck())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bits 0:7 - SCK Setup"]
56    #[inline(always)]
57    pub fn sckset(&mut self) -> ScksetW<'_, Ccr1Spec> {
58        ScksetW::new(self, 0)
59    }
60    #[doc = "Bits 8:15 - SCK Hold"]
61    #[inline(always)]
62    pub fn sckhld(&mut self) -> SckhldW<'_, Ccr1Spec> {
63        SckhldW::new(self, 8)
64    }
65    #[doc = "Bits 16:23 - PCS to PCS Delay"]
66    #[inline(always)]
67    pub fn pcspcs(&mut self) -> PcspcsW<'_, Ccr1Spec> {
68        PcspcsW::new(self, 16)
69    }
70    #[doc = "Bits 24:31 - SCK Inter-Frame Delay"]
71    #[inline(always)]
72    pub fn scksck(&mut self) -> ScksckW<'_, Ccr1Spec> {
73        ScksckW::new(self, 24)
74    }
75}
76#[doc = "Clock Configuration 1\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct Ccr1Spec;
78impl crate::RegisterSpec for Ccr1Spec {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`ccr1::R`](R) reader structure"]
82impl crate::Readable for Ccr1Spec {}
83#[doc = "`write(|w| ..)` method takes [`ccr1::W`](W) writer structure"]
84impl crate::Writable for Ccr1Spec {
85    type Safety = crate::Unsafe;
86}
87#[doc = "`reset()` method sets CCR1 to value 0"]
88impl crate::Resettable for Ccr1Spec {}
mcxa_pac/lpspi0/ccr1.rs

mcxa_pac/lpspi0/
ccr1.rs
