mcxa_pac/lpi2c0/
mcfgr2.rs

1#[doc = "Register `MCFGR2` reader"]
2pub type R = crate::R<Mcfgr2Spec>;
3#[doc = "Register `MCFGR2` writer"]
4pub type W = crate::W<Mcfgr2Spec>;
5#[doc = "Field `BUSIDLE` reader - Bus Idle Timeout"]
6pub type BusidleR = crate::FieldReader<u16>;
7#[doc = "Field `BUSIDLE` writer - Bus Idle Timeout"]
8pub type BusidleW<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9#[doc = "Field `FILTSCL` reader - Glitch Filter SCL"]
10pub type FiltsclR = crate::FieldReader;
11#[doc = "Field `FILTSCL` writer - Glitch Filter SCL"]
12pub type FiltsclW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `FILTSDA` reader - Glitch Filter SDA"]
14pub type FiltsdaR = crate::FieldReader;
15#[doc = "Field `FILTSDA` writer - Glitch Filter SDA"]
16pub type FiltsdaW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17impl R {
18    #[doc = "Bits 0:11 - Bus Idle Timeout"]
19    #[inline(always)]
20    pub fn busidle(&self) -> BusidleR {
21        BusidleR::new((self.bits & 0x0fff) as u16)
22    }
23    #[doc = "Bits 16:19 - Glitch Filter SCL"]
24    #[inline(always)]
25    pub fn filtscl(&self) -> FiltsclR {
26        FiltsclR::new(((self.bits >> 16) & 0x0f) as u8)
27    }
28    #[doc = "Bits 24:27 - Glitch Filter SDA"]
29    #[inline(always)]
30    pub fn filtsda(&self) -> FiltsdaR {
31        FiltsdaR::new(((self.bits >> 24) & 0x0f) as u8)
32    }
33}
34#[cfg(feature = "debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("MCFGR2")
38            .field("busidle", &self.busidle())
39            .field("filtscl", &self.filtscl())
40            .field("filtsda", &self.filtsda())
41            .finish()
42    }
43}
44impl W {
45    #[doc = "Bits 0:11 - Bus Idle Timeout"]
46    #[inline(always)]
47    pub fn busidle(&mut self) -> BusidleW<'_, Mcfgr2Spec> {
48        BusidleW::new(self, 0)
49    }
50    #[doc = "Bits 16:19 - Glitch Filter SCL"]
51    #[inline(always)]
52    pub fn filtscl(&mut self) -> FiltsclW<'_, Mcfgr2Spec> {
53        FiltsclW::new(self, 16)
54    }
55    #[doc = "Bits 24:27 - Glitch Filter SDA"]
56    #[inline(always)]
57    pub fn filtsda(&mut self) -> FiltsdaW<'_, Mcfgr2Spec> {
58        FiltsdaW::new(self, 24)
59    }
60}
61#[doc = "Controller Configuration 2\n\nYou can [`read`](crate::Reg::read) this register and get [`mcfgr2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcfgr2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
62pub struct Mcfgr2Spec;
63impl crate::RegisterSpec for Mcfgr2Spec {
64    type Ux = u32;
65}
66#[doc = "`read()` method returns [`mcfgr2::R`](R) reader structure"]
67impl crate::Readable for Mcfgr2Spec {}
68#[doc = "`write(|w| ..)` method takes [`mcfgr2::W`](W) writer structure"]
69impl crate::Writable for Mcfgr2Spec {
70    type Safety = crate::Unsafe;
71}
72#[doc = "`reset()` method sets MCFGR2 to value 0"]
73impl crate::Resettable for Mcfgr2Spec {}
mcxa_pac/lpi2c0/mcfgr2.rs

mcxa_pac/lpi2c0/
mcfgr2.rs
