mcxa_pac/
inputmux0.rs

1#[repr(C)]
2#[cfg_attr(feature = "debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    _reserved0: [u8; 0x20],
6    ctimer0cap: [Ctimer0cap; 4],
7    timer0trig: Timer0trig,
8    _reserved2: [u8; 0x0c],
9    ctimer1cap: [Ctimer1cap; 4],
10    timer1trig: Timer1trig,
11    _reserved4: [u8; 0x0c],
12    ctimer2cap: [Ctimer2cap; 4],
13    timer2trig: Timer2trig,
14    _reserved6: [u8; 0x2c],
15    smart_dma_trig: [SmartDmaTrig; 8],
16    _reserved7: [u8; 0xc0],
17    freqmeas_ref: FreqmeasRef,
18    freqmeas_tar: FreqmeasTar,
19    _reserved9: [u8; 0x18],
20    ctimer3cap: [Ctimer3cap; 4],
21    timer3trig: Timer3trig,
22    _reserved11: [u8; 0x0c],
23    ctimer4cap: [Ctimer4cap; 4],
24    timer4trig: Timer4trig,
25    _reserved13: [u8; 0x2c],
26    aoi1_input: [Aoi1Input; 16],
27    _reserved14: [u8; 0x20],
28    cmp0_trig: Cmp0Trig,
29    _reserved15: [u8; 0x1c],
30    adc0_trig: [Adc0Trig; 4],
31    _reserved16: [u8; 0x10],
32    adc2_trig: [Adc2Trig; 4],
33    _reserved17: [u8; 0x10],
34    adc1_trig: [Adc1Trig; 4],
35    _reserved18: [u8; 0x10],
36    adc3_trig: [Adc3Trig; 4],
37    _reserved19: [u8; 0x10],
38    dac0_trig: Dac0Trig,
39    _reserved20: [u8; 0x5c],
40    qdc0_trig: Qdc0Trig,
41    qdc0_home: Qdc0Home,
42    qdc0_index: Qdc0Index,
43    qdc0_phaseb: Qdc0Phaseb,
44    qdc0_phasea: Qdc0Phasea,
45    qdc0_icap1: Qdc0Icap1,
46    qdc0_icap2: Qdc0Icap2,
47    qdc0_icap3: Qdc0Icap3,
48    qdc1_trig: Qdc1Trig,
49    qdc1_home: Qdc1Home,
50    qdc1_index: Qdc1Index,
51    qdc1_phaseb: Qdc1Phaseb,
52    qdc1_phasea: Qdc1Phasea,
53    qdc1_icap1: Qdc1Icap1,
54    qdc1_icap2: Qdc1Icap2,
55    qdc1_icap3: Qdc1Icap3,
56    flex_pwm0_sm0_exta0: FlexPwm0Sm0Exta0,
57    flex_pwm0_sm0_extsync: FlexPwm0Sm0Extsync,
58    flex_pwm0_sm1_exta: FlexPwm0Sm1Exta,
59    flex_pwm0_sm1_extsync: FlexPwm0Sm1Extsync,
60    flex_pwm0_sm2_exta: FlexPwm0Sm2Exta,
61    flex_pwm0_sm2_extsync: FlexPwm0Sm2Extsync,
62    flex_pwm0_sm3_exta0: FlexPwm0Sm3Exta0,
63    flex_pwm0_sm3_extsync: FlexPwm0Sm3Extsync,
64    flex_pwm0_fault: [FlexPwm0Fault; 4],
65    flex_pwm0_force: FlexPwm0Force,
66    _reserved46: [u8; 0x0c],
67    flex_pwm1_sm0_exta0: FlexPwm1Sm0Exta0,
68    flex_pwm1_sm0_extsync: FlexPwm1Sm0Extsync,
69    flex_pwm1_sm1_exta: FlexPwm1Sm1Exta,
70    flex_pwm1_sm1_extsync: FlexPwm1Sm1Extsync,
71    flex_pwm1_sm2_exta: FlexPwm1Sm2Exta,
72    flex_pwm1_sm2_extsync: FlexPwm1Sm2Extsync,
73    flex_pwm1_sm3_exta0: FlexPwm1Sm3Exta0,
74    flex_pwm1_sm3_extsync: FlexPwm1Sm3Extsync,
75    flex_pwm1_fault: [FlexPwm1Fault; 4],
76    flex_pwm1_force: FlexPwm1Force,
77    _reserved56: [u8; 0x0c],
78    pwm0_ext_clk: Pwm0ExtClk,
79    pwm1_ext_clk: Pwm1ExtClk,
80    _reserved58: [u8; 0x18],
81    aoi0_input: [Aoi0Input; 16],
82    usbfs_trig: UsbfsTrig,
83    _reserved60: [u8; 0x3c],
84    ext_trig: [ExtTrig; 8],
85    cmp1_trig: Cmp1Trig,
86    _reserved62: [u8; 0x1c],
87    cmp2_trig: Cmp2Trig,
88    _reserved63: [u8; 0x3c],
89    lpi2c2_trig: Lpi2c2Trig,
90    _reserved64: [u8; 0x1c],
91    lpi2c3_trig: Lpi2c3Trig,
92    _reserved65: [u8; 0x3c],
93    lpi2c0_trig: Lpi2c0Trig,
94    _reserved66: [u8; 0x1c],
95    lpi2c1_trig: Lpi2c1Trig,
96    _reserved67: [u8; 0x1c],
97    lpspi0_trig: Lpspi0Trig,
98    _reserved68: [u8; 0x1c],
99    lpspi1_trig: Lpspi1Trig,
100    _reserved69: [u8; 0x1c],
101    lpuart0: Lpuart0,
102    _reserved70: [u8; 0x1c],
103    lpuart1: Lpuart1,
104    _reserved71: [u8; 0x1c],
105    lpuart2: Lpuart2,
106    _reserved72: [u8; 0x1c],
107    lpuart3: Lpuart3,
108    _reserved73: [u8; 0x1c],
109    lpuart4: Lpuart4,
110    _reserved74: [u8; 0x1c],
111    lpuart5: Lpuart5,
112    _reserved75: [u8; 0x1c],
113    flexio_trig: [FlexioTrig; 4],
114    _reserved76: [u8; 0x0310],
115    trigfil_prsc: TrigfilPrsc,
116    trigfil_stat0: TrigfilStat0,
117    _reserved78: [u8; 0x08],
118    trigfil: [Trigfil; 12],
119}
120impl RegisterBlock {
121    #[doc = "0x20..0x30 - Capture select register for CTIMER inputs"]
122    #[inline(always)]
123    pub const fn ctimer0cap(&self, n: usize) -> &Ctimer0cap {
124        &self.ctimer0cap[n]
125    }
126    #[doc = "Iterator for array of:"]
127    #[doc = "0x20..0x30 - Capture select register for CTIMER inputs"]
128    #[inline(always)]
129    pub fn ctimer0cap_iter(&self) -> impl Iterator<Item = &Ctimer0cap> {
130        self.ctimer0cap.iter()
131    }
132    #[doc = "0x30 - Trigger register for TIMER0"]
133    #[inline(always)]
134    pub const fn timer0trig(&self) -> &Timer0trig {
135        &self.timer0trig
136    }
137    #[doc = "0x40..0x50 - Capture select register for CTIMER inputs"]
138    #[inline(always)]
139    pub const fn ctimer1cap(&self, n: usize) -> &Ctimer1cap {
140        &self.ctimer1cap[n]
141    }
142    #[doc = "Iterator for array of:"]
143    #[doc = "0x40..0x50 - Capture select register for CTIMER inputs"]
144    #[inline(always)]
145    pub fn ctimer1cap_iter(&self) -> impl Iterator<Item = &Ctimer1cap> {
146        self.ctimer1cap.iter()
147    }
148    #[doc = "0x50 - Trigger register for TIMER1"]
149    #[inline(always)]
150    pub const fn timer1trig(&self) -> &Timer1trig {
151        &self.timer1trig
152    }
153    #[doc = "0x60..0x70 - Capture select register for CTIMER inputs"]
154    #[inline(always)]
155    pub const fn ctimer2cap(&self, n: usize) -> &Ctimer2cap {
156        &self.ctimer2cap[n]
157    }
158    #[doc = "Iterator for array of:"]
159    #[doc = "0x60..0x70 - Capture select register for CTIMER inputs"]
160    #[inline(always)]
161    pub fn ctimer2cap_iter(&self) -> impl Iterator<Item = &Ctimer2cap> {
162        self.ctimer2cap.iter()
163    }
164    #[doc = "0x70 - Trigger register for TIMER2 inputs"]
165    #[inline(always)]
166    pub const fn timer2trig(&self) -> &Timer2trig {
167        &self.timer2trig
168    }
169    #[doc = "0xa0..0xc0 - SmartDMA Trigger Input Connections"]
170    #[inline(always)]
171    pub const fn smart_dma_trig(&self, n: usize) -> &SmartDmaTrig {
172        &self.smart_dma_trig[n]
173    }
174    #[doc = "Iterator for array of:"]
175    #[doc = "0xa0..0xc0 - SmartDMA Trigger Input Connections"]
176    #[inline(always)]
177    pub fn smart_dma_trig_iter(&self) -> impl Iterator<Item = &SmartDmaTrig> {
178        self.smart_dma_trig.iter()
179    }
180    #[doc = "0x180 - Selection for frequency measurement reference clock"]
181    #[inline(always)]
182    pub const fn freqmeas_ref(&self) -> &FreqmeasRef {
183        &self.freqmeas_ref
184    }
185    #[doc = "0x184 - Selection for frequency measurement reference clock"]
186    #[inline(always)]
187    pub const fn freqmeas_tar(&self) -> &FreqmeasTar {
188        &self.freqmeas_tar
189    }
190    #[doc = "0x1a0..0x1b0 - Capture select register for CTIMER inputs"]
191    #[inline(always)]
192    pub const fn ctimer3cap(&self, n: usize) -> &Ctimer3cap {
193        &self.ctimer3cap[n]
194    }
195    #[doc = "Iterator for array of:"]
196    #[doc = "0x1a0..0x1b0 - Capture select register for CTIMER inputs"]
197    #[inline(always)]
198    pub fn ctimer3cap_iter(&self) -> impl Iterator<Item = &Ctimer3cap> {
199        self.ctimer3cap.iter()
200    }
201    #[doc = "0x1b0 - Trigger register for TIMER3"]
202    #[inline(always)]
203    pub const fn timer3trig(&self) -> &Timer3trig {
204        &self.timer3trig
205    }
206    #[doc = "0x1c0..0x1d0 - Capture select register for CTIMER inputs"]
207    #[inline(always)]
208    pub const fn ctimer4cap(&self, n: usize) -> &Ctimer4cap {
209        &self.ctimer4cap[n]
210    }
211    #[doc = "Iterator for array of:"]
212    #[doc = "0x1c0..0x1d0 - Capture select register for CTIMER inputs"]
213    #[inline(always)]
214    pub fn ctimer4cap_iter(&self) -> impl Iterator<Item = &Ctimer4cap> {
215        self.ctimer4cap.iter()
216    }
217    #[doc = "0x1d0 - Trigger register for TIMER4"]
218    #[inline(always)]
219    pub const fn timer4trig(&self) -> &Timer4trig {
220        &self.timer4trig
221    }
222    #[doc = "0x200..0x240 - AOI1 trigger input connections 0"]
223    #[inline(always)]
224    pub const fn aoi1_input(&self, n: usize) -> &Aoi1Input {
225        &self.aoi1_input[n]
226    }
227    #[doc = "Iterator for array of:"]
228    #[doc = "0x200..0x240 - AOI1 trigger input connections 0"]
229    #[inline(always)]
230    pub fn aoi1_input_iter(&self) -> impl Iterator<Item = &Aoi1Input> {
231        self.aoi1_input.iter()
232    }
233    #[doc = "0x260 - CMP0 input connections"]
234    #[inline(always)]
235    pub const fn cmp0_trig(&self) -> &Cmp0Trig {
236        &self.cmp0_trig
237    }
238    #[doc = "0x280..0x290 - ADC Trigger input connections"]
239    #[inline(always)]
240    pub const fn adc0_trig(&self, n: usize) -> &Adc0Trig {
241        &self.adc0_trig[n]
242    }
243    #[doc = "Iterator for array of:"]
244    #[doc = "0x280..0x290 - ADC Trigger input connections"]
245    #[inline(always)]
246    pub fn adc0_trig_iter(&self) -> impl Iterator<Item = &Adc0Trig> {
247        self.adc0_trig.iter()
248    }
249    #[doc = "0x2a0..0x2b0 - ADC Trigger input connections"]
250    #[inline(always)]
251    pub const fn adc2_trig(&self, n: usize) -> &Adc2Trig {
252        &self.adc2_trig[n]
253    }
254    #[doc = "Iterator for array of:"]
255    #[doc = "0x2a0..0x2b0 - ADC Trigger input connections"]
256    #[inline(always)]
257    pub fn adc2_trig_iter(&self) -> impl Iterator<Item = &Adc2Trig> {
258        self.adc2_trig.iter()
259    }
260    #[doc = "0x2c0..0x2d0 - ADC Trigger input connections"]
261    #[inline(always)]
262    pub const fn adc1_trig(&self, n: usize) -> &Adc1Trig {
263        &self.adc1_trig[n]
264    }
265    #[doc = "Iterator for array of:"]
266    #[doc = "0x2c0..0x2d0 - ADC Trigger input connections"]
267    #[inline(always)]
268    pub fn adc1_trig_iter(&self) -> impl Iterator<Item = &Adc1Trig> {
269        self.adc1_trig.iter()
270    }
271    #[doc = "0x2e0..0x2f0 - ADC Trigger input connections"]
272    #[inline(always)]
273    pub const fn adc3_trig(&self, n: usize) -> &Adc3Trig {
274        &self.adc3_trig[n]
275    }
276    #[doc = "Iterator for array of:"]
277    #[doc = "0x2e0..0x2f0 - ADC Trigger input connections"]
278    #[inline(always)]
279    pub fn adc3_trig_iter(&self) -> impl Iterator<Item = &Adc3Trig> {
280        self.adc3_trig.iter()
281    }
282    #[doc = "0x300 - DAC0 Trigger input connections."]
283    #[inline(always)]
284    pub const fn dac0_trig(&self) -> &Dac0Trig {
285        &self.dac0_trig
286    }
287    #[doc = "0x360 - QDC0 Trigger Input Connections"]
288    #[inline(always)]
289    pub const fn qdc0_trig(&self) -> &Qdc0Trig {
290        &self.qdc0_trig
291    }
292    #[doc = "0x364 - QDC0 Trigger Input Connections"]
293    #[inline(always)]
294    pub const fn qdc0_home(&self) -> &Qdc0Home {
295        &self.qdc0_home
296    }
297    #[doc = "0x368 - QDC0 Trigger Input Connections"]
298    #[inline(always)]
299    pub const fn qdc0_index(&self) -> &Qdc0Index {
300        &self.qdc0_index
301    }
302    #[doc = "0x36c - QDC0 Trigger Input Connections"]
303    #[inline(always)]
304    pub const fn qdc0_phaseb(&self) -> &Qdc0Phaseb {
305        &self.qdc0_phaseb
306    }
307    #[doc = "0x370 - QDC0 Trigger Input Connections"]
308    #[inline(always)]
309    pub const fn qdc0_phasea(&self) -> &Qdc0Phasea {
310        &self.qdc0_phasea
311    }
312    #[doc = "0x374 - QDC0 Trigger Input Connections"]
313    #[inline(always)]
314    pub const fn qdc0_icap1(&self) -> &Qdc0Icap1 {
315        &self.qdc0_icap1
316    }
317    #[doc = "0x378 - QDC0 Trigger Input Connections"]
318    #[inline(always)]
319    pub const fn qdc0_icap2(&self) -> &Qdc0Icap2 {
320        &self.qdc0_icap2
321    }
322    #[doc = "0x37c - QDC0 Trigger Input Connections"]
323    #[inline(always)]
324    pub const fn qdc0_icap3(&self) -> &Qdc0Icap3 {
325        &self.qdc0_icap3
326    }
327    #[doc = "0x380 - QDC1 Trigger Input Connections"]
328    #[inline(always)]
329    pub const fn qdc1_trig(&self) -> &Qdc1Trig {
330        &self.qdc1_trig
331    }
332    #[doc = "0x384 - QDC1 Trigger Input Connections"]
333    #[inline(always)]
334    pub const fn qdc1_home(&self) -> &Qdc1Home {
335        &self.qdc1_home
336    }
337    #[doc = "0x388 - QDC1 Trigger Input Connections"]
338    #[inline(always)]
339    pub const fn qdc1_index(&self) -> &Qdc1Index {
340        &self.qdc1_index
341    }
342    #[doc = "0x38c - QDC1 Trigger Input Connections"]
343    #[inline(always)]
344    pub const fn qdc1_phaseb(&self) -> &Qdc1Phaseb {
345        &self.qdc1_phaseb
346    }
347    #[doc = "0x390 - QDC1 Trigger Input Connections"]
348    #[inline(always)]
349    pub const fn qdc1_phasea(&self) -> &Qdc1Phasea {
350        &self.qdc1_phasea
351    }
352    #[doc = "0x394 - QDC1 Trigger Input Connections"]
353    #[inline(always)]
354    pub const fn qdc1_icap1(&self) -> &Qdc1Icap1 {
355        &self.qdc1_icap1
356    }
357    #[doc = "0x398 - QDC1 Trigger Input Connections"]
358    #[inline(always)]
359    pub const fn qdc1_icap2(&self) -> &Qdc1Icap2 {
360        &self.qdc1_icap2
361    }
362    #[doc = "0x39c - QDC1 Trigger Input Connections"]
363    #[inline(always)]
364    pub const fn qdc1_icap3(&self) -> &Qdc1Icap3 {
365        &self.qdc1_icap3
366    }
367    #[doc = "0x3a0 - PWM0 input trigger connections"]
368    #[inline(always)]
369    pub const fn flex_pwm0_sm0_exta0(&self) -> &FlexPwm0Sm0Exta0 {
370        &self.flex_pwm0_sm0_exta0
371    }
372    #[doc = "0x3a4 - PWM0 input trigger connections"]
373    #[inline(always)]
374    pub const fn flex_pwm0_sm0_extsync(&self) -> &FlexPwm0Sm0Extsync {
375        &self.flex_pwm0_sm0_extsync
376    }
377    #[doc = "0x3a8 - PWM0 input trigger connections"]
378    #[inline(always)]
379    pub const fn flex_pwm0_sm1_exta(&self) -> &FlexPwm0Sm1Exta {
380        &self.flex_pwm0_sm1_exta
381    }
382    #[doc = "0x3ac - PWM0 input trigger connections"]
383    #[inline(always)]
384    pub const fn flex_pwm0_sm1_extsync(&self) -> &FlexPwm0Sm1Extsync {
385        &self.flex_pwm0_sm1_extsync
386    }
387    #[doc = "0x3b0 - PWM0 input trigger connections"]
388    #[inline(always)]
389    pub const fn flex_pwm0_sm2_exta(&self) -> &FlexPwm0Sm2Exta {
390        &self.flex_pwm0_sm2_exta
391    }
392    #[doc = "0x3b4 - PWM0 input trigger connections"]
393    #[inline(always)]
394    pub const fn flex_pwm0_sm2_extsync(&self) -> &FlexPwm0Sm2Extsync {
395        &self.flex_pwm0_sm2_extsync
396    }
397    #[doc = "0x3b8 - PWM0 input trigger connections"]
398    #[inline(always)]
399    pub const fn flex_pwm0_sm3_exta0(&self) -> &FlexPwm0Sm3Exta0 {
400        &self.flex_pwm0_sm3_exta0
401    }
402    #[doc = "0x3bc - PWM0 input trigger connections"]
403    #[inline(always)]
404    pub const fn flex_pwm0_sm3_extsync(&self) -> &FlexPwm0Sm3Extsync {
405        &self.flex_pwm0_sm3_extsync
406    }
407    #[doc = "0x3c0..0x3d0 - PWM0 Fault Input Trigger Connections"]
408    #[inline(always)]
409    pub const fn flex_pwm0_fault(&self, n: usize) -> &FlexPwm0Fault {
410        &self.flex_pwm0_fault[n]
411    }
412    #[doc = "Iterator for array of:"]
413    #[doc = "0x3c0..0x3d0 - PWM0 Fault Input Trigger Connections"]
414    #[inline(always)]
415    pub fn flex_pwm0_fault_iter(&self) -> impl Iterator<Item = &FlexPwm0Fault> {
416        self.flex_pwm0_fault.iter()
417    }
418    #[doc = "0x3d0 - PWM0 input trigger connections"]
419    #[inline(always)]
420    pub const fn flex_pwm0_force(&self) -> &FlexPwm0Force {
421        &self.flex_pwm0_force
422    }
423    #[doc = "0x3e0 - PWM1 input trigger connections"]
424    #[inline(always)]
425    pub const fn flex_pwm1_sm0_exta0(&self) -> &FlexPwm1Sm0Exta0 {
426        &self.flex_pwm1_sm0_exta0
427    }
428    #[doc = "0x3e4 - PWM1 input trigger connections"]
429    #[inline(always)]
430    pub const fn flex_pwm1_sm0_extsync(&self) -> &FlexPwm1Sm0Extsync {
431        &self.flex_pwm1_sm0_extsync
432    }
433    #[doc = "0x3e8 - PWM1 input trigger connections"]
434    #[inline(always)]
435    pub const fn flex_pwm1_sm1_exta(&self) -> &FlexPwm1Sm1Exta {
436        &self.flex_pwm1_sm1_exta
437    }
438    #[doc = "0x3ec - PWM1 input trigger connections"]
439    #[inline(always)]
440    pub const fn flex_pwm1_sm1_extsync(&self) -> &FlexPwm1Sm1Extsync {
441        &self.flex_pwm1_sm1_extsync
442    }
443    #[doc = "0x3f0 - PWM1 input trigger connections"]
444    #[inline(always)]
445    pub const fn flex_pwm1_sm2_exta(&self) -> &FlexPwm1Sm2Exta {
446        &self.flex_pwm1_sm2_exta
447    }
448    #[doc = "0x3f4 - PWM1 input trigger connections"]
449    #[inline(always)]
450    pub const fn flex_pwm1_sm2_extsync(&self) -> &FlexPwm1Sm2Extsync {
451        &self.flex_pwm1_sm2_extsync
452    }
453    #[doc = "0x3f8 - PWM1 input trigger connections"]
454    #[inline(always)]
455    pub const fn flex_pwm1_sm3_exta0(&self) -> &FlexPwm1Sm3Exta0 {
456        &self.flex_pwm1_sm3_exta0
457    }
458    #[doc = "0x3fc - PWM1 input trigger connections"]
459    #[inline(always)]
460    pub const fn flex_pwm1_sm3_extsync(&self) -> &FlexPwm1Sm3Extsync {
461        &self.flex_pwm1_sm3_extsync
462    }
463    #[doc = "0x400..0x410 - PWM1 Fault Input Trigger Connections"]
464    #[inline(always)]
465    pub const fn flex_pwm1_fault(&self, n: usize) -> &FlexPwm1Fault {
466        &self.flex_pwm1_fault[n]
467    }
468    #[doc = "Iterator for array of:"]
469    #[doc = "0x400..0x410 - PWM1 Fault Input Trigger Connections"]
470    #[inline(always)]
471    pub fn flex_pwm1_fault_iter(&self) -> impl Iterator<Item = &FlexPwm1Fault> {
472        self.flex_pwm1_fault.iter()
473    }
474    #[doc = "0x410 - PWM1 input trigger connections"]
475    #[inline(always)]
476    pub const fn flex_pwm1_force(&self) -> &FlexPwm1Force {
477        &self.flex_pwm1_force
478    }
479    #[doc = "0x420 - PWM0 external clock trigger"]
480    #[inline(always)]
481    pub const fn pwm0_ext_clk(&self) -> &Pwm0ExtClk {
482        &self.pwm0_ext_clk
483    }
484    #[doc = "0x424 - PWM1 external clock trigger"]
485    #[inline(always)]
486    pub const fn pwm1_ext_clk(&self) -> &Pwm1ExtClk {
487        &self.pwm1_ext_clk
488    }
489    #[doc = "0x440..0x480 - AOI0 trigger input connections 0"]
490    #[inline(always)]
491    pub const fn aoi0_input(&self, n: usize) -> &Aoi0Input {
492        &self.aoi0_input[n]
493    }
494    #[doc = "Iterator for array of:"]
495    #[doc = "0x440..0x480 - AOI0 trigger input connections 0"]
496    #[inline(always)]
497    pub fn aoi0_input_iter(&self) -> impl Iterator<Item = &Aoi0Input> {
498        self.aoi0_input.iter()
499    }
500    #[doc = "0x480 - USB-FS trigger input connections"]
501    #[inline(always)]
502    pub const fn usbfs_trig(&self) -> &UsbfsTrig {
503        &self.usbfs_trig
504    }
505    #[doc = "0x4c0..0x4e0 - EXT trigger connections"]
506    #[inline(always)]
507    pub const fn ext_trig(&self, n: usize) -> &ExtTrig {
508        &self.ext_trig[n]
509    }
510    #[doc = "Iterator for array of:"]
511    #[doc = "0x4c0..0x4e0 - EXT trigger connections"]
512    #[inline(always)]
513    pub fn ext_trig_iter(&self) -> impl Iterator<Item = &ExtTrig> {
514        self.ext_trig.iter()
515    }
516    #[doc = "0x4e0 - CMP1 input connections"]
517    #[inline(always)]
518    pub const fn cmp1_trig(&self) -> &Cmp1Trig {
519        &self.cmp1_trig
520    }
521    #[doc = "0x500 - CMP2 input connections"]
522    #[inline(always)]
523    pub const fn cmp2_trig(&self) -> &Cmp2Trig {
524        &self.cmp2_trig
525    }
526    #[doc = "0x540 - LPI2C2 trigger input connections"]
527    #[inline(always)]
528    pub const fn lpi2c2_trig(&self) -> &Lpi2c2Trig {
529        &self.lpi2c2_trig
530    }
531    #[doc = "0x560 - LPI2C3 trigger input connections"]
532    #[inline(always)]
533    pub const fn lpi2c3_trig(&self) -> &Lpi2c3Trig {
534        &self.lpi2c3_trig
535    }
536    #[doc = "0x5a0 - LPI2C0 trigger input connections"]
537    #[inline(always)]
538    pub const fn lpi2c0_trig(&self) -> &Lpi2c0Trig {
539        &self.lpi2c0_trig
540    }
541    #[doc = "0x5c0 - LPI2C1 trigger input connections"]
542    #[inline(always)]
543    pub const fn lpi2c1_trig(&self) -> &Lpi2c1Trig {
544        &self.lpi2c1_trig
545    }
546    #[doc = "0x5e0 - LPSPI0 trigger input connections"]
547    #[inline(always)]
548    pub const fn lpspi0_trig(&self) -> &Lpspi0Trig {
549        &self.lpspi0_trig
550    }
551    #[doc = "0x600 - LPSPI1 trigger input connections"]
552    #[inline(always)]
553    pub const fn lpspi1_trig(&self) -> &Lpspi1Trig {
554        &self.lpspi1_trig
555    }
556    #[doc = "0x620 - LPUART0 trigger input connections"]
557    #[inline(always)]
558    pub const fn lpuart0(&self) -> &Lpuart0 {
559        &self.lpuart0
560    }
561    #[doc = "0x640 - LPUART1 trigger input connections"]
562    #[inline(always)]
563    pub const fn lpuart1(&self) -> &Lpuart1 {
564        &self.lpuart1
565    }
566    #[doc = "0x660 - LPUART2 trigger input connections"]
567    #[inline(always)]
568    pub const fn lpuart2(&self) -> &Lpuart2 {
569        &self.lpuart2
570    }
571    #[doc = "0x680 - LPUART3 trigger input connections"]
572    #[inline(always)]
573    pub const fn lpuart3(&self) -> &Lpuart3 {
574        &self.lpuart3
575    }
576    #[doc = "0x6a0 - LPUART4 trigger input connections"]
577    #[inline(always)]
578    pub const fn lpuart4(&self) -> &Lpuart4 {
579        &self.lpuart4
580    }
581    #[doc = "0x6c0 - LPUART5 trigger input connections"]
582    #[inline(always)]
583    pub const fn lpuart5(&self) -> &Lpuart5 {
584        &self.lpuart5
585    }
586    #[doc = "0x6e0..0x6f0 - FlexIO Trigger Input Connections"]
587    #[inline(always)]
588    pub const fn flexio_trig(&self, n: usize) -> &FlexioTrig {
589        &self.flexio_trig[n]
590    }
591    #[doc = "Iterator for array of:"]
592    #[doc = "0x6e0..0x6f0 - FlexIO Trigger Input Connections"]
593    #[inline(always)]
594    pub fn flexio_trig_iter(&self) -> impl Iterator<Item = &FlexioTrig> {
595        self.flexio_trig.iter()
596    }
597    #[doc = "0xa00 - Trigger filter prescaller"]
598    #[inline(always)]
599    pub const fn trigfil_prsc(&self) -> &TrigfilPrsc {
600        &self.trigfil_prsc
601    }
602    #[doc = "0xa04 - Trigger filter stat"]
603    #[inline(always)]
604    pub const fn trigfil_stat0(&self) -> &TrigfilStat0 {
605        &self.trigfil_stat0
606    }
607    #[doc = "0xa10..0xa40 - TRIGFIL control"]
608    #[inline(always)]
609    pub const fn trigfil(&self, n: usize) -> &Trigfil {
610        &self.trigfil[n]
611    }
612    #[doc = "Iterator for array of:"]
613    #[doc = "0xa10..0xa40 - TRIGFIL control"]
614    #[inline(always)]
615    pub fn trigfil_iter(&self) -> impl Iterator<Item = &Trigfil> {
616        self.trigfil.iter()
617    }
618}
619#[doc = "CTIMER0CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer0cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer0cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer0cap`] module"]
620#[doc(alias = "CTIMER0CAP")]
621pub type Ctimer0cap = crate::Reg<ctimer0cap::Ctimer0capSpec>;
622#[doc = "Capture select register for CTIMER inputs"]
623pub mod ctimer0cap;
624#[doc = "TIMER0TRIG (rw) register accessor: Trigger register for TIMER0\n\nYou can [`read`](crate::Reg::read) this register and get [`timer0trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer0trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer0trig`] module"]
625#[doc(alias = "TIMER0TRIG")]
626pub type Timer0trig = crate::Reg<timer0trig::Timer0trigSpec>;
627#[doc = "Trigger register for TIMER0"]
628pub mod timer0trig;
629#[doc = "CTIMER1CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer1cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer1cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer1cap`] module"]
630#[doc(alias = "CTIMER1CAP")]
631pub type Ctimer1cap = crate::Reg<ctimer1cap::Ctimer1capSpec>;
632#[doc = "Capture select register for CTIMER inputs"]
633pub mod ctimer1cap;
634#[doc = "TIMER1TRIG (rw) register accessor: Trigger register for TIMER1\n\nYou can [`read`](crate::Reg::read) this register and get [`timer1trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer1trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer1trig`] module"]
635#[doc(alias = "TIMER1TRIG")]
636pub type Timer1trig = crate::Reg<timer1trig::Timer1trigSpec>;
637#[doc = "Trigger register for TIMER1"]
638pub mod timer1trig;
639#[doc = "CTIMER2CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer2cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer2cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer2cap`] module"]
640#[doc(alias = "CTIMER2CAP")]
641pub type Ctimer2cap = crate::Reg<ctimer2cap::Ctimer2capSpec>;
642#[doc = "Capture select register for CTIMER inputs"]
643pub mod ctimer2cap;
644#[doc = "TIMER2TRIG (rw) register accessor: Trigger register for TIMER2 inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`timer2trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer2trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer2trig`] module"]
645#[doc(alias = "TIMER2TRIG")]
646pub type Timer2trig = crate::Reg<timer2trig::Timer2trigSpec>;
647#[doc = "Trigger register for TIMER2 inputs"]
648pub mod timer2trig;
649#[doc = "SmartDMA_TRIG (rw) register accessor: SmartDMA Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`smart_dma_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`smart_dma_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smart_dma_trig`] module"]
650#[doc(alias = "SmartDMA_TRIG")]
651pub type SmartDmaTrig = crate::Reg<smart_dma_trig::SmartDmaTrigSpec>;
652#[doc = "SmartDMA Trigger Input Connections"]
653pub mod smart_dma_trig;
654#[doc = "FREQMEAS_REF (rw) register accessor: Selection for frequency measurement reference clock\n\nYou can [`read`](crate::Reg::read) this register and get [`freqmeas_ref::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqmeas_ref::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@freqmeas_ref`] module"]
655#[doc(alias = "FREQMEAS_REF")]
656pub type FreqmeasRef = crate::Reg<freqmeas_ref::FreqmeasRefSpec>;
657#[doc = "Selection for frequency measurement reference clock"]
658pub mod freqmeas_ref;
659#[doc = "FREQMEAS_TAR (rw) register accessor: Selection for frequency measurement reference clock\n\nYou can [`read`](crate::Reg::read) this register and get [`freqmeas_tar::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`freqmeas_tar::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@freqmeas_tar`] module"]
660#[doc(alias = "FREQMEAS_TAR")]
661pub type FreqmeasTar = crate::Reg<freqmeas_tar::FreqmeasTarSpec>;
662#[doc = "Selection for frequency measurement reference clock"]
663pub mod freqmeas_tar;
664#[doc = "CTIMER3CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer3cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer3cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer3cap`] module"]
665#[doc(alias = "CTIMER3CAP")]
666pub type Ctimer3cap = crate::Reg<ctimer3cap::Ctimer3capSpec>;
667#[doc = "Capture select register for CTIMER inputs"]
668pub mod ctimer3cap;
669#[doc = "TIMER3TRIG (rw) register accessor: Trigger register for TIMER3\n\nYou can [`read`](crate::Reg::read) this register and get [`timer3trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer3trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer3trig`] module"]
670#[doc(alias = "TIMER3TRIG")]
671pub type Timer3trig = crate::Reg<timer3trig::Timer3trigSpec>;
672#[doc = "Trigger register for TIMER3"]
673pub mod timer3trig;
674#[doc = "CTIMER4CAP (rw) register accessor: Capture select register for CTIMER inputs\n\nYou can [`read`](crate::Reg::read) this register and get [`ctimer4cap::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctimer4cap::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctimer4cap`] module"]
675#[doc(alias = "CTIMER4CAP")]
676pub type Ctimer4cap = crate::Reg<ctimer4cap::Ctimer4capSpec>;
677#[doc = "Capture select register for CTIMER inputs"]
678pub mod ctimer4cap;
679#[doc = "TIMER4TRIG (rw) register accessor: Trigger register for TIMER4\n\nYou can [`read`](crate::Reg::read) this register and get [`timer4trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timer4trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@timer4trig`] module"]
680#[doc(alias = "TIMER4TRIG")]
681pub type Timer4trig = crate::Reg<timer4trig::Timer4trigSpec>;
682#[doc = "Trigger register for TIMER4"]
683pub mod timer4trig;
684#[doc = "AOI1_INPUT (rw) register accessor: AOI1 trigger input connections 0\n\nYou can [`read`](crate::Reg::read) this register and get [`aoi1_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aoi1_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aoi1_input`] module"]
685#[doc(alias = "AOI1_INPUT")]
686pub type Aoi1Input = crate::Reg<aoi1_input::Aoi1InputSpec>;
687#[doc = "AOI1 trigger input connections 0"]
688pub mod aoi1_input;
689#[doc = "CMP0_TRIG (rw) register accessor: CMP0 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp0_trig`] module"]
690#[doc(alias = "CMP0_TRIG")]
691pub type Cmp0Trig = crate::Reg<cmp0_trig::Cmp0TrigSpec>;
692#[doc = "CMP0 input connections"]
693pub mod cmp0_trig;
694#[doc = "ADC0_TRIG (rw) register accessor: ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc0_trig`] module"]
695#[doc(alias = "ADC0_TRIG")]
696pub type Adc0Trig = crate::Reg<adc0_trig::Adc0TrigSpec>;
697#[doc = "ADC Trigger input connections"]
698pub mod adc0_trig;
699#[doc = "ADC2_TRIG (rw) register accessor: ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc2_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc2_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc2_trig`] module"]
700#[doc(alias = "ADC2_TRIG")]
701pub type Adc2Trig = crate::Reg<adc2_trig::Adc2TrigSpec>;
702#[doc = "ADC Trigger input connections"]
703pub mod adc2_trig;
704#[doc = "ADC1_TRIG (rw) register accessor: ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc1_trig`] module"]
705#[doc(alias = "ADC1_TRIG")]
706pub type Adc1Trig = crate::Reg<adc1_trig::Adc1TrigSpec>;
707#[doc = "ADC Trigger input connections"]
708pub mod adc1_trig;
709#[doc = "ADC3_TRIG (rw) register accessor: ADC Trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`adc3_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`adc3_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@adc3_trig`] module"]
710#[doc(alias = "ADC3_TRIG")]
711pub type Adc3Trig = crate::Reg<adc3_trig::Adc3TrigSpec>;
712#[doc = "ADC Trigger input connections"]
713pub mod adc3_trig;
714#[doc = "DAC0_TRIG (rw) register accessor: DAC0 Trigger input connections.\n\nYou can [`read`](crate::Reg::read) this register and get [`dac0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`dac0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@dac0_trig`] module"]
715#[doc(alias = "DAC0_TRIG")]
716pub type Dac0Trig = crate::Reg<dac0_trig::Dac0TrigSpec>;
717#[doc = "DAC0 Trigger input connections."]
718pub mod dac0_trig;
719#[doc = "QDC0_TRIG (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_trig`] module"]
720#[doc(alias = "QDC0_TRIG")]
721pub type Qdc0Trig = crate::Reg<qdc0_trig::Qdc0TrigSpec>;
722#[doc = "QDC0 Trigger Input Connections"]
723pub mod qdc0_trig;
724#[doc = "QDC0_HOME (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_home::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_home::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_home`] module"]
725#[doc(alias = "QDC0_HOME")]
726pub type Qdc0Home = crate::Reg<qdc0_home::Qdc0HomeSpec>;
727#[doc = "QDC0 Trigger Input Connections"]
728pub mod qdc0_home;
729#[doc = "QDC0_INDEX (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_index::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_index::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_index`] module"]
730#[doc(alias = "QDC0_INDEX")]
731pub type Qdc0Index = crate::Reg<qdc0_index::Qdc0IndexSpec>;
732#[doc = "QDC0 Trigger Input Connections"]
733pub mod qdc0_index;
734#[doc = "QDC0_PHASEB (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_phaseb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_phaseb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_phaseb`] module"]
735#[doc(alias = "QDC0_PHASEB")]
736pub type Qdc0Phaseb = crate::Reg<qdc0_phaseb::Qdc0PhasebSpec>;
737#[doc = "QDC0 Trigger Input Connections"]
738pub mod qdc0_phaseb;
739#[doc = "QDC0_PHASEA (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_phasea::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_phasea::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_phasea`] module"]
740#[doc(alias = "QDC0_PHASEA")]
741pub type Qdc0Phasea = crate::Reg<qdc0_phasea::Qdc0PhaseaSpec>;
742#[doc = "QDC0 Trigger Input Connections"]
743pub mod qdc0_phasea;
744#[doc = "QDC0_ICAP1 (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_icap1`] module"]
745#[doc(alias = "QDC0_ICAP1")]
746pub type Qdc0Icap1 = crate::Reg<qdc0_icap1::Qdc0Icap1Spec>;
747#[doc = "QDC0 Trigger Input Connections"]
748pub mod qdc0_icap1;
749#[doc = "QDC0_ICAP2 (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_icap2`] module"]
750#[doc(alias = "QDC0_ICAP2")]
751pub type Qdc0Icap2 = crate::Reg<qdc0_icap2::Qdc0Icap2Spec>;
752#[doc = "QDC0 Trigger Input Connections"]
753pub mod qdc0_icap2;
754#[doc = "QDC0_ICAP3 (rw) register accessor: QDC0 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc0_icap3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc0_icap3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc0_icap3`] module"]
755#[doc(alias = "QDC0_ICAP3")]
756pub type Qdc0Icap3 = crate::Reg<qdc0_icap3::Qdc0Icap3Spec>;
757#[doc = "QDC0 Trigger Input Connections"]
758pub mod qdc0_icap3;
759#[doc = "QDC1_TRIG (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_trig`] module"]
760#[doc(alias = "QDC1_TRIG")]
761pub type Qdc1Trig = crate::Reg<qdc1_trig::Qdc1TrigSpec>;
762#[doc = "QDC1 Trigger Input Connections"]
763pub mod qdc1_trig;
764#[doc = "QDC1_HOME (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_home::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_home::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_home`] module"]
765#[doc(alias = "QDC1_HOME")]
766pub type Qdc1Home = crate::Reg<qdc1_home::Qdc1HomeSpec>;
767#[doc = "QDC1 Trigger Input Connections"]
768pub mod qdc1_home;
769#[doc = "QDC1_INDEX (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_index::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_index::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_index`] module"]
770#[doc(alias = "QDC1_INDEX")]
771pub type Qdc1Index = crate::Reg<qdc1_index::Qdc1IndexSpec>;
772#[doc = "QDC1 Trigger Input Connections"]
773pub mod qdc1_index;
774#[doc = "QDC1_PHASEB (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_phaseb::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_phaseb::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_phaseb`] module"]
775#[doc(alias = "QDC1_PHASEB")]
776pub type Qdc1Phaseb = crate::Reg<qdc1_phaseb::Qdc1PhasebSpec>;
777#[doc = "QDC1 Trigger Input Connections"]
778pub mod qdc1_phaseb;
779#[doc = "QDC1_PHASEA (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_phasea::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_phasea::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_phasea`] module"]
780#[doc(alias = "QDC1_PHASEA")]
781pub type Qdc1Phasea = crate::Reg<qdc1_phasea::Qdc1PhaseaSpec>;
782#[doc = "QDC1 Trigger Input Connections"]
783pub mod qdc1_phasea;
784#[doc = "QDC1_ICAP1 (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_icap1`] module"]
785#[doc(alias = "QDC1_ICAP1")]
786pub type Qdc1Icap1 = crate::Reg<qdc1_icap1::Qdc1Icap1Spec>;
787#[doc = "QDC1 Trigger Input Connections"]
788pub mod qdc1_icap1;
789#[doc = "QDC1_ICAP2 (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_icap2`] module"]
790#[doc(alias = "QDC1_ICAP2")]
791pub type Qdc1Icap2 = crate::Reg<qdc1_icap2::Qdc1Icap2Spec>;
792#[doc = "QDC1 Trigger Input Connections"]
793pub mod qdc1_icap2;
794#[doc = "QDC1_ICAP3 (rw) register accessor: QDC1 Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`qdc1_icap3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`qdc1_icap3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@qdc1_icap3`] module"]
795#[doc(alias = "QDC1_ICAP3")]
796pub type Qdc1Icap3 = crate::Reg<qdc1_icap3::Qdc1Icap3Spec>;
797#[doc = "QDC1 Trigger Input Connections"]
798pub mod qdc1_icap3;
799#[doc = "FlexPWM0_SM0_EXTA0 (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm0_exta0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm0_exta0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm0_exta0`] module"]
800#[doc(alias = "FlexPWM0_SM0_EXTA0")]
801pub type FlexPwm0Sm0Exta0 = crate::Reg<flex_pwm0_sm0_exta0::FlexPwm0Sm0Exta0Spec>;
802#[doc = "PWM0 input trigger connections"]
803pub mod flex_pwm0_sm0_exta0;
804#[doc = "FlexPWM0_SM0_EXTSYNC (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm0_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm0_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm0_extsync`] module"]
805#[doc(alias = "FlexPWM0_SM0_EXTSYNC")]
806pub type FlexPwm0Sm0Extsync = crate::Reg<flex_pwm0_sm0_extsync::FlexPwm0Sm0ExtsyncSpec>;
807#[doc = "PWM0 input trigger connections"]
808pub mod flex_pwm0_sm0_extsync;
809#[doc = "FlexPWM0_SM1_EXTA (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm1_exta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm1_exta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm1_exta`] module"]
810#[doc(alias = "FlexPWM0_SM1_EXTA")]
811pub type FlexPwm0Sm1Exta = crate::Reg<flex_pwm0_sm1_exta::FlexPwm0Sm1ExtaSpec>;
812#[doc = "PWM0 input trigger connections"]
813pub mod flex_pwm0_sm1_exta;
814#[doc = "FlexPWM0_SM1_EXTSYNC (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm1_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm1_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm1_extsync`] module"]
815#[doc(alias = "FlexPWM0_SM1_EXTSYNC")]
816pub type FlexPwm0Sm1Extsync = crate::Reg<flex_pwm0_sm1_extsync::FlexPwm0Sm1ExtsyncSpec>;
817#[doc = "PWM0 input trigger connections"]
818pub mod flex_pwm0_sm1_extsync;
819#[doc = "FlexPWM0_SM2_EXTA (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm2_exta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm2_exta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm2_exta`] module"]
820#[doc(alias = "FlexPWM0_SM2_EXTA")]
821pub type FlexPwm0Sm2Exta = crate::Reg<flex_pwm0_sm2_exta::FlexPwm0Sm2ExtaSpec>;
822#[doc = "PWM0 input trigger connections"]
823pub mod flex_pwm0_sm2_exta;
824#[doc = "FlexPWM0_SM2_EXTSYNC (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm2_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm2_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm2_extsync`] module"]
825#[doc(alias = "FlexPWM0_SM2_EXTSYNC")]
826pub type FlexPwm0Sm2Extsync = crate::Reg<flex_pwm0_sm2_extsync::FlexPwm0Sm2ExtsyncSpec>;
827#[doc = "PWM0 input trigger connections"]
828pub mod flex_pwm0_sm2_extsync;
829#[doc = "FlexPWM0_SM3_EXTA0 (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm3_exta0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm3_exta0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm3_exta0`] module"]
830#[doc(alias = "FlexPWM0_SM3_EXTA0")]
831pub type FlexPwm0Sm3Exta0 = crate::Reg<flex_pwm0_sm3_exta0::FlexPwm0Sm3Exta0Spec>;
832#[doc = "PWM0 input trigger connections"]
833pub mod flex_pwm0_sm3_exta0;
834#[doc = "FlexPWM0_SM3_EXTSYNC (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_sm3_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_sm3_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_sm3_extsync`] module"]
835#[doc(alias = "FlexPWM0_SM3_EXTSYNC")]
836pub type FlexPwm0Sm3Extsync = crate::Reg<flex_pwm0_sm3_extsync::FlexPwm0Sm3ExtsyncSpec>;
837#[doc = "PWM0 input trigger connections"]
838pub mod flex_pwm0_sm3_extsync;
839#[doc = "FlexPWM0_FAULT (rw) register accessor: PWM0 Fault Input Trigger Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_fault::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_fault::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_fault`] module"]
840#[doc(alias = "FlexPWM0_FAULT")]
841pub type FlexPwm0Fault = crate::Reg<flex_pwm0_fault::FlexPwm0FaultSpec>;
842#[doc = "PWM0 Fault Input Trigger Connections"]
843pub mod flex_pwm0_fault;
844#[doc = "FlexPWM0_FORCE (rw) register accessor: PWM0 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm0_force::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm0_force::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm0_force`] module"]
845#[doc(alias = "FlexPWM0_FORCE")]
846pub type FlexPwm0Force = crate::Reg<flex_pwm0_force::FlexPwm0ForceSpec>;
847#[doc = "PWM0 input trigger connections"]
848pub mod flex_pwm0_force;
849#[doc = "FlexPWM1_SM0_EXTA0 (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm0_exta0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm0_exta0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm0_exta0`] module"]
850#[doc(alias = "FlexPWM1_SM0_EXTA0")]
851pub type FlexPwm1Sm0Exta0 = crate::Reg<flex_pwm1_sm0_exta0::FlexPwm1Sm0Exta0Spec>;
852#[doc = "PWM1 input trigger connections"]
853pub mod flex_pwm1_sm0_exta0;
854#[doc = "FlexPWM1_SM0_EXTSYNC (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm0_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm0_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm0_extsync`] module"]
855#[doc(alias = "FlexPWM1_SM0_EXTSYNC")]
856pub type FlexPwm1Sm0Extsync = crate::Reg<flex_pwm1_sm0_extsync::FlexPwm1Sm0ExtsyncSpec>;
857#[doc = "PWM1 input trigger connections"]
858pub mod flex_pwm1_sm0_extsync;
859#[doc = "FlexPWM1_SM1_EXTA (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm1_exta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm1_exta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm1_exta`] module"]
860#[doc(alias = "FlexPWM1_SM1_EXTA")]
861pub type FlexPwm1Sm1Exta = crate::Reg<flex_pwm1_sm1_exta::FlexPwm1Sm1ExtaSpec>;
862#[doc = "PWM1 input trigger connections"]
863pub mod flex_pwm1_sm1_exta;
864#[doc = "FlexPWM1_SM1_EXTSYNC (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm1_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm1_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm1_extsync`] module"]
865#[doc(alias = "FlexPWM1_SM1_EXTSYNC")]
866pub type FlexPwm1Sm1Extsync = crate::Reg<flex_pwm1_sm1_extsync::FlexPwm1Sm1ExtsyncSpec>;
867#[doc = "PWM1 input trigger connections"]
868pub mod flex_pwm1_sm1_extsync;
869#[doc = "FlexPWM1_SM2_EXTA (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm2_exta::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm2_exta::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm2_exta`] module"]
870#[doc(alias = "FlexPWM1_SM2_EXTA")]
871pub type FlexPwm1Sm2Exta = crate::Reg<flex_pwm1_sm2_exta::FlexPwm1Sm2ExtaSpec>;
872#[doc = "PWM1 input trigger connections"]
873pub mod flex_pwm1_sm2_exta;
874#[doc = "FlexPWM1_SM2_EXTSYNC (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm2_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm2_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm2_extsync`] module"]
875#[doc(alias = "FlexPWM1_SM2_EXTSYNC")]
876pub type FlexPwm1Sm2Extsync = crate::Reg<flex_pwm1_sm2_extsync::FlexPwm1Sm2ExtsyncSpec>;
877#[doc = "PWM1 input trigger connections"]
878pub mod flex_pwm1_sm2_extsync;
879#[doc = "FlexPWM1_SM3_EXTA0 (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm3_exta0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm3_exta0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm3_exta0`] module"]
880#[doc(alias = "FlexPWM1_SM3_EXTA0")]
881pub type FlexPwm1Sm3Exta0 = crate::Reg<flex_pwm1_sm3_exta0::FlexPwm1Sm3Exta0Spec>;
882#[doc = "PWM1 input trigger connections"]
883pub mod flex_pwm1_sm3_exta0;
884#[doc = "FlexPWM1_SM3_EXTSYNC (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_sm3_extsync::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_sm3_extsync::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_sm3_extsync`] module"]
885#[doc(alias = "FlexPWM1_SM3_EXTSYNC")]
886pub type FlexPwm1Sm3Extsync = crate::Reg<flex_pwm1_sm3_extsync::FlexPwm1Sm3ExtsyncSpec>;
887#[doc = "PWM1 input trigger connections"]
888pub mod flex_pwm1_sm3_extsync;
889#[doc = "FlexPWM1_FAULT (rw) register accessor: PWM1 Fault Input Trigger Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_fault::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_fault::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_fault`] module"]
890#[doc(alias = "FlexPWM1_FAULT")]
891pub type FlexPwm1Fault = crate::Reg<flex_pwm1_fault::FlexPwm1FaultSpec>;
892#[doc = "PWM1 Fault Input Trigger Connections"]
893pub mod flex_pwm1_fault;
894#[doc = "FlexPWM1_FORCE (rw) register accessor: PWM1 input trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flex_pwm1_force::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flex_pwm1_force::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flex_pwm1_force`] module"]
895#[doc(alias = "FlexPWM1_FORCE")]
896pub type FlexPwm1Force = crate::Reg<flex_pwm1_force::FlexPwm1ForceSpec>;
897#[doc = "PWM1 input trigger connections"]
898pub mod flex_pwm1_force;
899#[doc = "PWM0_EXT_CLK (rw) register accessor: PWM0 external clock trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm0_ext_clk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm0_ext_clk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm0_ext_clk`] module"]
900#[doc(alias = "PWM0_EXT_CLK")]
901pub type Pwm0ExtClk = crate::Reg<pwm0_ext_clk::Pwm0ExtClkSpec>;
902#[doc = "PWM0 external clock trigger"]
903pub mod pwm0_ext_clk;
904#[doc = "PWM1_EXT_CLK (rw) register accessor: PWM1 external clock trigger\n\nYou can [`read`](crate::Reg::read) this register and get [`pwm1_ext_clk::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwm1_ext_clk::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwm1_ext_clk`] module"]
905#[doc(alias = "PWM1_EXT_CLK")]
906pub type Pwm1ExtClk = crate::Reg<pwm1_ext_clk::Pwm1ExtClkSpec>;
907#[doc = "PWM1 external clock trigger"]
908pub mod pwm1_ext_clk;
909#[doc = "AOI0_INPUT (rw) register accessor: AOI0 trigger input connections 0\n\nYou can [`read`](crate::Reg::read) this register and get [`aoi0_input::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`aoi0_input::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@aoi0_input`] module"]
910#[doc(alias = "AOI0_INPUT")]
911pub type Aoi0Input = crate::Reg<aoi0_input::Aoi0InputSpec>;
912#[doc = "AOI0 trigger input connections 0"]
913pub mod aoi0_input;
914#[doc = "USBFS_TRIG (rw) register accessor: USB-FS trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`usbfs_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`usbfs_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@usbfs_trig`] module"]
915#[doc(alias = "USBFS_TRIG")]
916pub type UsbfsTrig = crate::Reg<usbfs_trig::UsbfsTrigSpec>;
917#[doc = "USB-FS trigger input connections"]
918pub mod usbfs_trig;
919#[doc = "EXT_TRIG (rw) register accessor: EXT trigger connections\n\nYou can [`read`](crate::Reg::read) this register and get [`ext_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ext_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ext_trig`] module"]
920#[doc(alias = "EXT_TRIG")]
921pub type ExtTrig = crate::Reg<ext_trig::ExtTrigSpec>;
922#[doc = "EXT trigger connections"]
923pub mod ext_trig;
924#[doc = "CMP1_TRIG (rw) register accessor: CMP1 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp1_trig`] module"]
925#[doc(alias = "CMP1_TRIG")]
926pub type Cmp1Trig = crate::Reg<cmp1_trig::Cmp1TrigSpec>;
927#[doc = "CMP1 input connections"]
928pub mod cmp1_trig;
929#[doc = "CMP2_TRIG (rw) register accessor: CMP2 input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`cmp2_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cmp2_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cmp2_trig`] module"]
930#[doc(alias = "CMP2_TRIG")]
931pub type Cmp2Trig = crate::Reg<cmp2_trig::Cmp2TrigSpec>;
932#[doc = "CMP2 input connections"]
933pub mod cmp2_trig;
934#[doc = "LPI2C2_TRIG (rw) register accessor: LPI2C2 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c2_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c2_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi2c2_trig`] module"]
935#[doc(alias = "LPI2C2_TRIG")]
936pub type Lpi2c2Trig = crate::Reg<lpi2c2_trig::Lpi2c2TrigSpec>;
937#[doc = "LPI2C2 trigger input connections"]
938pub mod lpi2c2_trig;
939#[doc = "LPI2C3_TRIG (rw) register accessor: LPI2C3 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c3_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c3_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi2c3_trig`] module"]
940#[doc(alias = "LPI2C3_TRIG")]
941pub type Lpi2c3Trig = crate::Reg<lpi2c3_trig::Lpi2c3TrigSpec>;
942#[doc = "LPI2C3 trigger input connections"]
943pub mod lpi2c3_trig;
944#[doc = "LPI2C0_TRIG (rw) register accessor: LPI2C0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi2c0_trig`] module"]
945#[doc(alias = "LPI2C0_TRIG")]
946pub type Lpi2c0Trig = crate::Reg<lpi2c0_trig::Lpi2c0TrigSpec>;
947#[doc = "LPI2C0 trigger input connections"]
948pub mod lpi2c0_trig;
949#[doc = "LPI2C1_TRIG (rw) register accessor: LPI2C1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpi2c1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpi2c1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpi2c1_trig`] module"]
950#[doc(alias = "LPI2C1_TRIG")]
951pub type Lpi2c1Trig = crate::Reg<lpi2c1_trig::Lpi2c1TrigSpec>;
952#[doc = "LPI2C1 trigger input connections"]
953pub mod lpi2c1_trig;
954#[doc = "LPSPI0_TRIG (rw) register accessor: LPSPI0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpspi0_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpspi0_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpspi0_trig`] module"]
955#[doc(alias = "LPSPI0_TRIG")]
956pub type Lpspi0Trig = crate::Reg<lpspi0_trig::Lpspi0TrigSpec>;
957#[doc = "LPSPI0 trigger input connections"]
958pub mod lpspi0_trig;
959#[doc = "LPSPI1_TRIG (rw) register accessor: LPSPI1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpspi1_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpspi1_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpspi1_trig`] module"]
960#[doc(alias = "LPSPI1_TRIG")]
961pub type Lpspi1Trig = crate::Reg<lpspi1_trig::Lpspi1TrigSpec>;
962#[doc = "LPSPI1 trigger input connections"]
963pub mod lpspi1_trig;
964#[doc = "LPUART0 (rw) register accessor: LPUART0 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart0`] module"]
965#[doc(alias = "LPUART0")]
966pub type Lpuart0 = crate::Reg<lpuart0::Lpuart0Spec>;
967#[doc = "LPUART0 trigger input connections"]
968pub mod lpuart0;
969#[doc = "LPUART1 (rw) register accessor: LPUART1 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart1`] module"]
970#[doc(alias = "LPUART1")]
971pub type Lpuart1 = crate::Reg<lpuart1::Lpuart1Spec>;
972#[doc = "LPUART1 trigger input connections"]
973pub mod lpuart1;
974#[doc = "LPUART2 (rw) register accessor: LPUART2 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart2`] module"]
975#[doc(alias = "LPUART2")]
976pub type Lpuart2 = crate::Reg<lpuart2::Lpuart2Spec>;
977#[doc = "LPUART2 trigger input connections"]
978pub mod lpuart2;
979#[doc = "LPUART3 (rw) register accessor: LPUART3 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart3`] module"]
980#[doc(alias = "LPUART3")]
981pub type Lpuart3 = crate::Reg<lpuart3::Lpuart3Spec>;
982#[doc = "LPUART3 trigger input connections"]
983pub mod lpuart3;
984#[doc = "LPUART4 (rw) register accessor: LPUART4 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart4`] module"]
985#[doc(alias = "LPUART4")]
986pub type Lpuart4 = crate::Reg<lpuart4::Lpuart4Spec>;
987#[doc = "LPUART4 trigger input connections"]
988pub mod lpuart4;
989#[doc = "LPUART5 (rw) register accessor: LPUART5 trigger input connections\n\nYou can [`read`](crate::Reg::read) this register and get [`lpuart5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`lpuart5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@lpuart5`] module"]
990#[doc(alias = "LPUART5")]
991pub type Lpuart5 = crate::Reg<lpuart5::Lpuart5Spec>;
992#[doc = "LPUART5 trigger input connections"]
993pub mod lpuart5;
994#[doc = "FLEXIO_TRIG (rw) register accessor: FlexIO Trigger Input Connections\n\nYou can [`read`](crate::Reg::read) this register and get [`flexio_trig::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flexio_trig::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flexio_trig`] module"]
995#[doc(alias = "FLEXIO_TRIG")]
996pub type FlexioTrig = crate::Reg<flexio_trig::FlexioTrigSpec>;
997#[doc = "FlexIO Trigger Input Connections"]
998pub mod flexio_trig;
999#[doc = "TRIGFIL_PRSC (rw) register accessor: Trigger filter prescaller\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil_prsc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigfil_prsc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigfil_prsc`] module"]
1000#[doc(alias = "TRIGFIL_PRSC")]
1001pub type TrigfilPrsc = crate::Reg<trigfil_prsc::TrigfilPrscSpec>;
1002#[doc = "Trigger filter prescaller"]
1003pub mod trigfil_prsc;
1004#[doc = "TRIGFIL_STAT0 (r) register accessor: Trigger filter stat\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil_stat0::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigfil_stat0`] module"]
1005#[doc(alias = "TRIGFIL_STAT0")]
1006pub type TrigfilStat0 = crate::Reg<trigfil_stat0::TrigfilStat0Spec>;
1007#[doc = "Trigger filter stat"]
1008pub mod trigfil_stat0;
1009#[doc = "TRIGFIL (rw) register accessor: TRIGFIL control\n\nYou can [`read`](crate::Reg::read) this register and get [`trigfil::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`trigfil::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@trigfil`] module"]
1010#[doc(alias = "TRIGFIL")]
1011pub type Trigfil = crate::Reg<trigfil::TrigfilSpec>;
1012#[doc = "TRIGFIL control"]
1013pub mod trigfil;
mcxa_pac/inputmux0.rs

mcxa_pac/
inputmux0.rs
