mcxa_pac/i3c0/
sdynaddr.rs

1#[doc = "Register `SDYNADDR` reader"]
2pub type R = crate::R<SdynaddrSpec>;
3#[doc = "Register `SDYNADDR` writer"]
4pub type W = crate::W<SdynaddrSpec>;
5#[doc = "Dynamic Address Valid\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Davalid {
9    #[doc = "0: DANOTASSIGNED: a dynamic address is not assigned"]
10    Danotassigned = 0,
11    #[doc = "1: DAASSIGNED: a dynamic address is assigned"]
12    Daassigned = 1,
13}
14impl From<Davalid> for bool {
15    #[inline(always)]
16    fn from(variant: Davalid) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `DAVALID` reader - Dynamic Address Valid"]
21pub type DavalidR = crate::BitReader<Davalid>;
22impl DavalidR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Davalid {
26        match self.bits {
27            false => Davalid::Danotassigned,
28            true => Davalid::Daassigned,
29        }
30    }
31    #[doc = "DANOTASSIGNED: a dynamic address is not assigned"]
32    #[inline(always)]
33    pub fn is_danotassigned(&self) -> bool {
34        *self == Davalid::Danotassigned
35    }
36    #[doc = "DAASSIGNED: a dynamic address is assigned"]
37    #[inline(always)]
38    pub fn is_daassigned(&self) -> bool {
39        *self == Davalid::Daassigned
40    }
41}
42#[doc = "Field `DAVALID` writer - Dynamic Address Valid"]
43pub type DavalidW<'a, REG> = crate::BitWriter<'a, REG, Davalid>;
44impl<'a, REG> DavalidW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "DANOTASSIGNED: a dynamic address is not assigned"]
49    #[inline(always)]
50    pub fn danotassigned(self) -> &'a mut crate::W<REG> {
51        self.variant(Davalid::Danotassigned)
52    }
53    #[doc = "DAASSIGNED: a dynamic address is assigned"]
54    #[inline(always)]
55    pub fn daassigned(self) -> &'a mut crate::W<REG> {
56        self.variant(Davalid::Daassigned)
57    }
58}
59#[doc = "Field `DADDR` reader - Dynamic Address"]
60pub type DaddrR = crate::FieldReader;
61#[doc = "Field `DADDR` writer - Dynamic Address"]
62pub type DaddrW<'a, REG> = crate::FieldWriter<'a, REG, 7>;
63#[doc = "Field `MAPSA` writer - Map a Static Address"]
64pub type MapsaW<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `SA10B` writer - 10-Bit Static Address"]
66pub type Sa10bW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
67#[doc = "Field `KEY` reader - Key"]
68pub type KeyR = crate::FieldReader<u16>;
69#[doc = "Field `KEY` writer - Key"]
70pub type KeyW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
71impl R {
72    #[doc = "Bit 0 - Dynamic Address Valid"]
73    #[inline(always)]
74    pub fn davalid(&self) -> DavalidR {
75        DavalidR::new((self.bits & 1) != 0)
76    }
77    #[doc = "Bits 1:7 - Dynamic Address"]
78    #[inline(always)]
79    pub fn daddr(&self) -> DaddrR {
80        DaddrR::new(((self.bits >> 1) & 0x7f) as u8)
81    }
82    #[doc = "Bits 16:31 - Key"]
83    #[inline(always)]
84    pub fn key(&self) -> KeyR {
85        KeyR::new(((self.bits >> 16) & 0xffff) as u16)
86    }
87}
88#[cfg(feature = "debug")]
89impl core::fmt::Debug for R {
90    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91        f.debug_struct("SDYNADDR")
92            .field("davalid", &self.davalid())
93            .field("daddr", &self.daddr())
94            .field("key", &self.key())
95            .finish()
96    }
97}
98impl W {
99    #[doc = "Bit 0 - Dynamic Address Valid"]
100    #[inline(always)]
101    pub fn davalid(&mut self) -> DavalidW<'_, SdynaddrSpec> {
102        DavalidW::new(self, 0)
103    }
104    #[doc = "Bits 1:7 - Dynamic Address"]
105    #[inline(always)]
106    pub fn daddr(&mut self) -> DaddrW<'_, SdynaddrSpec> {
107        DaddrW::new(self, 1)
108    }
109    #[doc = "Bit 12 - Map a Static Address"]
110    #[inline(always)]
111    pub fn mapsa(&mut self) -> MapsaW<'_, SdynaddrSpec> {
112        MapsaW::new(self, 12)
113    }
114    #[doc = "Bits 13:15 - 10-Bit Static Address"]
115    #[inline(always)]
116    pub fn sa10b(&mut self) -> Sa10bW<'_, SdynaddrSpec> {
117        Sa10bW::new(self, 13)
118    }
119    #[doc = "Bits 16:31 - Key"]
120    #[inline(always)]
121    pub fn key(&mut self) -> KeyW<'_, SdynaddrSpec> {
122        KeyW::new(self, 16)
123    }
124}
125#[doc = "Target Dynamic Address\n\nYou can [`read`](crate::Reg::read) this register and get [`sdynaddr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sdynaddr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
126pub struct SdynaddrSpec;
127impl crate::RegisterSpec for SdynaddrSpec {
128    type Ux = u32;
129}
130#[doc = "`read()` method returns [`sdynaddr::R`](R) reader structure"]
131impl crate::Readable for SdynaddrSpec {}
132#[doc = "`write(|w| ..)` method takes [`sdynaddr::W`](W) writer structure"]
133impl crate::Writable for SdynaddrSpec {
134    type Safety = crate::Unsafe;
135}
136#[doc = "`reset()` method sets SDYNADDR to value 0"]
137impl crate::Resettable for SdynaddrSpec {}
mcxa_pac/i3c0/sdynaddr.rs

mcxa_pac/i3c0/
sdynaddr.rs
