mcxa_pac/i3c0/
mrmsg_ddr.rs

1#[doc = "Register `MRMSG_DDR` reader"]
2pub type R = crate::R<MrmsgDdrSpec>;
3#[doc = "Field `DATA` reader - Data"]
4pub type DataR = crate::FieldReader<u16>;
5impl R {
6    #[doc = "Bits 0:15 - Data"]
7    #[inline(always)]
8    pub fn data(&self) -> DataR {
9        DataR::new((self.bits & 0xffff) as u16)
10    }
11}
12#[cfg(feature = "debug")]
13impl core::fmt::Debug for R {
14    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
15        f.debug_struct("MRMSG_DDR").field("data", &self.data()).finish()
16    }
17}
18#[doc = "Controller Read Message in DDR mode\n\nYou can [`read`](crate::Reg::read) this register and get [`mrmsg_ddr::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
19pub struct MrmsgDdrSpec;
20impl crate::RegisterSpec for MrmsgDdrSpec {
21    type Ux = u32;
22}
23#[doc = "`read()` method returns [`mrmsg_ddr::R`](R) reader structure"]
24impl crate::Readable for MrmsgDdrSpec {}
25#[doc = "`reset()` method sets MRMSG_DDR to value 0"]
26impl crate::Resettable for MrmsgDdrSpec {}
mcxa_pac/i3c0/mrmsg_ddr.rs

mcxa_pac/i3c0/
mrmsg_ddr.rs
