mcxa_pac/i3c0/
mdmactrl.rs

1#[doc = "Register `MDMACTRL` reader"]
2pub type R = crate::R<MdmactrlSpec>;
3#[doc = "Register `MDMACTRL` writer"]
4pub type W = crate::W<MdmactrlSpec>;
5#[doc = "DMA from Bus\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Dmafb {
10    #[doc = "0: DMA not used"]
11    NotUsed = 0,
12    #[doc = "1: Enable DMA for one frame"]
13    EnableOneFrame = 1,
14    #[doc = "2: Enable DMA until DMA is turned off"]
15    Enable = 2,
16}
17impl From<Dmafb> for u8 {
18    #[inline(always)]
19    fn from(variant: Dmafb) -> Self {
20        variant as _
21    }
22}
23impl crate::FieldSpec for Dmafb {
24    type Ux = u8;
25}
26impl crate::IsEnum for Dmafb {}
27#[doc = "Field `DMAFB` reader - DMA from Bus"]
28pub type DmafbR = crate::FieldReader<Dmafb>;
29impl DmafbR {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<Dmafb> {
33        match self.bits {
34            0 => Some(Dmafb::NotUsed),
35            1 => Some(Dmafb::EnableOneFrame),
36            2 => Some(Dmafb::Enable),
37            _ => None,
38        }
39    }
40    #[doc = "DMA not used"]
41    #[inline(always)]
42    pub fn is_not_used(&self) -> bool {
43        *self == Dmafb::NotUsed
44    }
45    #[doc = "Enable DMA for one frame"]
46    #[inline(always)]
47    pub fn is_enable_one_frame(&self) -> bool {
48        *self == Dmafb::EnableOneFrame
49    }
50    #[doc = "Enable DMA until DMA is turned off"]
51    #[inline(always)]
52    pub fn is_enable(&self) -> bool {
53        *self == Dmafb::Enable
54    }
55}
56#[doc = "Field `DMAFB` writer - DMA from Bus"]
57pub type DmafbW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmafb>;
58impl<'a, REG> DmafbW<'a, REG>
59where
60    REG: crate::Writable + crate::RegisterSpec,
61    REG::Ux: From<u8>,
62{
63    #[doc = "DMA not used"]
64    #[inline(always)]
65    pub fn not_used(self) -> &'a mut crate::W<REG> {
66        self.variant(Dmafb::NotUsed)
67    }
68    #[doc = "Enable DMA for one frame"]
69    #[inline(always)]
70    pub fn enable_one_frame(self) -> &'a mut crate::W<REG> {
71        self.variant(Dmafb::EnableOneFrame)
72    }
73    #[doc = "Enable DMA until DMA is turned off"]
74    #[inline(always)]
75    pub fn enable(self) -> &'a mut crate::W<REG> {
76        self.variant(Dmafb::Enable)
77    }
78}
79#[doc = "DMA to Bus\n\nValue on reset: 0"]
80#[cfg_attr(feature = "defmt", derive(defmt::Format))]
81#[derive(Clone, Copy, Debug, PartialEq, Eq)]
82#[repr(u8)]
83pub enum Dmatb {
84    #[doc = "0: DMA not used"]
85    NotUsed = 0,
86    #[doc = "1: Enable DMA for one frame (ended by DMA or terminated)"]
87    EnableOneFrame = 1,
88    #[doc = "2: Enable DMA until DMA is turned off"]
89    Enable = 2,
90}
91impl From<Dmatb> for u8 {
92    #[inline(always)]
93    fn from(variant: Dmatb) -> Self {
94        variant as _
95    }
96}
97impl crate::FieldSpec for Dmatb {
98    type Ux = u8;
99}
100impl crate::IsEnum for Dmatb {}
101#[doc = "Field `DMATB` reader - DMA to Bus"]
102pub type DmatbR = crate::FieldReader<Dmatb>;
103impl DmatbR {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub const fn variant(&self) -> Option<Dmatb> {
107        match self.bits {
108            0 => Some(Dmatb::NotUsed),
109            1 => Some(Dmatb::EnableOneFrame),
110            2 => Some(Dmatb::Enable),
111            _ => None,
112        }
113    }
114    #[doc = "DMA not used"]
115    #[inline(always)]
116    pub fn is_not_used(&self) -> bool {
117        *self == Dmatb::NotUsed
118    }
119    #[doc = "Enable DMA for one frame (ended by DMA or terminated)"]
120    #[inline(always)]
121    pub fn is_enable_one_frame(&self) -> bool {
122        *self == Dmatb::EnableOneFrame
123    }
124    #[doc = "Enable DMA until DMA is turned off"]
125    #[inline(always)]
126    pub fn is_enable(&self) -> bool {
127        *self == Dmatb::Enable
128    }
129}
130#[doc = "Field `DMATB` writer - DMA to Bus"]
131pub type DmatbW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmatb>;
132impl<'a, REG> DmatbW<'a, REG>
133where
134    REG: crate::Writable + crate::RegisterSpec,
135    REG::Ux: From<u8>,
136{
137    #[doc = "DMA not used"]
138    #[inline(always)]
139    pub fn not_used(self) -> &'a mut crate::W<REG> {
140        self.variant(Dmatb::NotUsed)
141    }
142    #[doc = "Enable DMA for one frame (ended by DMA or terminated)"]
143    #[inline(always)]
144    pub fn enable_one_frame(self) -> &'a mut crate::W<REG> {
145        self.variant(Dmatb::EnableOneFrame)
146    }
147    #[doc = "Enable DMA until DMA is turned off"]
148    #[inline(always)]
149    pub fn enable(self) -> &'a mut crate::W<REG> {
150        self.variant(Dmatb::Enable)
151    }
152}
153#[doc = "DMA Width\n\nValue on reset: 1"]
154#[cfg_attr(feature = "defmt", derive(defmt::Format))]
155#[derive(Clone, Copy, Debug, PartialEq, Eq)]
156#[repr(u8)]
157pub enum Dmawidth {
158    #[doc = "0: Byte"]
159    Byte0 = 0,
160    #[doc = "1: Byte"]
161    Byte1 = 1,
162    #[doc = "2: Halfword (16 bits)"]
163    HalfWord = 2,
164}
165impl From<Dmawidth> for u8 {
166    #[inline(always)]
167    fn from(variant: Dmawidth) -> Self {
168        variant as _
169    }
170}
171impl crate::FieldSpec for Dmawidth {
172    type Ux = u8;
173}
174impl crate::IsEnum for Dmawidth {}
175#[doc = "Field `DMAWIDTH` reader - DMA Width"]
176pub type DmawidthR = crate::FieldReader<Dmawidth>;
177impl DmawidthR {
178    #[doc = "Get enumerated values variant"]
179    #[inline(always)]
180    pub const fn variant(&self) -> Option<Dmawidth> {
181        match self.bits {
182            0 => Some(Dmawidth::Byte0),
183            1 => Some(Dmawidth::Byte1),
184            2 => Some(Dmawidth::HalfWord),
185            _ => None,
186        }
187    }
188    #[doc = "Byte"]
189    #[inline(always)]
190    pub fn is_byte_0(&self) -> bool {
191        *self == Dmawidth::Byte0
192    }
193    #[doc = "Byte"]
194    #[inline(always)]
195    pub fn is_byte_1(&self) -> bool {
196        *self == Dmawidth::Byte1
197    }
198    #[doc = "Halfword (16 bits)"]
199    #[inline(always)]
200    pub fn is_half_word(&self) -> bool {
201        *self == Dmawidth::HalfWord
202    }
203}
204#[doc = "Field `DMAWIDTH` writer - DMA Width"]
205pub type DmawidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dmawidth>;
206impl<'a, REG> DmawidthW<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209    REG::Ux: From<u8>,
210{
211    #[doc = "Byte"]
212    #[inline(always)]
213    pub fn byte_0(self) -> &'a mut crate::W<REG> {
214        self.variant(Dmawidth::Byte0)
215    }
216    #[doc = "Byte"]
217    #[inline(always)]
218    pub fn byte_1(self) -> &'a mut crate::W<REG> {
219        self.variant(Dmawidth::Byte1)
220    }
221    #[doc = "Halfword (16 bits)"]
222    #[inline(always)]
223    pub fn half_word(self) -> &'a mut crate::W<REG> {
224        self.variant(Dmawidth::HalfWord)
225    }
226}
227impl R {
228    #[doc = "Bits 0:1 - DMA from Bus"]
229    #[inline(always)]
230    pub fn dmafb(&self) -> DmafbR {
231        DmafbR::new((self.bits & 3) as u8)
232    }
233    #[doc = "Bits 2:3 - DMA to Bus"]
234    #[inline(always)]
235    pub fn dmatb(&self) -> DmatbR {
236        DmatbR::new(((self.bits >> 2) & 3) as u8)
237    }
238    #[doc = "Bits 4:5 - DMA Width"]
239    #[inline(always)]
240    pub fn dmawidth(&self) -> DmawidthR {
241        DmawidthR::new(((self.bits >> 4) & 3) as u8)
242    }
243}
244#[cfg(feature = "debug")]
245impl core::fmt::Debug for R {
246    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
247        f.debug_struct("MDMACTRL")
248            .field("dmafb", &self.dmafb())
249            .field("dmatb", &self.dmatb())
250            .field("dmawidth", &self.dmawidth())
251            .finish()
252    }
253}
254impl W {
255    #[doc = "Bits 0:1 - DMA from Bus"]
256    #[inline(always)]
257    pub fn dmafb(&mut self) -> DmafbW<'_, MdmactrlSpec> {
258        DmafbW::new(self, 0)
259    }
260    #[doc = "Bits 2:3 - DMA to Bus"]
261    #[inline(always)]
262    pub fn dmatb(&mut self) -> DmatbW<'_, MdmactrlSpec> {
263        DmatbW::new(self, 2)
264    }
265    #[doc = "Bits 4:5 - DMA Width"]
266    #[inline(always)]
267    pub fn dmawidth(&mut self) -> DmawidthW<'_, MdmactrlSpec> {
268        DmawidthW::new(self, 4)
269    }
270}
271#[doc = "Controller DMA Control\n\nYou can [`read`](crate::Reg::read) this register and get [`mdmactrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mdmactrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
272pub struct MdmactrlSpec;
273impl crate::RegisterSpec for MdmactrlSpec {
274    type Ux = u32;
275}
276#[doc = "`read()` method returns [`mdmactrl::R`](R) reader structure"]
277impl crate::Readable for MdmactrlSpec {}
278#[doc = "`write(|w| ..)` method takes [`mdmactrl::W`](W) writer structure"]
279impl crate::Writable for MdmactrlSpec {
280    type Safety = crate::Unsafe;
281}
282#[doc = "`reset()` method sets MDMACTRL to value 0x10"]
283impl crate::Resettable for MdmactrlSpec {
284    const RESET_VALUE: u32 = 0x10;
285}
mcxa_pac/i3c0/mdmactrl.rs

mcxa_pac/i3c0/
mdmactrl.rs
