1#[doc = "Register `PDIR` reader"]
2pub type R = crate::R<PdirSpec>;
3#[doc = "Port Data Input\n\nValue on reset: 0"]
4#[cfg_attr(feature = "defmt", derive(defmt::Format))]
5#[derive(Clone, Copy, Debug, PartialEq, Eq)]
6pub enum Pdi {
7 #[doc = "0: Logic 0"]
8 Pdi0 = 0,
9 #[doc = "1: Logic 1"]
10 Pdi1 = 1,
11}
12impl From<Pdi> for bool {
13 #[inline(always)]
14 fn from(variant: Pdi) -> Self {
15 variant as u8 != 0
16 }
17}
18#[doc = "Field `PDI(0-31)` reader - Port Data Input"]
19pub type PdiR = crate::BitReader<Pdi>;
20impl PdiR {
21 #[doc = "Get enumerated values variant"]
22 #[inline(always)]
23 pub const fn variant(&self) -> Pdi {
24 match self.bits {
25 false => Pdi::Pdi0,
26 true => Pdi::Pdi1,
27 }
28 }
29 #[doc = "Logic 0"]
30 #[inline(always)]
31 pub fn is_pdi0(&self) -> bool {
32 *self == Pdi::Pdi0
33 }
34 #[doc = "Logic 1"]
35 #[inline(always)]
36 pub fn is_pdi1(&self) -> bool {
37 *self == Pdi::Pdi1
38 }
39}
40impl R {
41 #[doc = "Port Data Input"]
42 #[doc = ""]
43 #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `PDI0` field.</div>"]
44 #[inline(always)]
45 pub fn pdi(&self, n: u8) -> PdiR {
46 #[allow(clippy::no_effect)]
47 [(); 32][n as usize];
48 PdiR::new(((self.bits >> n) & 1) != 0)
49 }
50 #[doc = "Iterator for array of:"]
51 #[doc = "Port Data Input"]
52 #[inline(always)]
53 pub fn pdi_iter(&self) -> impl Iterator<Item = PdiR> + '_ {
54 (0..32).map(move |n| PdiR::new(((self.bits >> n) & 1) != 0))
55 }
56 #[doc = "Bit 0 - Port Data Input"]
57 #[inline(always)]
58 pub fn pdi0(&self) -> PdiR {
59 PdiR::new((self.bits & 1) != 0)
60 }
61 #[doc = "Bit 1 - Port Data Input"]
62 #[inline(always)]
63 pub fn pdi1(&self) -> PdiR {
64 PdiR::new(((self.bits >> 1) & 1) != 0)
65 }
66 #[doc = "Bit 2 - Port Data Input"]
67 #[inline(always)]
68 pub fn pdi2(&self) -> PdiR {
69 PdiR::new(((self.bits >> 2) & 1) != 0)
70 }
71 #[doc = "Bit 3 - Port Data Input"]
72 #[inline(always)]
73 pub fn pdi3(&self) -> PdiR {
74 PdiR::new(((self.bits >> 3) & 1) != 0)
75 }
76 #[doc = "Bit 4 - Port Data Input"]
77 #[inline(always)]
78 pub fn pdi4(&self) -> PdiR {
79 PdiR::new(((self.bits >> 4) & 1) != 0)
80 }
81 #[doc = "Bit 5 - Port Data Input"]
82 #[inline(always)]
83 pub fn pdi5(&self) -> PdiR {
84 PdiR::new(((self.bits >> 5) & 1) != 0)
85 }
86 #[doc = "Bit 6 - Port Data Input"]
87 #[inline(always)]
88 pub fn pdi6(&self) -> PdiR {
89 PdiR::new(((self.bits >> 6) & 1) != 0)
90 }
91 #[doc = "Bit 7 - Port Data Input"]
92 #[inline(always)]
93 pub fn pdi7(&self) -> PdiR {
94 PdiR::new(((self.bits >> 7) & 1) != 0)
95 }
96 #[doc = "Bit 8 - Port Data Input"]
97 #[inline(always)]
98 pub fn pdi8(&self) -> PdiR {
99 PdiR::new(((self.bits >> 8) & 1) != 0)
100 }
101 #[doc = "Bit 9 - Port Data Input"]
102 #[inline(always)]
103 pub fn pdi9(&self) -> PdiR {
104 PdiR::new(((self.bits >> 9) & 1) != 0)
105 }
106 #[doc = "Bit 10 - Port Data Input"]
107 #[inline(always)]
108 pub fn pdi10(&self) -> PdiR {
109 PdiR::new(((self.bits >> 10) & 1) != 0)
110 }
111 #[doc = "Bit 11 - Port Data Input"]
112 #[inline(always)]
113 pub fn pdi11(&self) -> PdiR {
114 PdiR::new(((self.bits >> 11) & 1) != 0)
115 }
116 #[doc = "Bit 12 - Port Data Input"]
117 #[inline(always)]
118 pub fn pdi12(&self) -> PdiR {
119 PdiR::new(((self.bits >> 12) & 1) != 0)
120 }
121 #[doc = "Bit 13 - Port Data Input"]
122 #[inline(always)]
123 pub fn pdi13(&self) -> PdiR {
124 PdiR::new(((self.bits >> 13) & 1) != 0)
125 }
126 #[doc = "Bit 14 - Port Data Input"]
127 #[inline(always)]
128 pub fn pdi14(&self) -> PdiR {
129 PdiR::new(((self.bits >> 14) & 1) != 0)
130 }
131 #[doc = "Bit 15 - Port Data Input"]
132 #[inline(always)]
133 pub fn pdi15(&self) -> PdiR {
134 PdiR::new(((self.bits >> 15) & 1) != 0)
135 }
136 #[doc = "Bit 16 - Port Data Input"]
137 #[inline(always)]
138 pub fn pdi16(&self) -> PdiR {
139 PdiR::new(((self.bits >> 16) & 1) != 0)
140 }
141 #[doc = "Bit 17 - Port Data Input"]
142 #[inline(always)]
143 pub fn pdi17(&self) -> PdiR {
144 PdiR::new(((self.bits >> 17) & 1) != 0)
145 }
146 #[doc = "Bit 18 - Port Data Input"]
147 #[inline(always)]
148 pub fn pdi18(&self) -> PdiR {
149 PdiR::new(((self.bits >> 18) & 1) != 0)
150 }
151 #[doc = "Bit 19 - Port Data Input"]
152 #[inline(always)]
153 pub fn pdi19(&self) -> PdiR {
154 PdiR::new(((self.bits >> 19) & 1) != 0)
155 }
156 #[doc = "Bit 20 - Port Data Input"]
157 #[inline(always)]
158 pub fn pdi20(&self) -> PdiR {
159 PdiR::new(((self.bits >> 20) & 1) != 0)
160 }
161 #[doc = "Bit 21 - Port Data Input"]
162 #[inline(always)]
163 pub fn pdi21(&self) -> PdiR {
164 PdiR::new(((self.bits >> 21) & 1) != 0)
165 }
166 #[doc = "Bit 22 - Port Data Input"]
167 #[inline(always)]
168 pub fn pdi22(&self) -> PdiR {
169 PdiR::new(((self.bits >> 22) & 1) != 0)
170 }
171 #[doc = "Bit 23 - Port Data Input"]
172 #[inline(always)]
173 pub fn pdi23(&self) -> PdiR {
174 PdiR::new(((self.bits >> 23) & 1) != 0)
175 }
176 #[doc = "Bit 24 - Port Data Input"]
177 #[inline(always)]
178 pub fn pdi24(&self) -> PdiR {
179 PdiR::new(((self.bits >> 24) & 1) != 0)
180 }
181 #[doc = "Bit 25 - Port Data Input"]
182 #[inline(always)]
183 pub fn pdi25(&self) -> PdiR {
184 PdiR::new(((self.bits >> 25) & 1) != 0)
185 }
186 #[doc = "Bit 26 - Port Data Input"]
187 #[inline(always)]
188 pub fn pdi26(&self) -> PdiR {
189 PdiR::new(((self.bits >> 26) & 1) != 0)
190 }
191 #[doc = "Bit 27 - Port Data Input"]
192 #[inline(always)]
193 pub fn pdi27(&self) -> PdiR {
194 PdiR::new(((self.bits >> 27) & 1) != 0)
195 }
196 #[doc = "Bit 28 - Port Data Input"]
197 #[inline(always)]
198 pub fn pdi28(&self) -> PdiR {
199 PdiR::new(((self.bits >> 28) & 1) != 0)
200 }
201 #[doc = "Bit 29 - Port Data Input"]
202 #[inline(always)]
203 pub fn pdi29(&self) -> PdiR {
204 PdiR::new(((self.bits >> 29) & 1) != 0)
205 }
206 #[doc = "Bit 30 - Port Data Input"]
207 #[inline(always)]
208 pub fn pdi30(&self) -> PdiR {
209 PdiR::new(((self.bits >> 30) & 1) != 0)
210 }
211 #[doc = "Bit 31 - Port Data Input"]
212 #[inline(always)]
213 pub fn pdi31(&self) -> PdiR {
214 PdiR::new(((self.bits >> 31) & 1) != 0)
215 }
216}
217#[cfg(feature = "debug")]
218impl core::fmt::Debug for R {
219 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
220 f.debug_struct("PDIR")
221 .field("pdi0", &self.pdi0())
222 .field("pdi1", &self.pdi1())
223 .field("pdi2", &self.pdi2())
224 .field("pdi3", &self.pdi3())
225 .field("pdi4", &self.pdi4())
226 .field("pdi5", &self.pdi5())
227 .field("pdi6", &self.pdi6())
228 .field("pdi7", &self.pdi7())
229 .field("pdi8", &self.pdi8())
230 .field("pdi9", &self.pdi9())
231 .field("pdi10", &self.pdi10())
232 .field("pdi11", &self.pdi11())
233 .field("pdi12", &self.pdi12())
234 .field("pdi13", &self.pdi13())
235 .field("pdi14", &self.pdi14())
236 .field("pdi15", &self.pdi15())
237 .field("pdi16", &self.pdi16())
238 .field("pdi17", &self.pdi17())
239 .field("pdi18", &self.pdi18())
240 .field("pdi19", &self.pdi19())
241 .field("pdi20", &self.pdi20())
242 .field("pdi21", &self.pdi21())
243 .field("pdi22", &self.pdi22())
244 .field("pdi23", &self.pdi23())
245 .field("pdi24", &self.pdi24())
246 .field("pdi25", &self.pdi25())
247 .field("pdi26", &self.pdi26())
248 .field("pdi27", &self.pdi27())
249 .field("pdi28", &self.pdi28())
250 .field("pdi29", &self.pdi29())
251 .field("pdi30", &self.pdi30())
252 .field("pdi31", &self.pdi31())
253 .finish()
254 }
255}
256#[doc = "Port Data Input\n\nYou can [`read`](crate::Reg::read) this register and get [`pdir::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
257pub struct PdirSpec;
258impl crate::RegisterSpec for PdirSpec {
259 type Ux = u32;
260}
261#[doc = "`read()` method returns [`pdir::R`](R) reader structure"]
262impl crate::Readable for PdirSpec {}
263#[doc = "`reset()` method sets PDIR to value 0"]
264impl crate::Resettable for PdirSpec {}