mcxa_pac/gpio0/
icr.rs

1#[doc = "Register `ICR[%s]` reader"]
2pub type R = crate::R<IcrSpec>;
3#[doc = "Register `ICR[%s]` writer"]
4pub type W = crate::W<IcrSpec>;
5#[doc = "Interrupt Configuration\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Irqc {
10    #[doc = "0: ISF is disabled"]
11    Irqc0 = 0,
12    #[doc = "1: ISF and DMA request on rising edge"]
13    Irqc1 = 1,
14    #[doc = "2: ISF and DMA request on falling edge"]
15    Irqc2 = 2,
16    #[doc = "3: ISF and DMA request on either edge"]
17    Irqc3 = 3,
18    #[doc = "5: ISF sets on rising edge"]
19    Irqc5 = 5,
20    #[doc = "6: ISF sets on falling edge"]
21    Irqc6 = 6,
22    #[doc = "7: ISF sets on either edge"]
23    Irqc7 = 7,
24    #[doc = "8: ISF and interrupt when logic 0"]
25    Irqc8 = 8,
26    #[doc = "9: ISF and interrupt on rising edge"]
27    Irqc9 = 9,
28    #[doc = "10: ISF and interrupt on falling edge"]
29    Irqc10 = 10,
30    #[doc = "11: ISF and Interrupt on either edge"]
31    Irqc11 = 11,
32    #[doc = "12: ISF and interrupt when logic 1"]
33    Irqc12 = 12,
34    #[doc = "13: Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals)"]
35    Irqc13 = 13,
36    #[doc = "14: Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals)"]
37    Irqc14 = 14,
38}
39impl From<Irqc> for u8 {
40    #[inline(always)]
41    fn from(variant: Irqc) -> Self {
42        variant as _
43    }
44}
45impl crate::FieldSpec for Irqc {
46    type Ux = u8;
47}
48impl crate::IsEnum for Irqc {}
49#[doc = "Field `IRQC` reader - Interrupt Configuration"]
50pub type IrqcR = crate::FieldReader<Irqc>;
51impl IrqcR {
52    #[doc = "Get enumerated values variant"]
53    #[inline(always)]
54    pub const fn variant(&self) -> Option<Irqc> {
55        match self.bits {
56            0 => Some(Irqc::Irqc0),
57            1 => Some(Irqc::Irqc1),
58            2 => Some(Irqc::Irqc2),
59            3 => Some(Irqc::Irqc3),
60            5 => Some(Irqc::Irqc5),
61            6 => Some(Irqc::Irqc6),
62            7 => Some(Irqc::Irqc7),
63            8 => Some(Irqc::Irqc8),
64            9 => Some(Irqc::Irqc9),
65            10 => Some(Irqc::Irqc10),
66            11 => Some(Irqc::Irqc11),
67            12 => Some(Irqc::Irqc12),
68            13 => Some(Irqc::Irqc13),
69            14 => Some(Irqc::Irqc14),
70            _ => None,
71        }
72    }
73    #[doc = "ISF is disabled"]
74    #[inline(always)]
75    pub fn is_irqc0(&self) -> bool {
76        *self == Irqc::Irqc0
77    }
78    #[doc = "ISF and DMA request on rising edge"]
79    #[inline(always)]
80    pub fn is_irqc1(&self) -> bool {
81        *self == Irqc::Irqc1
82    }
83    #[doc = "ISF and DMA request on falling edge"]
84    #[inline(always)]
85    pub fn is_irqc2(&self) -> bool {
86        *self == Irqc::Irqc2
87    }
88    #[doc = "ISF and DMA request on either edge"]
89    #[inline(always)]
90    pub fn is_irqc3(&self) -> bool {
91        *self == Irqc::Irqc3
92    }
93    #[doc = "ISF sets on rising edge"]
94    #[inline(always)]
95    pub fn is_irqc5(&self) -> bool {
96        *self == Irqc::Irqc5
97    }
98    #[doc = "ISF sets on falling edge"]
99    #[inline(always)]
100    pub fn is_irqc6(&self) -> bool {
101        *self == Irqc::Irqc6
102    }
103    #[doc = "ISF sets on either edge"]
104    #[inline(always)]
105    pub fn is_irqc7(&self) -> bool {
106        *self == Irqc::Irqc7
107    }
108    #[doc = "ISF and interrupt when logic 0"]
109    #[inline(always)]
110    pub fn is_irqc8(&self) -> bool {
111        *self == Irqc::Irqc8
112    }
113    #[doc = "ISF and interrupt on rising edge"]
114    #[inline(always)]
115    pub fn is_irqc9(&self) -> bool {
116        *self == Irqc::Irqc9
117    }
118    #[doc = "ISF and interrupt on falling edge"]
119    #[inline(always)]
120    pub fn is_irqc10(&self) -> bool {
121        *self == Irqc::Irqc10
122    }
123    #[doc = "ISF and Interrupt on either edge"]
124    #[inline(always)]
125    pub fn is_irqc11(&self) -> bool {
126        *self == Irqc::Irqc11
127    }
128    #[doc = "ISF and interrupt when logic 1"]
129    #[inline(always)]
130    pub fn is_irqc12(&self) -> bool {
131        *self == Irqc::Irqc12
132    }
133    #[doc = "Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals)"]
134    #[inline(always)]
135    pub fn is_irqc13(&self) -> bool {
136        *self == Irqc::Irqc13
137    }
138    #[doc = "Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals)"]
139    #[inline(always)]
140    pub fn is_irqc14(&self) -> bool {
141        *self == Irqc::Irqc14
142    }
143}
144#[doc = "Field `IRQC` writer - Interrupt Configuration"]
145pub type IrqcW<'a, REG> = crate::FieldWriter<'a, REG, 4, Irqc>;
146impl<'a, REG> IrqcW<'a, REG>
147where
148    REG: crate::Writable + crate::RegisterSpec,
149    REG::Ux: From<u8>,
150{
151    #[doc = "ISF is disabled"]
152    #[inline(always)]
153    pub fn irqc0(self) -> &'a mut crate::W<REG> {
154        self.variant(Irqc::Irqc0)
155    }
156    #[doc = "ISF and DMA request on rising edge"]
157    #[inline(always)]
158    pub fn irqc1(self) -> &'a mut crate::W<REG> {
159        self.variant(Irqc::Irqc1)
160    }
161    #[doc = "ISF and DMA request on falling edge"]
162    #[inline(always)]
163    pub fn irqc2(self) -> &'a mut crate::W<REG> {
164        self.variant(Irqc::Irqc2)
165    }
166    #[doc = "ISF and DMA request on either edge"]
167    #[inline(always)]
168    pub fn irqc3(self) -> &'a mut crate::W<REG> {
169        self.variant(Irqc::Irqc3)
170    }
171    #[doc = "ISF sets on rising edge"]
172    #[inline(always)]
173    pub fn irqc5(self) -> &'a mut crate::W<REG> {
174        self.variant(Irqc::Irqc5)
175    }
176    #[doc = "ISF sets on falling edge"]
177    #[inline(always)]
178    pub fn irqc6(self) -> &'a mut crate::W<REG> {
179        self.variant(Irqc::Irqc6)
180    }
181    #[doc = "ISF sets on either edge"]
182    #[inline(always)]
183    pub fn irqc7(self) -> &'a mut crate::W<REG> {
184        self.variant(Irqc::Irqc7)
185    }
186    #[doc = "ISF and interrupt when logic 0"]
187    #[inline(always)]
188    pub fn irqc8(self) -> &'a mut crate::W<REG> {
189        self.variant(Irqc::Irqc8)
190    }
191    #[doc = "ISF and interrupt on rising edge"]
192    #[inline(always)]
193    pub fn irqc9(self) -> &'a mut crate::W<REG> {
194        self.variant(Irqc::Irqc9)
195    }
196    #[doc = "ISF and interrupt on falling edge"]
197    #[inline(always)]
198    pub fn irqc10(self) -> &'a mut crate::W<REG> {
199        self.variant(Irqc::Irqc10)
200    }
201    #[doc = "ISF and Interrupt on either edge"]
202    #[inline(always)]
203    pub fn irqc11(self) -> &'a mut crate::W<REG> {
204        self.variant(Irqc::Irqc11)
205    }
206    #[doc = "ISF and interrupt when logic 1"]
207    #[inline(always)]
208    pub fn irqc12(self) -> &'a mut crate::W<REG> {
209        self.variant(Irqc::Irqc12)
210    }
211    #[doc = "Enable active-high trigger output; ISF on rising edge (pin state is ORed with other enabled triggers to generate the output trigger for use by other peripherals)"]
212    #[inline(always)]
213    pub fn irqc13(self) -> &'a mut crate::W<REG> {
214        self.variant(Irqc::Irqc13)
215    }
216    #[doc = "Enable active-low trigger output; ISF on falling edge (pin state is inverted and ORed with other enabled triggers to generate the output trigger for use by other peripherals)"]
217    #[inline(always)]
218    pub fn irqc14(self) -> &'a mut crate::W<REG> {
219        self.variant(Irqc::Irqc14)
220    }
221}
222#[doc = "Interrupt Status Flag\n\nValue on reset: 0"]
223#[cfg_attr(feature = "defmt", derive(defmt::Format))]
224#[derive(Clone, Copy, Debug, PartialEq, Eq)]
225pub enum Isf {
226    #[doc = "0: Not detected"]
227    Isf0 = 0,
228    #[doc = "1: Detected"]
229    Isf1 = 1,
230}
231impl From<Isf> for bool {
232    #[inline(always)]
233    fn from(variant: Isf) -> Self {
234        variant as u8 != 0
235    }
236}
237#[doc = "Field `ISF` reader - Interrupt Status Flag"]
238pub type IsfR = crate::BitReader<Isf>;
239impl IsfR {
240    #[doc = "Get enumerated values variant"]
241    #[inline(always)]
242    pub const fn variant(&self) -> Isf {
243        match self.bits {
244            false => Isf::Isf0,
245            true => Isf::Isf1,
246        }
247    }
248    #[doc = "Not detected"]
249    #[inline(always)]
250    pub fn is_isf0(&self) -> bool {
251        *self == Isf::Isf0
252    }
253    #[doc = "Detected"]
254    #[inline(always)]
255    pub fn is_isf1(&self) -> bool {
256        *self == Isf::Isf1
257    }
258}
259#[doc = "Field `ISF` writer - Interrupt Status Flag"]
260pub type IsfW<'a, REG> = crate::BitWriter1C<'a, REG, Isf>;
261impl<'a, REG> IsfW<'a, REG>
262where
263    REG: crate::Writable + crate::RegisterSpec,
264{
265    #[doc = "Not detected"]
266    #[inline(always)]
267    pub fn isf0(self) -> &'a mut crate::W<REG> {
268        self.variant(Isf::Isf0)
269    }
270    #[doc = "Detected"]
271    #[inline(always)]
272    pub fn isf1(self) -> &'a mut crate::W<REG> {
273        self.variant(Isf::Isf1)
274    }
275}
276impl R {
277    #[doc = "Bits 16:19 - Interrupt Configuration"]
278    #[inline(always)]
279    pub fn irqc(&self) -> IrqcR {
280        IrqcR::new(((self.bits >> 16) & 0x0f) as u8)
281    }
282    #[doc = "Bit 24 - Interrupt Status Flag"]
283    #[inline(always)]
284    pub fn isf(&self) -> IsfR {
285        IsfR::new(((self.bits >> 24) & 1) != 0)
286    }
287}
288#[cfg(feature = "debug")]
289impl core::fmt::Debug for R {
290    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
291        f.debug_struct("ICR")
292            .field("irqc", &self.irqc())
293            .field("isf", &self.isf())
294            .finish()
295    }
296}
297impl W {
298    #[doc = "Bits 16:19 - Interrupt Configuration"]
299    #[inline(always)]
300    pub fn irqc(&mut self) -> IrqcW<'_, IcrSpec> {
301        IrqcW::new(self, 16)
302    }
303    #[doc = "Bit 24 - Interrupt Status Flag"]
304    #[inline(always)]
305    pub fn isf(&mut self) -> IsfW<'_, IcrSpec> {
306        IsfW::new(self, 24)
307    }
308}
309#[doc = "Interrupt Control index\n\nYou can [`read`](crate::Reg::read) this register and get [`icr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`icr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
310pub struct IcrSpec;
311impl crate::RegisterSpec for IcrSpec {
312    type Ux = u32;
313}
314#[doc = "`read()` method returns [`icr::R`](R) reader structure"]
315impl crate::Readable for IcrSpec {}
316#[doc = "`write(|w| ..)` method takes [`icr::W`](W) writer structure"]
317impl crate::Writable for IcrSpec {
318    type Safety = crate::Unsafe;
319    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0100_0000;
320}
321#[doc = "`reset()` method sets ICR[%s] to value 0"]
322impl crate::Resettable for IcrSpec {}
mcxa_pac/gpio0/icr.rs

mcxa_pac/gpio0/
icr.rs
