mcxa_pac/flexpwm0/
ftst0.rs

1#[doc = "Register `FTST0` reader"]
2pub type R = crate::R<Ftst0Spec>;
3#[doc = "Register `FTST0` writer"]
4pub type W = crate::W<Ftst0Spec>;
5#[doc = "Fault Test\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Ftest {
9    #[doc = "0: No fault"]
10    NoFault = 0,
11    #[doc = "1: Cause a simulated fault"]
12    Fault = 1,
13}
14impl From<Ftest> for bool {
15    #[inline(always)]
16    fn from(variant: Ftest) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `FTEST` reader - Fault Test"]
21pub type FtestR = crate::BitReader<Ftest>;
22impl FtestR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Ftest {
26        match self.bits {
27            false => Ftest::NoFault,
28            true => Ftest::Fault,
29        }
30    }
31    #[doc = "No fault"]
32    #[inline(always)]
33    pub fn is_no_fault(&self) -> bool {
34        *self == Ftest::NoFault
35    }
36    #[doc = "Cause a simulated fault"]
37    #[inline(always)]
38    pub fn is_fault(&self) -> bool {
39        *self == Ftest::Fault
40    }
41}
42#[doc = "Field `FTEST` writer - Fault Test"]
43pub type FtestW<'a, REG> = crate::BitWriter<'a, REG, Ftest>;
44impl<'a, REG> FtestW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "No fault"]
49    #[inline(always)]
50    pub fn no_fault(self) -> &'a mut crate::W<REG> {
51        self.variant(Ftest::NoFault)
52    }
53    #[doc = "Cause a simulated fault"]
54    #[inline(always)]
55    pub fn fault(self) -> &'a mut crate::W<REG> {
56        self.variant(Ftest::Fault)
57    }
58}
59impl R {
60    #[doc = "Bit 0 - Fault Test"]
61    #[inline(always)]
62    pub fn ftest(&self) -> FtestR {
63        FtestR::new((self.bits & 1) != 0)
64    }
65}
66#[cfg(feature = "debug")]
67impl core::fmt::Debug for R {
68    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
69        f.debug_struct("FTST0").field("ftest", &self.ftest()).finish()
70    }
71}
72impl W {
73    #[doc = "Bit 0 - Fault Test"]
74    #[inline(always)]
75    pub fn ftest(&mut self) -> FtestW<'_, Ftst0Spec> {
76        FtestW::new(self, 0)
77    }
78}
79#[doc = "Fault Test Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ftst0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ftst0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
80pub struct Ftst0Spec;
81impl crate::RegisterSpec for Ftst0Spec {
82    type Ux = u16;
83}
84#[doc = "`read()` method returns [`ftst0::R`](R) reader structure"]
85impl crate::Readable for Ftst0Spec {}
86#[doc = "`write(|w| ..)` method takes [`ftst0::W`](W) writer structure"]
87impl crate::Writable for Ftst0Spec {
88    type Safety = crate::Unsafe;
89}
90#[doc = "`reset()` method sets FTST0 to value 0"]
91impl crate::Resettable for Ftst0Spec {}
mcxa_pac/flexpwm0/ftst0.rs

mcxa_pac/flexpwm0/
ftst0.rs
