mcxa_pac/flexpwm0/
fsts0.rs

1#[doc = "Register `FSTS0` reader"]
2pub type R = crate::R<Fsts0Spec>;
3#[doc = "Register `FSTS0` writer"]
4pub type W = crate::W<Fsts0Spec>;
5#[doc = "Fault Flags\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Fflag {
10    #[doc = "0: No fault on the FAULTx pin."]
11    NoFlag = 0,
12    #[doc = "1: Fault on the FAULTx pin."]
13    Flag = 1,
14}
15impl From<Fflag> for u8 {
16    #[inline(always)]
17    fn from(variant: Fflag) -> Self {
18        variant as _
19    }
20}
21impl crate::FieldSpec for Fflag {
22    type Ux = u8;
23}
24impl crate::IsEnum for Fflag {}
25#[doc = "Field `FFLAG` reader - Fault Flags"]
26pub type FflagR = crate::FieldReader<Fflag>;
27impl FflagR {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> Option<Fflag> {
31        match self.bits {
32            0 => Some(Fflag::NoFlag),
33            1 => Some(Fflag::Flag),
34            _ => None,
35        }
36    }
37    #[doc = "No fault on the FAULTx pin."]
38    #[inline(always)]
39    pub fn is_no_flag(&self) -> bool {
40        *self == Fflag::NoFlag
41    }
42    #[doc = "Fault on the FAULTx pin."]
43    #[inline(always)]
44    pub fn is_flag(&self) -> bool {
45        *self == Fflag::Flag
46    }
47}
48#[doc = "Field `FFLAG` writer - Fault Flags"]
49pub type FflagW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fflag>;
50impl<'a, REG> FflagW<'a, REG>
51where
52    REG: crate::Writable + crate::RegisterSpec,
53    REG::Ux: From<u8>,
54{
55    #[doc = "No fault on the FAULTx pin."]
56    #[inline(always)]
57    pub fn no_flag(self) -> &'a mut crate::W<REG> {
58        self.variant(Fflag::NoFlag)
59    }
60    #[doc = "Fault on the FAULTx pin."]
61    #[inline(always)]
62    pub fn flag(self) -> &'a mut crate::W<REG> {
63        self.variant(Fflag::Flag)
64    }
65}
66#[doc = "Full Cycle\n\nValue on reset: 0"]
67#[cfg_attr(feature = "defmt", derive(defmt::Format))]
68#[derive(Clone, Copy, Debug, PartialEq, Eq)]
69#[repr(u8)]
70pub enum Ffull {
71    #[doc = "0: PWM outputs are not re-enabled at the start of a full cycle"]
72    PwmOutputsNotReenabled = 0,
73    #[doc = "1: PWM outputs are re-enabled at the start of a full cycle"]
74    PwmOutputsReenabled = 1,
75}
76impl From<Ffull> for u8 {
77    #[inline(always)]
78    fn from(variant: Ffull) -> Self {
79        variant as _
80    }
81}
82impl crate::FieldSpec for Ffull {
83    type Ux = u8;
84}
85impl crate::IsEnum for Ffull {}
86#[doc = "Field `FFULL` reader - Full Cycle"]
87pub type FfullR = crate::FieldReader<Ffull>;
88impl FfullR {
89    #[doc = "Get enumerated values variant"]
90    #[inline(always)]
91    pub const fn variant(&self) -> Option<Ffull> {
92        match self.bits {
93            0 => Some(Ffull::PwmOutputsNotReenabled),
94            1 => Some(Ffull::PwmOutputsReenabled),
95            _ => None,
96        }
97    }
98    #[doc = "PWM outputs are not re-enabled at the start of a full cycle"]
99    #[inline(always)]
100    pub fn is_pwm_outputs_not_reenabled(&self) -> bool {
101        *self == Ffull::PwmOutputsNotReenabled
102    }
103    #[doc = "PWM outputs are re-enabled at the start of a full cycle"]
104    #[inline(always)]
105    pub fn is_pwm_outputs_reenabled(&self) -> bool {
106        *self == Ffull::PwmOutputsReenabled
107    }
108}
109#[doc = "Field `FFULL` writer - Full Cycle"]
110pub type FfullW<'a, REG> = crate::FieldWriter<'a, REG, 4, Ffull>;
111impl<'a, REG> FfullW<'a, REG>
112where
113    REG: crate::Writable + crate::RegisterSpec,
114    REG::Ux: From<u8>,
115{
116    #[doc = "PWM outputs are not re-enabled at the start of a full cycle"]
117    #[inline(always)]
118    pub fn pwm_outputs_not_reenabled(self) -> &'a mut crate::W<REG> {
119        self.variant(Ffull::PwmOutputsNotReenabled)
120    }
121    #[doc = "PWM outputs are re-enabled at the start of a full cycle"]
122    #[inline(always)]
123    pub fn pwm_outputs_reenabled(self) -> &'a mut crate::W<REG> {
124        self.variant(Ffull::PwmOutputsReenabled)
125    }
126}
127#[doc = "Field `FFPIN` reader - Filtered Fault Pins"]
128pub type FfpinR = crate::FieldReader;
129#[doc = "Half Cycle Fault Recovery\n\nValue on reset: 0"]
130#[cfg_attr(feature = "defmt", derive(defmt::Format))]
131#[derive(Clone, Copy, Debug, PartialEq, Eq)]
132#[repr(u8)]
133pub enum Fhalf {
134    #[doc = "0: PWM outputs are not re-enabled at the start of a half cycle."]
135    PwmOutputsNotReenabled = 0,
136    #[doc = "1: PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0)."]
137    PwmOutputsReenabled = 1,
138}
139impl From<Fhalf> for u8 {
140    #[inline(always)]
141    fn from(variant: Fhalf) -> Self {
142        variant as _
143    }
144}
145impl crate::FieldSpec for Fhalf {
146    type Ux = u8;
147}
148impl crate::IsEnum for Fhalf {}
149#[doc = "Field `FHALF` reader - Half Cycle Fault Recovery"]
150pub type FhalfR = crate::FieldReader<Fhalf>;
151impl FhalfR {
152    #[doc = "Get enumerated values variant"]
153    #[inline(always)]
154    pub const fn variant(&self) -> Option<Fhalf> {
155        match self.bits {
156            0 => Some(Fhalf::PwmOutputsNotReenabled),
157            1 => Some(Fhalf::PwmOutputsReenabled),
158            _ => None,
159        }
160    }
161    #[doc = "PWM outputs are not re-enabled at the start of a half cycle."]
162    #[inline(always)]
163    pub fn is_pwm_outputs_not_reenabled(&self) -> bool {
164        *self == Fhalf::PwmOutputsNotReenabled
165    }
166    #[doc = "PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0)."]
167    #[inline(always)]
168    pub fn is_pwm_outputs_reenabled(&self) -> bool {
169        *self == Fhalf::PwmOutputsReenabled
170    }
171}
172#[doc = "Field `FHALF` writer - Half Cycle Fault Recovery"]
173pub type FhalfW<'a, REG> = crate::FieldWriter<'a, REG, 4, Fhalf>;
174impl<'a, REG> FhalfW<'a, REG>
175where
176    REG: crate::Writable + crate::RegisterSpec,
177    REG::Ux: From<u8>,
178{
179    #[doc = "PWM outputs are not re-enabled at the start of a half cycle."]
180    #[inline(always)]
181    pub fn pwm_outputs_not_reenabled(self) -> &'a mut crate::W<REG> {
182        self.variant(Fhalf::PwmOutputsNotReenabled)
183    }
184    #[doc = "PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0)."]
185    #[inline(always)]
186    pub fn pwm_outputs_reenabled(self) -> &'a mut crate::W<REG> {
187        self.variant(Fhalf::PwmOutputsReenabled)
188    }
189}
190impl R {
191    #[doc = "Bits 0:3 - Fault Flags"]
192    #[inline(always)]
193    pub fn fflag(&self) -> FflagR {
194        FflagR::new((self.bits & 0x0f) as u8)
195    }
196    #[doc = "Bits 4:7 - Full Cycle"]
197    #[inline(always)]
198    pub fn ffull(&self) -> FfullR {
199        FfullR::new(((self.bits >> 4) & 0x0f) as u8)
200    }
201    #[doc = "Bits 8:11 - Filtered Fault Pins"]
202    #[inline(always)]
203    pub fn ffpin(&self) -> FfpinR {
204        FfpinR::new(((self.bits >> 8) & 0x0f) as u8)
205    }
206    #[doc = "Bits 12:15 - Half Cycle Fault Recovery"]
207    #[inline(always)]
208    pub fn fhalf(&self) -> FhalfR {
209        FhalfR::new(((self.bits >> 12) & 0x0f) as u8)
210    }
211}
212#[cfg(feature = "debug")]
213impl core::fmt::Debug for R {
214    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
215        f.debug_struct("FSTS0")
216            .field("fflag", &self.fflag())
217            .field("ffull", &self.ffull())
218            .field("ffpin", &self.ffpin())
219            .field("fhalf", &self.fhalf())
220            .finish()
221    }
222}
223impl W {
224    #[doc = "Bits 0:3 - Fault Flags"]
225    #[inline(always)]
226    pub fn fflag(&mut self) -> FflagW<'_, Fsts0Spec> {
227        FflagW::new(self, 0)
228    }
229    #[doc = "Bits 4:7 - Full Cycle"]
230    #[inline(always)]
231    pub fn ffull(&mut self) -> FfullW<'_, Fsts0Spec> {
232        FfullW::new(self, 4)
233    }
234    #[doc = "Bits 12:15 - Half Cycle Fault Recovery"]
235    #[inline(always)]
236    pub fn fhalf(&mut self) -> FhalfW<'_, Fsts0Spec> {
237        FhalfW::new(self, 12)
238    }
239}
240#[doc = "Fault Status Register\n\nYou can [`read`](crate::Reg::read) this register and get [`fsts0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fsts0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
241pub struct Fsts0Spec;
242impl crate::RegisterSpec for Fsts0Spec {
243    type Ux = u16;
244}
245#[doc = "`read()` method returns [`fsts0::R`](R) reader structure"]
246impl crate::Readable for Fsts0Spec {}
247#[doc = "`write(|w| ..)` method takes [`fsts0::W`](W) writer structure"]
248impl crate::Writable for Fsts0Spec {
249    type Safety = crate::Unsafe;
250}
251#[doc = "`reset()` method sets FSTS0 to value 0"]
252impl crate::Resettable for Fsts0Spec {}
mcxa_pac/flexpwm0/fsts0.rs

mcxa_pac/flexpwm0/
fsts0.rs
