mcxa_pac/flexpwm0/
ffilt0.rs

1#[doc = "Register `FFILT0` reader"]
2pub type R = crate::R<Ffilt0Spec>;
3#[doc = "Register `FFILT0` writer"]
4pub type W = crate::W<Ffilt0Spec>;
5#[doc = "Field `FILT_PER` reader - Fault Filter Period"]
6pub type FiltPerR = crate::FieldReader;
7#[doc = "Field `FILT_PER` writer - Fault Filter Period"]
8pub type FiltPerW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `FILT_CNT` reader - Fault Filter Count"]
10pub type FiltCntR = crate::FieldReader;
11#[doc = "Field `FILT_CNT` writer - Fault Filter Count"]
12pub type FiltCntW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Fault Glitch Stretch Enable\n\nValue on reset: 0"]
14#[cfg_attr(feature = "defmt", derive(defmt::Format))]
15#[derive(Clone, Copy, Debug, PartialEq, Eq)]
16pub enum Gstr {
17    #[doc = "0: Fault input glitch stretching is disabled."]
18    Disabled = 0,
19    #[doc = "1: Input fault signals are stretched to at least 2 IPBus clock cycles."]
20    Enabled = 1,
21}
22impl From<Gstr> for bool {
23    #[inline(always)]
24    fn from(variant: Gstr) -> Self {
25        variant as u8 != 0
26    }
27}
28#[doc = "Field `GSTR` reader - Fault Glitch Stretch Enable"]
29pub type GstrR = crate::BitReader<Gstr>;
30impl GstrR {
31    #[doc = "Get enumerated values variant"]
32    #[inline(always)]
33    pub const fn variant(&self) -> Gstr {
34        match self.bits {
35            false => Gstr::Disabled,
36            true => Gstr::Enabled,
37        }
38    }
39    #[doc = "Fault input glitch stretching is disabled."]
40    #[inline(always)]
41    pub fn is_disabled(&self) -> bool {
42        *self == Gstr::Disabled
43    }
44    #[doc = "Input fault signals are stretched to at least 2 IPBus clock cycles."]
45    #[inline(always)]
46    pub fn is_enabled(&self) -> bool {
47        *self == Gstr::Enabled
48    }
49}
50#[doc = "Field `GSTR` writer - Fault Glitch Stretch Enable"]
51pub type GstrW<'a, REG> = crate::BitWriter<'a, REG, Gstr>;
52impl<'a, REG> GstrW<'a, REG>
53where
54    REG: crate::Writable + crate::RegisterSpec,
55{
56    #[doc = "Fault input glitch stretching is disabled."]
57    #[inline(always)]
58    pub fn disabled(self) -> &'a mut crate::W<REG> {
59        self.variant(Gstr::Disabled)
60    }
61    #[doc = "Input fault signals are stretched to at least 2 IPBus clock cycles."]
62    #[inline(always)]
63    pub fn enabled(self) -> &'a mut crate::W<REG> {
64        self.variant(Gstr::Enabled)
65    }
66}
67impl R {
68    #[doc = "Bits 0:7 - Fault Filter Period"]
69    #[inline(always)]
70    pub fn filt_per(&self) -> FiltPerR {
71        FiltPerR::new((self.bits & 0xff) as u8)
72    }
73    #[doc = "Bits 8:10 - Fault Filter Count"]
74    #[inline(always)]
75    pub fn filt_cnt(&self) -> FiltCntR {
76        FiltCntR::new(((self.bits >> 8) & 7) as u8)
77    }
78    #[doc = "Bit 15 - Fault Glitch Stretch Enable"]
79    #[inline(always)]
80    pub fn gstr(&self) -> GstrR {
81        GstrR::new(((self.bits >> 15) & 1) != 0)
82    }
83}
84#[cfg(feature = "debug")]
85impl core::fmt::Debug for R {
86    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
87        f.debug_struct("FFILT0")
88            .field("filt_per", &self.filt_per())
89            .field("filt_cnt", &self.filt_cnt())
90            .field("gstr", &self.gstr())
91            .finish()
92    }
93}
94impl W {
95    #[doc = "Bits 0:7 - Fault Filter Period"]
96    #[inline(always)]
97    pub fn filt_per(&mut self) -> FiltPerW<'_, Ffilt0Spec> {
98        FiltPerW::new(self, 0)
99    }
100    #[doc = "Bits 8:10 - Fault Filter Count"]
101    #[inline(always)]
102    pub fn filt_cnt(&mut self) -> FiltCntW<'_, Ffilt0Spec> {
103        FiltCntW::new(self, 8)
104    }
105    #[doc = "Bit 15 - Fault Glitch Stretch Enable"]
106    #[inline(always)]
107    pub fn gstr(&mut self) -> GstrW<'_, Ffilt0Spec> {
108        GstrW::new(self, 15)
109    }
110}
111#[doc = "Fault Filter Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ffilt0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ffilt0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
112pub struct Ffilt0Spec;
113impl crate::RegisterSpec for Ffilt0Spec {
114    type Ux = u16;
115}
116#[doc = "`read()` method returns [`ffilt0::R`](R) reader structure"]
117impl crate::Readable for Ffilt0Spec {}
118#[doc = "`write(|w| ..)` method takes [`ffilt0::W`](W) writer structure"]
119impl crate::Writable for Ffilt0Spec {
120    type Safety = crate::Unsafe;
121}
122#[doc = "`reset()` method sets FFILT0 to value 0"]
123impl crate::Resettable for Ffilt0Spec {}
mcxa_pac/flexpwm0/ffilt0.rs

mcxa_pac/flexpwm0/
ffilt0.rs
