mcxa_pac/flexio0/
verid.rs

1#[doc = "Register `VERID` reader"]
2pub type R = crate::R<VeridSpec>;
3#[doc = "Feature Specification Number\n\nValue on reset: 3"]
4#[cfg_attr(feature = "defmt", derive(defmt::Format))]
5#[derive(Clone, Copy, Debug, PartialEq, Eq)]
6#[repr(u16)]
7pub enum Feature {
8    #[doc = "0: Standard features implemented"]
9    Standard = 0,
10    #[doc = "1: State, logic, and parallel modes supported"]
11    StateLogicParallel = 1,
12    #[doc = "2: Pin control registers supported"]
13    Pinctrl = 2,
14    #[doc = "3: State, logic, and parallel modes, plus pin control registers supported"]
15    StateLogicParallelPinctrl = 3,
16}
17impl From<Feature> for u16 {
18    #[inline(always)]
19    fn from(variant: Feature) -> Self {
20        variant as _
21    }
22}
23impl crate::FieldSpec for Feature {
24    type Ux = u16;
25}
26impl crate::IsEnum for Feature {}
27#[doc = "Field `FEATURE` reader - Feature Specification Number"]
28pub type FeatureR = crate::FieldReader<Feature>;
29impl FeatureR {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<Feature> {
33        match self.bits {
34            0 => Some(Feature::Standard),
35            1 => Some(Feature::StateLogicParallel),
36            2 => Some(Feature::Pinctrl),
37            3 => Some(Feature::StateLogicParallelPinctrl),
38            _ => None,
39        }
40    }
41    #[doc = "Standard features implemented"]
42    #[inline(always)]
43    pub fn is_standard(&self) -> bool {
44        *self == Feature::Standard
45    }
46    #[doc = "State, logic, and parallel modes supported"]
47    #[inline(always)]
48    pub fn is_state_logic_parallel(&self) -> bool {
49        *self == Feature::StateLogicParallel
50    }
51    #[doc = "Pin control registers supported"]
52    #[inline(always)]
53    pub fn is_pinctrl(&self) -> bool {
54        *self == Feature::Pinctrl
55    }
56    #[doc = "State, logic, and parallel modes, plus pin control registers supported"]
57    #[inline(always)]
58    pub fn is_state_logic_parallel_pinctrl(&self) -> bool {
59        *self == Feature::StateLogicParallelPinctrl
60    }
61}
62#[doc = "Field `MINOR` reader - Minor Version Number"]
63pub type MinorR = crate::FieldReader;
64#[doc = "Field `MAJOR` reader - Major Version Number"]
65pub type MajorR = crate::FieldReader;
66impl R {
67    #[doc = "Bits 0:15 - Feature Specification Number"]
68    #[inline(always)]
69    pub fn feature(&self) -> FeatureR {
70        FeatureR::new((self.bits & 0xffff) as u16)
71    }
72    #[doc = "Bits 16:23 - Minor Version Number"]
73    #[inline(always)]
74    pub fn minor(&self) -> MinorR {
75        MinorR::new(((self.bits >> 16) & 0xff) as u8)
76    }
77    #[doc = "Bits 24:31 - Major Version Number"]
78    #[inline(always)]
79    pub fn major(&self) -> MajorR {
80        MajorR::new(((self.bits >> 24) & 0xff) as u8)
81    }
82}
83#[cfg(feature = "debug")]
84impl core::fmt::Debug for R {
85    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
86        f.debug_struct("VERID")
87            .field("feature", &self.feature())
88            .field("minor", &self.minor())
89            .field("major", &self.major())
90            .finish()
91    }
92}
93#[doc = "Version ID\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
94pub struct VeridSpec;
95impl crate::RegisterSpec for VeridSpec {
96    type Ux = u32;
97}
98#[doc = "`read()` method returns [`verid::R`](R) reader structure"]
99impl crate::Readable for VeridSpec {}
100#[doc = "`reset()` method sets VERID to value 0x0201_0003"]
101impl crate::Resettable for VeridSpec {
102    const RESET_VALUE: u32 = 0x0201_0003;
103}
mcxa_pac/flexio0/verid.rs

mcxa_pac/flexio0/
verid.rs
