mcxa_pac/flexio0/
timcfg.rs

1#[doc = "Register `TIMCFG[%s]` reader"]
2pub type R = crate::R<TimcfgSpec>;
3#[doc = "Register `TIMCFG[%s]` writer"]
4pub type W = crate::W<TimcfgSpec>;
5#[doc = "Timer Start\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Tstart {
9    #[doc = "0: Disabled"]
10    Disable = 0,
11    #[doc = "1: Enabled"]
12    Enable = 1,
13}
14impl From<Tstart> for bool {
15    #[inline(always)]
16    fn from(variant: Tstart) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `TSTART` reader - Timer Start"]
21pub type TstartR = crate::BitReader<Tstart>;
22impl TstartR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Tstart {
26        match self.bits {
27            false => Tstart::Disable,
28            true => Tstart::Enable,
29        }
30    }
31    #[doc = "Disabled"]
32    #[inline(always)]
33    pub fn is_disable(&self) -> bool {
34        *self == Tstart::Disable
35    }
36    #[doc = "Enabled"]
37    #[inline(always)]
38    pub fn is_enable(&self) -> bool {
39        *self == Tstart::Enable
40    }
41}
42#[doc = "Field `TSTART` writer - Timer Start"]
43pub type TstartW<'a, REG> = crate::BitWriter<'a, REG, Tstart>;
44impl<'a, REG> TstartW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Disabled"]
49    #[inline(always)]
50    pub fn disable(self) -> &'a mut crate::W<REG> {
51        self.variant(Tstart::Disable)
52    }
53    #[doc = "Enabled"]
54    #[inline(always)]
55    pub fn enable(self) -> &'a mut crate::W<REG> {
56        self.variant(Tstart::Enable)
57    }
58}
59#[doc = "Timer Stop\n\nValue on reset: 0"]
60#[cfg_attr(feature = "defmt", derive(defmt::Format))]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62#[repr(u8)]
63pub enum Tstop {
64    #[doc = "0: Disabled"]
65    StopDisable = 0,
66    #[doc = "1: Enabled on timer compare"]
67    EnableTmrcmp = 1,
68    #[doc = "2: Enabled on timer disable"]
69    EnableTmrdisable = 2,
70    #[doc = "3: Enabled on timer compare and timer disable"]
71    EnableTmrCmpDis = 3,
72}
73impl From<Tstop> for u8 {
74    #[inline(always)]
75    fn from(variant: Tstop) -> Self {
76        variant as _
77    }
78}
79impl crate::FieldSpec for Tstop {
80    type Ux = u8;
81}
82impl crate::IsEnum for Tstop {}
83#[doc = "Field `TSTOP` reader - Timer Stop"]
84pub type TstopR = crate::FieldReader<Tstop>;
85impl TstopR {
86    #[doc = "Get enumerated values variant"]
87    #[inline(always)]
88    pub const fn variant(&self) -> Tstop {
89        match self.bits {
90            0 => Tstop::StopDisable,
91            1 => Tstop::EnableTmrcmp,
92            2 => Tstop::EnableTmrdisable,
93            3 => Tstop::EnableTmrCmpDis,
94            _ => unreachable!(),
95        }
96    }
97    #[doc = "Disabled"]
98    #[inline(always)]
99    pub fn is_stop_disable(&self) -> bool {
100        *self == Tstop::StopDisable
101    }
102    #[doc = "Enabled on timer compare"]
103    #[inline(always)]
104    pub fn is_enable_tmrcmp(&self) -> bool {
105        *self == Tstop::EnableTmrcmp
106    }
107    #[doc = "Enabled on timer disable"]
108    #[inline(always)]
109    pub fn is_enable_tmrdisable(&self) -> bool {
110        *self == Tstop::EnableTmrdisable
111    }
112    #[doc = "Enabled on timer compare and timer disable"]
113    #[inline(always)]
114    pub fn is_enable_tmr_cmp_dis(&self) -> bool {
115        *self == Tstop::EnableTmrCmpDis
116    }
117}
118#[doc = "Field `TSTOP` writer - Timer Stop"]
119pub type TstopW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tstop, crate::Safe>;
120impl<'a, REG> TstopW<'a, REG>
121where
122    REG: crate::Writable + crate::RegisterSpec,
123    REG::Ux: From<u8>,
124{
125    #[doc = "Disabled"]
126    #[inline(always)]
127    pub fn stop_disable(self) -> &'a mut crate::W<REG> {
128        self.variant(Tstop::StopDisable)
129    }
130    #[doc = "Enabled on timer compare"]
131    #[inline(always)]
132    pub fn enable_tmrcmp(self) -> &'a mut crate::W<REG> {
133        self.variant(Tstop::EnableTmrcmp)
134    }
135    #[doc = "Enabled on timer disable"]
136    #[inline(always)]
137    pub fn enable_tmrdisable(self) -> &'a mut crate::W<REG> {
138        self.variant(Tstop::EnableTmrdisable)
139    }
140    #[doc = "Enabled on timer compare and timer disable"]
141    #[inline(always)]
142    pub fn enable_tmr_cmp_dis(self) -> &'a mut crate::W<REG> {
143        self.variant(Tstop::EnableTmrCmpDis)
144    }
145}
146#[doc = "Timer Enable\n\nValue on reset: 0"]
147#[cfg_attr(feature = "defmt", derive(defmt::Format))]
148#[derive(Clone, Copy, Debug, PartialEq, Eq)]
149#[repr(u8)]
150pub enum Timena {
151    #[doc = "0: Timer always enabled"]
152    Enable = 0,
153    #[doc = "1: Timer enabled on timer n-1 enable"]
154    TmrNminus1En = 1,
155    #[doc = "2: Timer enabled on trigger high"]
156    TmrTrighiEn = 2,
157    #[doc = "3: Timer enabled on trigger high and pin high"]
158    TmrTrigPinHiEn = 3,
159    #[doc = "4: Timer enabled on pin rising edge"]
160    TmrPinriseEn = 4,
161    #[doc = "5: Timer enabled on pin rising edge and trigger high"]
162    TmrPinriseTrighiEn = 5,
163    #[doc = "6: Timer enabled on trigger rising edge"]
164    TmrTrigriseEn = 6,
165    #[doc = "7: Timer enabled on trigger rising or falling edge"]
166    TmrTrigedgeEn = 7,
167}
168impl From<Timena> for u8 {
169    #[inline(always)]
170    fn from(variant: Timena) -> Self {
171        variant as _
172    }
173}
174impl crate::FieldSpec for Timena {
175    type Ux = u8;
176}
177impl crate::IsEnum for Timena {}
178#[doc = "Field `TIMENA` reader - Timer Enable"]
179pub type TimenaR = crate::FieldReader<Timena>;
180impl TimenaR {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> Timena {
184        match self.bits {
185            0 => Timena::Enable,
186            1 => Timena::TmrNminus1En,
187            2 => Timena::TmrTrighiEn,
188            3 => Timena::TmrTrigPinHiEn,
189            4 => Timena::TmrPinriseEn,
190            5 => Timena::TmrPinriseTrighiEn,
191            6 => Timena::TmrTrigriseEn,
192            7 => Timena::TmrTrigedgeEn,
193            _ => unreachable!(),
194        }
195    }
196    #[doc = "Timer always enabled"]
197    #[inline(always)]
198    pub fn is_enable(&self) -> bool {
199        *self == Timena::Enable
200    }
201    #[doc = "Timer enabled on timer n-1 enable"]
202    #[inline(always)]
203    pub fn is_tmr_nminus1_en(&self) -> bool {
204        *self == Timena::TmrNminus1En
205    }
206    #[doc = "Timer enabled on trigger high"]
207    #[inline(always)]
208    pub fn is_tmr_trighi_en(&self) -> bool {
209        *self == Timena::TmrTrighiEn
210    }
211    #[doc = "Timer enabled on trigger high and pin high"]
212    #[inline(always)]
213    pub fn is_tmr_trig_pin_hi_en(&self) -> bool {
214        *self == Timena::TmrTrigPinHiEn
215    }
216    #[doc = "Timer enabled on pin rising edge"]
217    #[inline(always)]
218    pub fn is_tmr_pinrise_en(&self) -> bool {
219        *self == Timena::TmrPinriseEn
220    }
221    #[doc = "Timer enabled on pin rising edge and trigger high"]
222    #[inline(always)]
223    pub fn is_tmr_pinrise_trighi_en(&self) -> bool {
224        *self == Timena::TmrPinriseTrighiEn
225    }
226    #[doc = "Timer enabled on trigger rising edge"]
227    #[inline(always)]
228    pub fn is_tmr_trigrise_en(&self) -> bool {
229        *self == Timena::TmrTrigriseEn
230    }
231    #[doc = "Timer enabled on trigger rising or falling edge"]
232    #[inline(always)]
233    pub fn is_tmr_trigedge_en(&self) -> bool {
234        *self == Timena::TmrTrigedgeEn
235    }
236}
237#[doc = "Field `TIMENA` writer - Timer Enable"]
238pub type TimenaW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timena, crate::Safe>;
239impl<'a, REG> TimenaW<'a, REG>
240where
241    REG: crate::Writable + crate::RegisterSpec,
242    REG::Ux: From<u8>,
243{
244    #[doc = "Timer always enabled"]
245    #[inline(always)]
246    pub fn enable(self) -> &'a mut crate::W<REG> {
247        self.variant(Timena::Enable)
248    }
249    #[doc = "Timer enabled on timer n-1 enable"]
250    #[inline(always)]
251    pub fn tmr_nminus1_en(self) -> &'a mut crate::W<REG> {
252        self.variant(Timena::TmrNminus1En)
253    }
254    #[doc = "Timer enabled on trigger high"]
255    #[inline(always)]
256    pub fn tmr_trighi_en(self) -> &'a mut crate::W<REG> {
257        self.variant(Timena::TmrTrighiEn)
258    }
259    #[doc = "Timer enabled on trigger high and pin high"]
260    #[inline(always)]
261    pub fn tmr_trig_pin_hi_en(self) -> &'a mut crate::W<REG> {
262        self.variant(Timena::TmrTrigPinHiEn)
263    }
264    #[doc = "Timer enabled on pin rising edge"]
265    #[inline(always)]
266    pub fn tmr_pinrise_en(self) -> &'a mut crate::W<REG> {
267        self.variant(Timena::TmrPinriseEn)
268    }
269    #[doc = "Timer enabled on pin rising edge and trigger high"]
270    #[inline(always)]
271    pub fn tmr_pinrise_trighi_en(self) -> &'a mut crate::W<REG> {
272        self.variant(Timena::TmrPinriseTrighiEn)
273    }
274    #[doc = "Timer enabled on trigger rising edge"]
275    #[inline(always)]
276    pub fn tmr_trigrise_en(self) -> &'a mut crate::W<REG> {
277        self.variant(Timena::TmrTrigriseEn)
278    }
279    #[doc = "Timer enabled on trigger rising or falling edge"]
280    #[inline(always)]
281    pub fn tmr_trigedge_en(self) -> &'a mut crate::W<REG> {
282        self.variant(Timena::TmrTrigedgeEn)
283    }
284}
285#[doc = "Timer Disable\n\nValue on reset: 0"]
286#[cfg_attr(feature = "defmt", derive(defmt::Format))]
287#[derive(Clone, Copy, Debug, PartialEq, Eq)]
288#[repr(u8)]
289pub enum Timdis {
290    #[doc = "0: Timer never disabled"]
291    Never = 0,
292    #[doc = "1: Timer disabled on timer n-1 disable"]
293    TmrNminus1 = 1,
294    #[doc = "2: Timer disabled on timer compare (upper 8 bits match and decrement)"]
295    TmrCmp = 2,
296    #[doc = "3: Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low"]
297    TmrCmpTriglow = 3,
298    #[doc = "4: Timer disabled on pin rising or falling edge"]
299    PinEdge = 4,
300    #[doc = "5: Timer disabled on pin rising or falling edge provided trigger is high"]
301    PinEdgeTrighi = 5,
302    #[doc = "6: Timer disabled on trigger falling edge"]
303    TrigFalledge = 6,
304}
305impl From<Timdis> for u8 {
306    #[inline(always)]
307    fn from(variant: Timdis) -> Self {
308        variant as _
309    }
310}
311impl crate::FieldSpec for Timdis {
312    type Ux = u8;
313}
314impl crate::IsEnum for Timdis {}
315#[doc = "Field `TIMDIS` reader - Timer Disable"]
316pub type TimdisR = crate::FieldReader<Timdis>;
317impl TimdisR {
318    #[doc = "Get enumerated values variant"]
319    #[inline(always)]
320    pub const fn variant(&self) -> Option<Timdis> {
321        match self.bits {
322            0 => Some(Timdis::Never),
323            1 => Some(Timdis::TmrNminus1),
324            2 => Some(Timdis::TmrCmp),
325            3 => Some(Timdis::TmrCmpTriglow),
326            4 => Some(Timdis::PinEdge),
327            5 => Some(Timdis::PinEdgeTrighi),
328            6 => Some(Timdis::TrigFalledge),
329            _ => None,
330        }
331    }
332    #[doc = "Timer never disabled"]
333    #[inline(always)]
334    pub fn is_never(&self) -> bool {
335        *self == Timdis::Never
336    }
337    #[doc = "Timer disabled on timer n-1 disable"]
338    #[inline(always)]
339    pub fn is_tmr_nminus1(&self) -> bool {
340        *self == Timdis::TmrNminus1
341    }
342    #[doc = "Timer disabled on timer compare (upper 8 bits match and decrement)"]
343    #[inline(always)]
344    pub fn is_tmr_cmp(&self) -> bool {
345        *self == Timdis::TmrCmp
346    }
347    #[doc = "Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low"]
348    #[inline(always)]
349    pub fn is_tmr_cmp_triglow(&self) -> bool {
350        *self == Timdis::TmrCmpTriglow
351    }
352    #[doc = "Timer disabled on pin rising or falling edge"]
353    #[inline(always)]
354    pub fn is_pin_edge(&self) -> bool {
355        *self == Timdis::PinEdge
356    }
357    #[doc = "Timer disabled on pin rising or falling edge provided trigger is high"]
358    #[inline(always)]
359    pub fn is_pin_edge_trighi(&self) -> bool {
360        *self == Timdis::PinEdgeTrighi
361    }
362    #[doc = "Timer disabled on trigger falling edge"]
363    #[inline(always)]
364    pub fn is_trig_falledge(&self) -> bool {
365        *self == Timdis::TrigFalledge
366    }
367}
368#[doc = "Field `TIMDIS` writer - Timer Disable"]
369pub type TimdisW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timdis>;
370impl<'a, REG> TimdisW<'a, REG>
371where
372    REG: crate::Writable + crate::RegisterSpec,
373    REG::Ux: From<u8>,
374{
375    #[doc = "Timer never disabled"]
376    #[inline(always)]
377    pub fn never(self) -> &'a mut crate::W<REG> {
378        self.variant(Timdis::Never)
379    }
380    #[doc = "Timer disabled on timer n-1 disable"]
381    #[inline(always)]
382    pub fn tmr_nminus1(self) -> &'a mut crate::W<REG> {
383        self.variant(Timdis::TmrNminus1)
384    }
385    #[doc = "Timer disabled on timer compare (upper 8 bits match and decrement)"]
386    #[inline(always)]
387    pub fn tmr_cmp(self) -> &'a mut crate::W<REG> {
388        self.variant(Timdis::TmrCmp)
389    }
390    #[doc = "Timer disabled on timer compare (upper 8 bits match and decrement) and trigger low"]
391    #[inline(always)]
392    pub fn tmr_cmp_triglow(self) -> &'a mut crate::W<REG> {
393        self.variant(Timdis::TmrCmpTriglow)
394    }
395    #[doc = "Timer disabled on pin rising or falling edge"]
396    #[inline(always)]
397    pub fn pin_edge(self) -> &'a mut crate::W<REG> {
398        self.variant(Timdis::PinEdge)
399    }
400    #[doc = "Timer disabled on pin rising or falling edge provided trigger is high"]
401    #[inline(always)]
402    pub fn pin_edge_trighi(self) -> &'a mut crate::W<REG> {
403        self.variant(Timdis::PinEdgeTrighi)
404    }
405    #[doc = "Timer disabled on trigger falling edge"]
406    #[inline(always)]
407    pub fn trig_falledge(self) -> &'a mut crate::W<REG> {
408        self.variant(Timdis::TrigFalledge)
409    }
410}
411#[doc = "Timer Reset\n\nValue on reset: 0"]
412#[cfg_attr(feature = "defmt", derive(defmt::Format))]
413#[derive(Clone, Copy, Debug, PartialEq, Eq)]
414#[repr(u8)]
415pub enum Timrst {
416    #[doc = "0: Never reset timer"]
417    Never = 0,
418    #[doc = "1: Timer reset on timer output high."]
419    TmrOutHi = 1,
420    #[doc = "2: Timer reset on timer pin equal to timer output"]
421    PinEqTmrOut = 2,
422    #[doc = "3: Timer reset on timer trigger equal to timer output"]
423    TrigEqTmrOut = 3,
424    #[doc = "4: Timer reset on timer pin rising edge"]
425    PinRiseEdge = 4,
426    #[doc = "6: Timer reset on trigger rising edge"]
427    TrigRiseEdge = 6,
428    #[doc = "7: Timer reset on trigger rising or falling edge"]
429    TrigEdge = 7,
430}
431impl From<Timrst> for u8 {
432    #[inline(always)]
433    fn from(variant: Timrst) -> Self {
434        variant as _
435    }
436}
437impl crate::FieldSpec for Timrst {
438    type Ux = u8;
439}
440impl crate::IsEnum for Timrst {}
441#[doc = "Field `TIMRST` reader - Timer Reset"]
442pub type TimrstR = crate::FieldReader<Timrst>;
443impl TimrstR {
444    #[doc = "Get enumerated values variant"]
445    #[inline(always)]
446    pub const fn variant(&self) -> Option<Timrst> {
447        match self.bits {
448            0 => Some(Timrst::Never),
449            1 => Some(Timrst::TmrOutHi),
450            2 => Some(Timrst::PinEqTmrOut),
451            3 => Some(Timrst::TrigEqTmrOut),
452            4 => Some(Timrst::PinRiseEdge),
453            6 => Some(Timrst::TrigRiseEdge),
454            7 => Some(Timrst::TrigEdge),
455            _ => None,
456        }
457    }
458    #[doc = "Never reset timer"]
459    #[inline(always)]
460    pub fn is_never(&self) -> bool {
461        *self == Timrst::Never
462    }
463    #[doc = "Timer reset on timer output high."]
464    #[inline(always)]
465    pub fn is_tmr_out_hi(&self) -> bool {
466        *self == Timrst::TmrOutHi
467    }
468    #[doc = "Timer reset on timer pin equal to timer output"]
469    #[inline(always)]
470    pub fn is_pin_eq_tmr_out(&self) -> bool {
471        *self == Timrst::PinEqTmrOut
472    }
473    #[doc = "Timer reset on timer trigger equal to timer output"]
474    #[inline(always)]
475    pub fn is_trig_eq_tmr_out(&self) -> bool {
476        *self == Timrst::TrigEqTmrOut
477    }
478    #[doc = "Timer reset on timer pin rising edge"]
479    #[inline(always)]
480    pub fn is_pin_rise_edge(&self) -> bool {
481        *self == Timrst::PinRiseEdge
482    }
483    #[doc = "Timer reset on trigger rising edge"]
484    #[inline(always)]
485    pub fn is_trig_rise_edge(&self) -> bool {
486        *self == Timrst::TrigRiseEdge
487    }
488    #[doc = "Timer reset on trigger rising or falling edge"]
489    #[inline(always)]
490    pub fn is_trig_edge(&self) -> bool {
491        *self == Timrst::TrigEdge
492    }
493}
494#[doc = "Field `TIMRST` writer - Timer Reset"]
495pub type TimrstW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timrst>;
496impl<'a, REG> TimrstW<'a, REG>
497where
498    REG: crate::Writable + crate::RegisterSpec,
499    REG::Ux: From<u8>,
500{
501    #[doc = "Never reset timer"]
502    #[inline(always)]
503    pub fn never(self) -> &'a mut crate::W<REG> {
504        self.variant(Timrst::Never)
505    }
506    #[doc = "Timer reset on timer output high."]
507    #[inline(always)]
508    pub fn tmr_out_hi(self) -> &'a mut crate::W<REG> {
509        self.variant(Timrst::TmrOutHi)
510    }
511    #[doc = "Timer reset on timer pin equal to timer output"]
512    #[inline(always)]
513    pub fn pin_eq_tmr_out(self) -> &'a mut crate::W<REG> {
514        self.variant(Timrst::PinEqTmrOut)
515    }
516    #[doc = "Timer reset on timer trigger equal to timer output"]
517    #[inline(always)]
518    pub fn trig_eq_tmr_out(self) -> &'a mut crate::W<REG> {
519        self.variant(Timrst::TrigEqTmrOut)
520    }
521    #[doc = "Timer reset on timer pin rising edge"]
522    #[inline(always)]
523    pub fn pin_rise_edge(self) -> &'a mut crate::W<REG> {
524        self.variant(Timrst::PinRiseEdge)
525    }
526    #[doc = "Timer reset on trigger rising edge"]
527    #[inline(always)]
528    pub fn trig_rise_edge(self) -> &'a mut crate::W<REG> {
529        self.variant(Timrst::TrigRiseEdge)
530    }
531    #[doc = "Timer reset on trigger rising or falling edge"]
532    #[inline(always)]
533    pub fn trig_edge(self) -> &'a mut crate::W<REG> {
534        self.variant(Timrst::TrigEdge)
535    }
536}
537#[doc = "Timer Decrement\n\nValue on reset: 0"]
538#[cfg_attr(feature = "defmt", derive(defmt::Format))]
539#[derive(Clone, Copy, Debug, PartialEq, Eq)]
540#[repr(u8)]
541pub enum Timdec {
542    #[doc = "0: Decrement counter on FLEXIO clock; shift clock equals timer output"]
543    FlexioClkShiftclkTmrOut = 0,
544    #[doc = "1: Decrement counter on trigger input (both edges); shift clock equals timer output"]
545    TrigEdgeShiftclkTmrOut = 1,
546    #[doc = "2: Decrement counter on pin input (both edges); shift clock equals pin input"]
547    PinEdgeShiftclkTmrOut = 2,
548    #[doc = "3: Decrement counter on trigger input (both edges); shift clock equals trigger input"]
549    TrigEdgeShiftclkTrigIn = 3,
550    #[doc = "4: Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output"]
551    FlexioClkDiv16ShiftclkTmrOut = 4,
552    #[doc = "5: Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output"]
553    FlexioClkDiv256ShiftclkTmrOut = 5,
554    #[doc = "6: Decrement counter on pin input (rising edge); shift clock equals pin input"]
555    PinRiseShiftclkPinIn = 6,
556    #[doc = "7: Decrement counter on trigger input (rising edge); shift clock equals trigger input"]
557    TrigRiseShiftclkTrigIn = 7,
558}
559impl From<Timdec> for u8 {
560    #[inline(always)]
561    fn from(variant: Timdec) -> Self {
562        variant as _
563    }
564}
565impl crate::FieldSpec for Timdec {
566    type Ux = u8;
567}
568impl crate::IsEnum for Timdec {}
569#[doc = "Field `TIMDEC` reader - Timer Decrement"]
570pub type TimdecR = crate::FieldReader<Timdec>;
571impl TimdecR {
572    #[doc = "Get enumerated values variant"]
573    #[inline(always)]
574    pub const fn variant(&self) -> Timdec {
575        match self.bits {
576            0 => Timdec::FlexioClkShiftclkTmrOut,
577            1 => Timdec::TrigEdgeShiftclkTmrOut,
578            2 => Timdec::PinEdgeShiftclkTmrOut,
579            3 => Timdec::TrigEdgeShiftclkTrigIn,
580            4 => Timdec::FlexioClkDiv16ShiftclkTmrOut,
581            5 => Timdec::FlexioClkDiv256ShiftclkTmrOut,
582            6 => Timdec::PinRiseShiftclkPinIn,
583            7 => Timdec::TrigRiseShiftclkTrigIn,
584            _ => unreachable!(),
585        }
586    }
587    #[doc = "Decrement counter on FLEXIO clock; shift clock equals timer output"]
588    #[inline(always)]
589    pub fn is_flexio_clk_shiftclk_tmr_out(&self) -> bool {
590        *self == Timdec::FlexioClkShiftclkTmrOut
591    }
592    #[doc = "Decrement counter on trigger input (both edges); shift clock equals timer output"]
593    #[inline(always)]
594    pub fn is_trig_edge_shiftclk_tmr_out(&self) -> bool {
595        *self == Timdec::TrigEdgeShiftclkTmrOut
596    }
597    #[doc = "Decrement counter on pin input (both edges); shift clock equals pin input"]
598    #[inline(always)]
599    pub fn is_pin_edge_shiftclk_tmr_out(&self) -> bool {
600        *self == Timdec::PinEdgeShiftclkTmrOut
601    }
602    #[doc = "Decrement counter on trigger input (both edges); shift clock equals trigger input"]
603    #[inline(always)]
604    pub fn is_trig_edge_shiftclk_trig_in(&self) -> bool {
605        *self == Timdec::TrigEdgeShiftclkTrigIn
606    }
607    #[doc = "Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output"]
608    #[inline(always)]
609    pub fn is_flexio_clk_div16_shiftclk_tmr_out(&self) -> bool {
610        *self == Timdec::FlexioClkDiv16ShiftclkTmrOut
611    }
612    #[doc = "Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output"]
613    #[inline(always)]
614    pub fn is_flexio_clk_div256_shiftclk_tmr_out(&self) -> bool {
615        *self == Timdec::FlexioClkDiv256ShiftclkTmrOut
616    }
617    #[doc = "Decrement counter on pin input (rising edge); shift clock equals pin input"]
618    #[inline(always)]
619    pub fn is_pin_rise_shiftclk_pin_in(&self) -> bool {
620        *self == Timdec::PinRiseShiftclkPinIn
621    }
622    #[doc = "Decrement counter on trigger input (rising edge); shift clock equals trigger input"]
623    #[inline(always)]
624    pub fn is_trig_rise_shiftclk_trig_in(&self) -> bool {
625        *self == Timdec::TrigRiseShiftclkTrigIn
626    }
627}
628#[doc = "Field `TIMDEC` writer - Timer Decrement"]
629pub type TimdecW<'a, REG> = crate::FieldWriter<'a, REG, 3, Timdec, crate::Safe>;
630impl<'a, REG> TimdecW<'a, REG>
631where
632    REG: crate::Writable + crate::RegisterSpec,
633    REG::Ux: From<u8>,
634{
635    #[doc = "Decrement counter on FLEXIO clock; shift clock equals timer output"]
636    #[inline(always)]
637    pub fn flexio_clk_shiftclk_tmr_out(self) -> &'a mut crate::W<REG> {
638        self.variant(Timdec::FlexioClkShiftclkTmrOut)
639    }
640    #[doc = "Decrement counter on trigger input (both edges); shift clock equals timer output"]
641    #[inline(always)]
642    pub fn trig_edge_shiftclk_tmr_out(self) -> &'a mut crate::W<REG> {
643        self.variant(Timdec::TrigEdgeShiftclkTmrOut)
644    }
645    #[doc = "Decrement counter on pin input (both edges); shift clock equals pin input"]
646    #[inline(always)]
647    pub fn pin_edge_shiftclk_tmr_out(self) -> &'a mut crate::W<REG> {
648        self.variant(Timdec::PinEdgeShiftclkTmrOut)
649    }
650    #[doc = "Decrement counter on trigger input (both edges); shift clock equals trigger input"]
651    #[inline(always)]
652    pub fn trig_edge_shiftclk_trig_in(self) -> &'a mut crate::W<REG> {
653        self.variant(Timdec::TrigEdgeShiftclkTrigIn)
654    }
655    #[doc = "Decrement counter on FLEXIO clock divided by 16; shift clock equals timer output"]
656    #[inline(always)]
657    pub fn flexio_clk_div16_shiftclk_tmr_out(self) -> &'a mut crate::W<REG> {
658        self.variant(Timdec::FlexioClkDiv16ShiftclkTmrOut)
659    }
660    #[doc = "Decrement counter on FLEXIO clock divided by 256; shift clock equals timer output"]
661    #[inline(always)]
662    pub fn flexio_clk_div256_shiftclk_tmr_out(self) -> &'a mut crate::W<REG> {
663        self.variant(Timdec::FlexioClkDiv256ShiftclkTmrOut)
664    }
665    #[doc = "Decrement counter on pin input (rising edge); shift clock equals pin input"]
666    #[inline(always)]
667    pub fn pin_rise_shiftclk_pin_in(self) -> &'a mut crate::W<REG> {
668        self.variant(Timdec::PinRiseShiftclkPinIn)
669    }
670    #[doc = "Decrement counter on trigger input (rising edge); shift clock equals trigger input"]
671    #[inline(always)]
672    pub fn trig_rise_shiftclk_trig_in(self) -> &'a mut crate::W<REG> {
673        self.variant(Timdec::TrigRiseShiftclkTrigIn)
674    }
675}
676#[doc = "Timer Output\n\nValue on reset: 0"]
677#[cfg_attr(feature = "defmt", derive(defmt::Format))]
678#[derive(Clone, Copy, Debug, PartialEq, Eq)]
679#[repr(u8)]
680pub enum Timout {
681    #[doc = "0: Logic one when enabled; not affected by timer reset"]
682    One = 0,
683    #[doc = "1: Logic zero when enabled; not affected by timer reset"]
684    Zero = 1,
685    #[doc = "2: Logic one when enabled and on timer reset"]
686    OneTmrreset = 2,
687    #[doc = "3: Logic zero when enabled and on timer reset"]
688    ZeroTmrreset = 3,
689}
690impl From<Timout> for u8 {
691    #[inline(always)]
692    fn from(variant: Timout) -> Self {
693        variant as _
694    }
695}
696impl crate::FieldSpec for Timout {
697    type Ux = u8;
698}
699impl crate::IsEnum for Timout {}
700#[doc = "Field `TIMOUT` reader - Timer Output"]
701pub type TimoutR = crate::FieldReader<Timout>;
702impl TimoutR {
703    #[doc = "Get enumerated values variant"]
704    #[inline(always)]
705    pub const fn variant(&self) -> Timout {
706        match self.bits {
707            0 => Timout::One,
708            1 => Timout::Zero,
709            2 => Timout::OneTmrreset,
710            3 => Timout::ZeroTmrreset,
711            _ => unreachable!(),
712        }
713    }
714    #[doc = "Logic one when enabled; not affected by timer reset"]
715    #[inline(always)]
716    pub fn is_one(&self) -> bool {
717        *self == Timout::One
718    }
719    #[doc = "Logic zero when enabled; not affected by timer reset"]
720    #[inline(always)]
721    pub fn is_zero(&self) -> bool {
722        *self == Timout::Zero
723    }
724    #[doc = "Logic one when enabled and on timer reset"]
725    #[inline(always)]
726    pub fn is_one_tmrreset(&self) -> bool {
727        *self == Timout::OneTmrreset
728    }
729    #[doc = "Logic zero when enabled and on timer reset"]
730    #[inline(always)]
731    pub fn is_zero_tmrreset(&self) -> bool {
732        *self == Timout::ZeroTmrreset
733    }
734}
735#[doc = "Field `TIMOUT` writer - Timer Output"]
736pub type TimoutW<'a, REG> = crate::FieldWriter<'a, REG, 2, Timout, crate::Safe>;
737impl<'a, REG> TimoutW<'a, REG>
738where
739    REG: crate::Writable + crate::RegisterSpec,
740    REG::Ux: From<u8>,
741{
742    #[doc = "Logic one when enabled; not affected by timer reset"]
743    #[inline(always)]
744    pub fn one(self) -> &'a mut crate::W<REG> {
745        self.variant(Timout::One)
746    }
747    #[doc = "Logic zero when enabled; not affected by timer reset"]
748    #[inline(always)]
749    pub fn zero(self) -> &'a mut crate::W<REG> {
750        self.variant(Timout::Zero)
751    }
752    #[doc = "Logic one when enabled and on timer reset"]
753    #[inline(always)]
754    pub fn one_tmrreset(self) -> &'a mut crate::W<REG> {
755        self.variant(Timout::OneTmrreset)
756    }
757    #[doc = "Logic zero when enabled and on timer reset"]
758    #[inline(always)]
759    pub fn zero_tmrreset(self) -> &'a mut crate::W<REG> {
760        self.variant(Timout::ZeroTmrreset)
761    }
762}
763impl R {
764    #[doc = "Bit 1 - Timer Start"]
765    #[inline(always)]
766    pub fn tstart(&self) -> TstartR {
767        TstartR::new(((self.bits >> 1) & 1) != 0)
768    }
769    #[doc = "Bits 4:5 - Timer Stop"]
770    #[inline(always)]
771    pub fn tstop(&self) -> TstopR {
772        TstopR::new(((self.bits >> 4) & 3) as u8)
773    }
774    #[doc = "Bits 8:10 - Timer Enable"]
775    #[inline(always)]
776    pub fn timena(&self) -> TimenaR {
777        TimenaR::new(((self.bits >> 8) & 7) as u8)
778    }
779    #[doc = "Bits 12:14 - Timer Disable"]
780    #[inline(always)]
781    pub fn timdis(&self) -> TimdisR {
782        TimdisR::new(((self.bits >> 12) & 7) as u8)
783    }
784    #[doc = "Bits 16:18 - Timer Reset"]
785    #[inline(always)]
786    pub fn timrst(&self) -> TimrstR {
787        TimrstR::new(((self.bits >> 16) & 7) as u8)
788    }
789    #[doc = "Bits 20:22 - Timer Decrement"]
790    #[inline(always)]
791    pub fn timdec(&self) -> TimdecR {
792        TimdecR::new(((self.bits >> 20) & 7) as u8)
793    }
794    #[doc = "Bits 24:25 - Timer Output"]
795    #[inline(always)]
796    pub fn timout(&self) -> TimoutR {
797        TimoutR::new(((self.bits >> 24) & 3) as u8)
798    }
799}
800#[cfg(feature = "debug")]
801impl core::fmt::Debug for R {
802    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
803        f.debug_struct("TIMCFG")
804            .field("tstart", &self.tstart())
805            .field("tstop", &self.tstop())
806            .field("timena", &self.timena())
807            .field("timdis", &self.timdis())
808            .field("timrst", &self.timrst())
809            .field("timdec", &self.timdec())
810            .field("timout", &self.timout())
811            .finish()
812    }
813}
814impl W {
815    #[doc = "Bit 1 - Timer Start"]
816    #[inline(always)]
817    pub fn tstart(&mut self) -> TstartW<'_, TimcfgSpec> {
818        TstartW::new(self, 1)
819    }
820    #[doc = "Bits 4:5 - Timer Stop"]
821    #[inline(always)]
822    pub fn tstop(&mut self) -> TstopW<'_, TimcfgSpec> {
823        TstopW::new(self, 4)
824    }
825    #[doc = "Bits 8:10 - Timer Enable"]
826    #[inline(always)]
827    pub fn timena(&mut self) -> TimenaW<'_, TimcfgSpec> {
828        TimenaW::new(self, 8)
829    }
830    #[doc = "Bits 12:14 - Timer Disable"]
831    #[inline(always)]
832    pub fn timdis(&mut self) -> TimdisW<'_, TimcfgSpec> {
833        TimdisW::new(self, 12)
834    }
835    #[doc = "Bits 16:18 - Timer Reset"]
836    #[inline(always)]
837    pub fn timrst(&mut self) -> TimrstW<'_, TimcfgSpec> {
838        TimrstW::new(self, 16)
839    }
840    #[doc = "Bits 20:22 - Timer Decrement"]
841    #[inline(always)]
842    pub fn timdec(&mut self) -> TimdecW<'_, TimcfgSpec> {
843        TimdecW::new(self, 20)
844    }
845    #[doc = "Bits 24:25 - Timer Output"]
846    #[inline(always)]
847    pub fn timout(&mut self) -> TimoutW<'_, TimcfgSpec> {
848        TimoutW::new(self, 24)
849    }
850}
851#[doc = "Timer Configuration\n\nYou can [`read`](crate::Reg::read) this register and get [`timcfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`timcfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
852pub struct TimcfgSpec;
853impl crate::RegisterSpec for TimcfgSpec {
854    type Ux = u32;
855}
856#[doc = "`read()` method returns [`timcfg::R`](R) reader structure"]
857impl crate::Readable for TimcfgSpec {}
858#[doc = "`write(|w| ..)` method takes [`timcfg::W`](W) writer structure"]
859impl crate::Writable for TimcfgSpec {
860    type Safety = crate::Unsafe;
861}
862#[doc = "`reset()` method sets TIMCFG[%s] to value 0"]
863impl crate::Resettable for TimcfgSpec {}
mcxa_pac/flexio0/timcfg.rs

mcxa_pac/flexio0/
timcfg.rs
