mcxa_pac/flexio0/
shiftsien.rs

1#[doc = "Register `SHIFTSIEN` reader"]
2pub type R = crate::R<ShiftsienSpec>;
3#[doc = "Register `SHIFTSIEN` writer"]
4pub type W = crate::W<ShiftsienSpec>;
5#[doc = "Field `SSIE` reader - Shifter Status Interrupt Enable"]
6pub type SsieR = crate::FieldReader;
7#[doc = "Field `SSIE` writer - Shifter Status Interrupt Enable"]
8pub type SsieW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9impl R {
10    #[doc = "Bits 0:3 - Shifter Status Interrupt Enable"]
11    #[inline(always)]
12    pub fn ssie(&self) -> SsieR {
13        SsieR::new((self.bits & 0x0f) as u8)
14    }
15}
16#[cfg(feature = "debug")]
17impl core::fmt::Debug for R {
18    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19        f.debug_struct("SHIFTSIEN").field("ssie", &self.ssie()).finish()
20    }
21}
22impl W {
23    #[doc = "Bits 0:3 - Shifter Status Interrupt Enable"]
24    #[inline(always)]
25    pub fn ssie(&mut self) -> SsieW<'_, ShiftsienSpec> {
26        SsieW::new(self, 0)
27    }
28}
29#[doc = "Shifter Status Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`shiftsien::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`shiftsien::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
30pub struct ShiftsienSpec;
31impl crate::RegisterSpec for ShiftsienSpec {
32    type Ux = u32;
33}
34#[doc = "`read()` method returns [`shiftsien::R`](R) reader structure"]
35impl crate::Readable for ShiftsienSpec {}
36#[doc = "`write(|w| ..)` method takes [`shiftsien::W`](W) writer structure"]
37impl crate::Writable for ShiftsienSpec {
38    type Safety = crate::Unsafe;
39}
40#[doc = "`reset()` method sets SHIFTSIEN to value 0"]
41impl crate::Resettable for ShiftsienSpec {}
mcxa_pac/flexio0/shiftsien.rs

mcxa_pac/flexio0/
shiftsien.rs
