mcxa_pac/edma_0_tcd0/tcd/
tcd_attr.rs

1#[doc = "Register `TCD_ATTR` reader"]
2pub type R = crate::R<TcdAttrSpec>;
3#[doc = "Register `TCD_ATTR` writer"]
4pub type W = crate::W<TcdAttrSpec>;
5#[doc = "Field `DSIZE` reader - Destination Data Transfer Size"]
6pub type DsizeR = crate::FieldReader;
7#[doc = "Field `DSIZE` writer - Destination Data Transfer Size"]
8pub type DsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `DMOD` reader - Destination Address Modulo"]
10pub type DmodR = crate::FieldReader;
11#[doc = "Field `DMOD` writer - Destination Address Modulo"]
12pub type DmodW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Source Data Transfer Size\n\nValue on reset: 0"]
14#[cfg_attr(feature = "defmt", derive(defmt::Format))]
15#[derive(Clone, Copy, Debug, PartialEq, Eq)]
16#[repr(u8)]
17pub enum Ssize {
18    #[doc = "0: 8-bit"]
19    EightBit = 0,
20    #[doc = "1: 16-bit"]
21    SixteenBit = 1,
22    #[doc = "2: 32-bit"]
23    ThirtytwoBit = 2,
24    #[doc = "3: 64-bit"]
25    SixtyfourBit = 3,
26    #[doc = "4: 16-byte"]
27    SixteenByte = 4,
28    #[doc = "5: 32-byte"]
29    ThirtytwoByte = 5,
30}
31impl From<Ssize> for u8 {
32    #[inline(always)]
33    fn from(variant: Ssize) -> Self {
34        variant as _
35    }
36}
37impl crate::FieldSpec for Ssize {
38    type Ux = u8;
39}
40impl crate::IsEnum for Ssize {}
41#[doc = "Field `SSIZE` reader - Source Data Transfer Size"]
42pub type SsizeR = crate::FieldReader<Ssize>;
43impl SsizeR {
44    #[doc = "Get enumerated values variant"]
45    #[inline(always)]
46    pub const fn variant(&self) -> Option<Ssize> {
47        match self.bits {
48            0 => Some(Ssize::EightBit),
49            1 => Some(Ssize::SixteenBit),
50            2 => Some(Ssize::ThirtytwoBit),
51            3 => Some(Ssize::SixtyfourBit),
52            4 => Some(Ssize::SixteenByte),
53            5 => Some(Ssize::ThirtytwoByte),
54            _ => None,
55        }
56    }
57    #[doc = "8-bit"]
58    #[inline(always)]
59    pub fn is_eight_bit(&self) -> bool {
60        *self == Ssize::EightBit
61    }
62    #[doc = "16-bit"]
63    #[inline(always)]
64    pub fn is_sixteen_bit(&self) -> bool {
65        *self == Ssize::SixteenBit
66    }
67    #[doc = "32-bit"]
68    #[inline(always)]
69    pub fn is_thirtytwo_bit(&self) -> bool {
70        *self == Ssize::ThirtytwoBit
71    }
72    #[doc = "64-bit"]
73    #[inline(always)]
74    pub fn is_sixtyfour_bit(&self) -> bool {
75        *self == Ssize::SixtyfourBit
76    }
77    #[doc = "16-byte"]
78    #[inline(always)]
79    pub fn is_sixteen_byte(&self) -> bool {
80        *self == Ssize::SixteenByte
81    }
82    #[doc = "32-byte"]
83    #[inline(always)]
84    pub fn is_thirtytwo_byte(&self) -> bool {
85        *self == Ssize::ThirtytwoByte
86    }
87}
88#[doc = "Field `SSIZE` writer - Source Data Transfer Size"]
89pub type SsizeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Ssize>;
90impl<'a, REG> SsizeW<'a, REG>
91where
92    REG: crate::Writable + crate::RegisterSpec,
93    REG::Ux: From<u8>,
94{
95    #[doc = "8-bit"]
96    #[inline(always)]
97    pub fn eight_bit(self) -> &'a mut crate::W<REG> {
98        self.variant(Ssize::EightBit)
99    }
100    #[doc = "16-bit"]
101    #[inline(always)]
102    pub fn sixteen_bit(self) -> &'a mut crate::W<REG> {
103        self.variant(Ssize::SixteenBit)
104    }
105    #[doc = "32-bit"]
106    #[inline(always)]
107    pub fn thirtytwo_bit(self) -> &'a mut crate::W<REG> {
108        self.variant(Ssize::ThirtytwoBit)
109    }
110    #[doc = "64-bit"]
111    #[inline(always)]
112    pub fn sixtyfour_bit(self) -> &'a mut crate::W<REG> {
113        self.variant(Ssize::SixtyfourBit)
114    }
115    #[doc = "16-byte"]
116    #[inline(always)]
117    pub fn sixteen_byte(self) -> &'a mut crate::W<REG> {
118        self.variant(Ssize::SixteenByte)
119    }
120    #[doc = "32-byte"]
121    #[inline(always)]
122    pub fn thirtytwo_byte(self) -> &'a mut crate::W<REG> {
123        self.variant(Ssize::ThirtytwoByte)
124    }
125}
126#[doc = "Source Address Modulo\n\nValue on reset: 0"]
127#[cfg_attr(feature = "defmt", derive(defmt::Format))]
128#[derive(Clone, Copy, Debug, PartialEq, Eq)]
129#[repr(u8)]
130pub enum Smod {
131    #[doc = "0: Source address modulo feature disabled"]
132    Disable = 0,
133    #[doc = "1: Source address modulo feature enabled for any non-zero value \\[1-31\\]"]
134    Enable = 1,
135}
136impl From<Smod> for u8 {
137    #[inline(always)]
138    fn from(variant: Smod) -> Self {
139        variant as _
140    }
141}
142impl crate::FieldSpec for Smod {
143    type Ux = u8;
144}
145impl crate::IsEnum for Smod {}
146#[doc = "Field `SMOD` reader - Source Address Modulo"]
147pub type SmodR = crate::FieldReader<Smod>;
148impl SmodR {
149    #[doc = "Get enumerated values variant"]
150    #[inline(always)]
151    pub const fn variant(&self) -> Option<Smod> {
152        match self.bits {
153            0 => Some(Smod::Disable),
154            1 => Some(Smod::Enable),
155            _ => None,
156        }
157    }
158    #[doc = "Source address modulo feature disabled"]
159    #[inline(always)]
160    pub fn is_disable(&self) -> bool {
161        *self == Smod::Disable
162    }
163    #[doc = "Source address modulo feature enabled for any non-zero value \\[1-31\\]"]
164    #[inline(always)]
165    pub fn is_enable(&self) -> bool {
166        *self == Smod::Enable
167    }
168}
169#[doc = "Field `SMOD` writer - Source Address Modulo"]
170pub type SmodW<'a, REG> = crate::FieldWriter<'a, REG, 5, Smod>;
171impl<'a, REG> SmodW<'a, REG>
172where
173    REG: crate::Writable + crate::RegisterSpec,
174    REG::Ux: From<u8>,
175{
176    #[doc = "Source address modulo feature disabled"]
177    #[inline(always)]
178    pub fn disable(self) -> &'a mut crate::W<REG> {
179        self.variant(Smod::Disable)
180    }
181    #[doc = "Source address modulo feature enabled for any non-zero value \\[1-31\\]"]
182    #[inline(always)]
183    pub fn enable(self) -> &'a mut crate::W<REG> {
184        self.variant(Smod::Enable)
185    }
186}
187impl R {
188    #[doc = "Bits 0:2 - Destination Data Transfer Size"]
189    #[inline(always)]
190    pub fn dsize(&self) -> DsizeR {
191        DsizeR::new((self.bits & 7) as u8)
192    }
193    #[doc = "Bits 3:7 - Destination Address Modulo"]
194    #[inline(always)]
195    pub fn dmod(&self) -> DmodR {
196        DmodR::new(((self.bits >> 3) & 0x1f) as u8)
197    }
198    #[doc = "Bits 8:10 - Source Data Transfer Size"]
199    #[inline(always)]
200    pub fn ssize(&self) -> SsizeR {
201        SsizeR::new(((self.bits >> 8) & 7) as u8)
202    }
203    #[doc = "Bits 11:15 - Source Address Modulo"]
204    #[inline(always)]
205    pub fn smod(&self) -> SmodR {
206        SmodR::new(((self.bits >> 11) & 0x1f) as u8)
207    }
208}
209#[cfg(feature = "debug")]
210impl core::fmt::Debug for R {
211    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
212        f.debug_struct("TCD_ATTR")
213            .field("dsize", &self.dsize())
214            .field("dmod", &self.dmod())
215            .field("ssize", &self.ssize())
216            .field("smod", &self.smod())
217            .finish()
218    }
219}
220impl W {
221    #[doc = "Bits 0:2 - Destination Data Transfer Size"]
222    #[inline(always)]
223    pub fn dsize(&mut self) -> DsizeW<'_, TcdAttrSpec> {
224        DsizeW::new(self, 0)
225    }
226    #[doc = "Bits 3:7 - Destination Address Modulo"]
227    #[inline(always)]
228    pub fn dmod(&mut self) -> DmodW<'_, TcdAttrSpec> {
229        DmodW::new(self, 3)
230    }
231    #[doc = "Bits 8:10 - Source Data Transfer Size"]
232    #[inline(always)]
233    pub fn ssize(&mut self) -> SsizeW<'_, TcdAttrSpec> {
234        SsizeW::new(self, 8)
235    }
236    #[doc = "Bits 11:15 - Source Address Modulo"]
237    #[inline(always)]
238    pub fn smod(&mut self) -> SmodW<'_, TcdAttrSpec> {
239        SmodW::new(self, 11)
240    }
241}
242#[doc = "TCD Transfer Attributes\n\nYou can [`read`](crate::Reg::read) this register and get [`tcd_attr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcd_attr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
243pub struct TcdAttrSpec;
244impl crate::RegisterSpec for TcdAttrSpec {
245    type Ux = u16;
246}
247#[doc = "`read()` method returns [`tcd_attr::R`](R) reader structure"]
248impl crate::Readable for TcdAttrSpec {}
249#[doc = "`write(|w| ..)` method takes [`tcd_attr::W`](W) writer structure"]
250impl crate::Writable for TcdAttrSpec {
251    type Safety = crate::Unsafe;
252}
253#[doc = "`reset()` method sets TCD_ATTR to value 0"]
254impl crate::Resettable for TcdAttrSpec {}
mcxa_pac/edma_0_tcd0/tcd/tcd_attr.rs

mcxa_pac/edma_0_tcd0/tcd/
tcd_attr.rs
