mcxa_pac/edma_0_tcd0/tcd/
ch_int.rs

1#[doc = "Register `CH_INT` reader"]
2pub type R = crate::R<ChIntSpec>;
3#[doc = "Register `CH_INT` writer"]
4pub type W = crate::W<ChIntSpec>;
5#[doc = "Interrupt Request\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Int {
9    #[doc = "0: Interrupt request for corresponding channel cleared"]
10    InterruptCleared = 0,
11    #[doc = "1: Interrupt request for corresponding channel active"]
12    InterruptActive = 1,
13}
14impl From<Int> for bool {
15    #[inline(always)]
16    fn from(variant: Int) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `INT` reader - Interrupt Request"]
21pub type IntR = crate::BitReader<Int>;
22impl IntR {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Int {
26        match self.bits {
27            false => Int::InterruptCleared,
28            true => Int::InterruptActive,
29        }
30    }
31    #[doc = "Interrupt request for corresponding channel cleared"]
32    #[inline(always)]
33    pub fn is_interrupt_cleared(&self) -> bool {
34        *self == Int::InterruptCleared
35    }
36    #[doc = "Interrupt request for corresponding channel active"]
37    #[inline(always)]
38    pub fn is_interrupt_active(&self) -> bool {
39        *self == Int::InterruptActive
40    }
41}
42#[doc = "Field `INT` writer - Interrupt Request"]
43pub type IntW<'a, REG> = crate::BitWriter1C<'a, REG, Int>;
44impl<'a, REG> IntW<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "Interrupt request for corresponding channel cleared"]
49    #[inline(always)]
50    pub fn interrupt_cleared(self) -> &'a mut crate::W<REG> {
51        self.variant(Int::InterruptCleared)
52    }
53    #[doc = "Interrupt request for corresponding channel active"]
54    #[inline(always)]
55    pub fn interrupt_active(self) -> &'a mut crate::W<REG> {
56        self.variant(Int::InterruptActive)
57    }
58}
59impl R {
60    #[doc = "Bit 0 - Interrupt Request"]
61    #[inline(always)]
62    pub fn int(&self) -> IntR {
63        IntR::new((self.bits & 1) != 0)
64    }
65}
66#[cfg(feature = "debug")]
67impl core::fmt::Debug for R {
68    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
69        f.debug_struct("CH_INT").field("int", &self.int()).finish()
70    }
71}
72impl W {
73    #[doc = "Bit 0 - Interrupt Request"]
74    #[inline(always)]
75    pub fn int(&mut self) -> IntW<'_, ChIntSpec> {
76        IntW::new(self, 0)
77    }
78}
79#[doc = "Channel Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`ch_int::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ch_int::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
80pub struct ChIntSpec;
81impl crate::RegisterSpec for ChIntSpec {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [`ch_int::R`](R) reader structure"]
85impl crate::Readable for ChIntSpec {}
86#[doc = "`write(|w| ..)` method takes [`ch_int::W`](W) writer structure"]
87impl crate::Writable for ChIntSpec {
88    type Safety = crate::Unsafe;
89    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01;
90}
91#[doc = "`reset()` method sets CH_INT to value 0"]
92impl crate::Resettable for ChIntSpec {}
mcxa_pac/edma_0_tcd0/tcd/ch_int.rs

mcxa_pac/edma_0_tcd0/tcd/
ch_int.rs
