1#[doc = "Register `CTCR` reader"]
2pub type R = crate::R<CtcrSpec>;
3#[doc = "Register `CTCR` writer"]
4pub type W = crate::W<CtcrSpec>;
5#[doc = "Counter Timer Mode\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Ctmode {
10 #[doc = "0: Timer mode"]
11 Timer = 0,
12 #[doc = "1: Counter mode rising edge"]
13 CounterRisingEdge = 1,
14 #[doc = "2: Counter mode falling edge"]
15 CounterFallingEdge = 2,
16 #[doc = "3: Counter mode dual edge"]
17 CounterDualEdge = 3,
18}
19impl From<Ctmode> for u8 {
20 #[inline(always)]
21 fn from(variant: Ctmode) -> Self {
22 variant as _
23 }
24}
25impl crate::FieldSpec for Ctmode {
26 type Ux = u8;
27}
28impl crate::IsEnum for Ctmode {}
29#[doc = "Field `CTMODE` reader - Counter Timer Mode"]
30pub type CtmodeR = crate::FieldReader<Ctmode>;
31impl CtmodeR {
32 #[doc = "Get enumerated values variant"]
33 #[inline(always)]
34 pub const fn variant(&self) -> Ctmode {
35 match self.bits {
36 0 => Ctmode::Timer,
37 1 => Ctmode::CounterRisingEdge,
38 2 => Ctmode::CounterFallingEdge,
39 3 => Ctmode::CounterDualEdge,
40 _ => unreachable!(),
41 }
42 }
43 #[doc = "Timer mode"]
44 #[inline(always)]
45 pub fn is_timer(&self) -> bool {
46 *self == Ctmode::Timer
47 }
48 #[doc = "Counter mode rising edge"]
49 #[inline(always)]
50 pub fn is_counter_rising_edge(&self) -> bool {
51 *self == Ctmode::CounterRisingEdge
52 }
53 #[doc = "Counter mode falling edge"]
54 #[inline(always)]
55 pub fn is_counter_falling_edge(&self) -> bool {
56 *self == Ctmode::CounterFallingEdge
57 }
58 #[doc = "Counter mode dual edge"]
59 #[inline(always)]
60 pub fn is_counter_dual_edge(&self) -> bool {
61 *self == Ctmode::CounterDualEdge
62 }
63}
64#[doc = "Field `CTMODE` writer - Counter Timer Mode"]
65pub type CtmodeW<'a, REG> = crate::FieldWriter<'a, REG, 2, Ctmode, crate::Safe>;
66impl<'a, REG> CtmodeW<'a, REG>
67where
68 REG: crate::Writable + crate::RegisterSpec,
69 REG::Ux: From<u8>,
70{
71 #[doc = "Timer mode"]
72 #[inline(always)]
73 pub fn timer(self) -> &'a mut crate::W<REG> {
74 self.variant(Ctmode::Timer)
75 }
76 #[doc = "Counter mode rising edge"]
77 #[inline(always)]
78 pub fn counter_rising_edge(self) -> &'a mut crate::W<REG> {
79 self.variant(Ctmode::CounterRisingEdge)
80 }
81 #[doc = "Counter mode falling edge"]
82 #[inline(always)]
83 pub fn counter_falling_edge(self) -> &'a mut crate::W<REG> {
84 self.variant(Ctmode::CounterFallingEdge)
85 }
86 #[doc = "Counter mode dual edge"]
87 #[inline(always)]
88 pub fn counter_dual_edge(self) -> &'a mut crate::W<REG> {
89 self.variant(Ctmode::CounterDualEdge)
90 }
91}
92#[doc = "Count Input Select\n\nValue on reset: 0"]
93#[cfg_attr(feature = "defmt", derive(defmt::Format))]
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95#[repr(u8)]
96pub enum Cinsel {
97 #[doc = "0: Channel 0, CAPn\\[0\\] for CTIMERn"]
98 Channel0 = 0,
99 #[doc = "1: Channel 1, CAPn\\[1\\] for CTIMERn"]
100 Channel1 = 1,
101 #[doc = "2: Channel 2, CAPn\\[2\\] for CTIMERn"]
102 Channel2 = 2,
103 #[doc = "3: Channel 3, CAPn\\[3\\] for CTIMERn"]
104 Channel3 = 3,
105}
106impl From<Cinsel> for u8 {
107 #[inline(always)]
108 fn from(variant: Cinsel) -> Self {
109 variant as _
110 }
111}
112impl crate::FieldSpec for Cinsel {
113 type Ux = u8;
114}
115impl crate::IsEnum for Cinsel {}
116#[doc = "Field `CINSEL` reader - Count Input Select"]
117pub type CinselR = crate::FieldReader<Cinsel>;
118impl CinselR {
119 #[doc = "Get enumerated values variant"]
120 #[inline(always)]
121 pub const fn variant(&self) -> Cinsel {
122 match self.bits {
123 0 => Cinsel::Channel0,
124 1 => Cinsel::Channel1,
125 2 => Cinsel::Channel2,
126 3 => Cinsel::Channel3,
127 _ => unreachable!(),
128 }
129 }
130 #[doc = "Channel 0, CAPn\\[0\\] for CTIMERn"]
131 #[inline(always)]
132 pub fn is_channel_0(&self) -> bool {
133 *self == Cinsel::Channel0
134 }
135 #[doc = "Channel 1, CAPn\\[1\\] for CTIMERn"]
136 #[inline(always)]
137 pub fn is_channel_1(&self) -> bool {
138 *self == Cinsel::Channel1
139 }
140 #[doc = "Channel 2, CAPn\\[2\\] for CTIMERn"]
141 #[inline(always)]
142 pub fn is_channel_2(&self) -> bool {
143 *self == Cinsel::Channel2
144 }
145 #[doc = "Channel 3, CAPn\\[3\\] for CTIMERn"]
146 #[inline(always)]
147 pub fn is_channel_3(&self) -> bool {
148 *self == Cinsel::Channel3
149 }
150}
151#[doc = "Field `CINSEL` writer - Count Input Select"]
152pub type CinselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Cinsel, crate::Safe>;
153impl<'a, REG> CinselW<'a, REG>
154where
155 REG: crate::Writable + crate::RegisterSpec,
156 REG::Ux: From<u8>,
157{
158 #[doc = "Channel 0, CAPn\\[0\\] for CTIMERn"]
159 #[inline(always)]
160 pub fn channel_0(self) -> &'a mut crate::W<REG> {
161 self.variant(Cinsel::Channel0)
162 }
163 #[doc = "Channel 1, CAPn\\[1\\] for CTIMERn"]
164 #[inline(always)]
165 pub fn channel_1(self) -> &'a mut crate::W<REG> {
166 self.variant(Cinsel::Channel1)
167 }
168 #[doc = "Channel 2, CAPn\\[2\\] for CTIMERn"]
169 #[inline(always)]
170 pub fn channel_2(self) -> &'a mut crate::W<REG> {
171 self.variant(Cinsel::Channel2)
172 }
173 #[doc = "Channel 3, CAPn\\[3\\] for CTIMERn"]
174 #[inline(always)]
175 pub fn channel_3(self) -> &'a mut crate::W<REG> {
176 self.variant(Cinsel::Channel3)
177 }
178}
179#[doc = "Field `ENCC` reader - Capture Channel Enable"]
180pub type EnccR = crate::BitReader;
181#[doc = "Field `ENCC` writer - Capture Channel Enable"]
182pub type EnccW<'a, REG> = crate::BitWriter<'a, REG>;
183#[doc = "Edge Select\n\nValue on reset: 0"]
184#[cfg_attr(feature = "defmt", derive(defmt::Format))]
185#[derive(Clone, Copy, Debug, PartialEq, Eq)]
186#[repr(u8)]
187pub enum Selcc {
188 #[doc = "0: Capture channel 0 rising edge"]
189 Channel0Rising = 0,
190 #[doc = "1: Capture channel 0 falling edge"]
191 Channel0Falling = 1,
192 #[doc = "2: Capture channel 1 rising edge"]
193 Channel1Rising = 2,
194 #[doc = "3: Capture channel 1 falling edge"]
195 Channel1Falling = 3,
196 #[doc = "4: Capture channel 2 rising edge"]
197 Channel2Rising = 4,
198 #[doc = "5: Capture channel 2 falling edge"]
199 Channel2Falling = 5,
200 #[doc = "6: Capture channel 3 rising edge"]
201 Channel3Rising = 6,
202 #[doc = "7: Capture channel 3 falling edge"]
203 Channel3Falling = 7,
204}
205impl From<Selcc> for u8 {
206 #[inline(always)]
207 fn from(variant: Selcc) -> Self {
208 variant as _
209 }
210}
211impl crate::FieldSpec for Selcc {
212 type Ux = u8;
213}
214impl crate::IsEnum for Selcc {}
215#[doc = "Field `SELCC` reader - Edge Select"]
216pub type SelccR = crate::FieldReader<Selcc>;
217impl SelccR {
218 #[doc = "Get enumerated values variant"]
219 #[inline(always)]
220 pub const fn variant(&self) -> Selcc {
221 match self.bits {
222 0 => Selcc::Channel0Rising,
223 1 => Selcc::Channel0Falling,
224 2 => Selcc::Channel1Rising,
225 3 => Selcc::Channel1Falling,
226 4 => Selcc::Channel2Rising,
227 5 => Selcc::Channel2Falling,
228 6 => Selcc::Channel3Rising,
229 7 => Selcc::Channel3Falling,
230 _ => unreachable!(),
231 }
232 }
233 #[doc = "Capture channel 0 rising edge"]
234 #[inline(always)]
235 pub fn is_channel_0_rising(&self) -> bool {
236 *self == Selcc::Channel0Rising
237 }
238 #[doc = "Capture channel 0 falling edge"]
239 #[inline(always)]
240 pub fn is_channel_0_falling(&self) -> bool {
241 *self == Selcc::Channel0Falling
242 }
243 #[doc = "Capture channel 1 rising edge"]
244 #[inline(always)]
245 pub fn is_channel_1_rising(&self) -> bool {
246 *self == Selcc::Channel1Rising
247 }
248 #[doc = "Capture channel 1 falling edge"]
249 #[inline(always)]
250 pub fn is_channel_1_falling(&self) -> bool {
251 *self == Selcc::Channel1Falling
252 }
253 #[doc = "Capture channel 2 rising edge"]
254 #[inline(always)]
255 pub fn is_channel_2_rising(&self) -> bool {
256 *self == Selcc::Channel2Rising
257 }
258 #[doc = "Capture channel 2 falling edge"]
259 #[inline(always)]
260 pub fn is_channel_2_falling(&self) -> bool {
261 *self == Selcc::Channel2Falling
262 }
263 #[doc = "Capture channel 3 rising edge"]
264 #[inline(always)]
265 pub fn is_channel_3_rising(&self) -> bool {
266 *self == Selcc::Channel3Rising
267 }
268 #[doc = "Capture channel 3 falling edge"]
269 #[inline(always)]
270 pub fn is_channel_3_falling(&self) -> bool {
271 *self == Selcc::Channel3Falling
272 }
273}
274#[doc = "Field `SELCC` writer - Edge Select"]
275pub type SelccW<'a, REG> = crate::FieldWriter<'a, REG, 3, Selcc, crate::Safe>;
276impl<'a, REG> SelccW<'a, REG>
277where
278 REG: crate::Writable + crate::RegisterSpec,
279 REG::Ux: From<u8>,
280{
281 #[doc = "Capture channel 0 rising edge"]
282 #[inline(always)]
283 pub fn channel_0_rising(self) -> &'a mut crate::W<REG> {
284 self.variant(Selcc::Channel0Rising)
285 }
286 #[doc = "Capture channel 0 falling edge"]
287 #[inline(always)]
288 pub fn channel_0_falling(self) -> &'a mut crate::W<REG> {
289 self.variant(Selcc::Channel0Falling)
290 }
291 #[doc = "Capture channel 1 rising edge"]
292 #[inline(always)]
293 pub fn channel_1_rising(self) -> &'a mut crate::W<REG> {
294 self.variant(Selcc::Channel1Rising)
295 }
296 #[doc = "Capture channel 1 falling edge"]
297 #[inline(always)]
298 pub fn channel_1_falling(self) -> &'a mut crate::W<REG> {
299 self.variant(Selcc::Channel1Falling)
300 }
301 #[doc = "Capture channel 2 rising edge"]
302 #[inline(always)]
303 pub fn channel_2_rising(self) -> &'a mut crate::W<REG> {
304 self.variant(Selcc::Channel2Rising)
305 }
306 #[doc = "Capture channel 2 falling edge"]
307 #[inline(always)]
308 pub fn channel_2_falling(self) -> &'a mut crate::W<REG> {
309 self.variant(Selcc::Channel2Falling)
310 }
311 #[doc = "Capture channel 3 rising edge"]
312 #[inline(always)]
313 pub fn channel_3_rising(self) -> &'a mut crate::W<REG> {
314 self.variant(Selcc::Channel3Rising)
315 }
316 #[doc = "Capture channel 3 falling edge"]
317 #[inline(always)]
318 pub fn channel_3_falling(self) -> &'a mut crate::W<REG> {
319 self.variant(Selcc::Channel3Falling)
320 }
321}
322impl R {
323 #[doc = "Bits 0:1 - Counter Timer Mode"]
324 #[inline(always)]
325 pub fn ctmode(&self) -> CtmodeR {
326 CtmodeR::new((self.bits & 3) as u8)
327 }
328 #[doc = "Bits 2:3 - Count Input Select"]
329 #[inline(always)]
330 pub fn cinsel(&self) -> CinselR {
331 CinselR::new(((self.bits >> 2) & 3) as u8)
332 }
333 #[doc = "Bit 4 - Capture Channel Enable"]
334 #[inline(always)]
335 pub fn encc(&self) -> EnccR {
336 EnccR::new(((self.bits >> 4) & 1) != 0)
337 }
338 #[doc = "Bits 5:7 - Edge Select"]
339 #[inline(always)]
340 pub fn selcc(&self) -> SelccR {
341 SelccR::new(((self.bits >> 5) & 7) as u8)
342 }
343}
344#[cfg(feature = "debug")]
345impl core::fmt::Debug for R {
346 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
347 f.debug_struct("CTCR")
348 .field("ctmode", &self.ctmode())
349 .field("cinsel", &self.cinsel())
350 .field("encc", &self.encc())
351 .field("selcc", &self.selcc())
352 .finish()
353 }
354}
355impl W {
356 #[doc = "Bits 0:1 - Counter Timer Mode"]
357 #[inline(always)]
358 pub fn ctmode(&mut self) -> CtmodeW<'_, CtcrSpec> {
359 CtmodeW::new(self, 0)
360 }
361 #[doc = "Bits 2:3 - Count Input Select"]
362 #[inline(always)]
363 pub fn cinsel(&mut self) -> CinselW<'_, CtcrSpec> {
364 CinselW::new(self, 2)
365 }
366 #[doc = "Bit 4 - Capture Channel Enable"]
367 #[inline(always)]
368 pub fn encc(&mut self) -> EnccW<'_, CtcrSpec> {
369 EnccW::new(self, 4)
370 }
371 #[doc = "Bits 5:7 - Edge Select"]
372 #[inline(always)]
373 pub fn selcc(&mut self) -> SelccW<'_, CtcrSpec> {
374 SelccW::new(self, 5)
375 }
376}
377#[doc = "Count Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctcr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctcr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
378pub struct CtcrSpec;
379impl crate::RegisterSpec for CtcrSpec {
380 type Ux = u32;
381}
382#[doc = "`read()` method returns [`ctcr::R`](R) reader structure"]
383impl crate::Readable for CtcrSpec {}
384#[doc = "`write(|w| ..)` method takes [`ctcr::W`](W) writer structure"]
385impl crate::Writable for CtcrSpec {
386 type Safety = crate::Unsafe;
387}
388#[doc = "`reset()` method sets CTCR to value 0"]
389impl crate::Resettable for CtcrSpec {}