mcxa_pac/can0/
flt_dlc.rs

1#[doc = "Register `FLT_DLC` reader"]
2pub type R = crate::R<FltDlcSpec>;
3#[doc = "Register `FLT_DLC` writer"]
4pub type W = crate::W<FltDlcSpec>;
5#[doc = "Field `FLT_DLC_HI` reader - Upper Limit for Length of Data Bytes Filter"]
6pub type FltDlcHiR = crate::FieldReader;
7#[doc = "Field `FLT_DLC_HI` writer - Upper Limit for Length of Data Bytes Filter"]
8pub type FltDlcHiW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `FLT_DLC_LO` reader - Lower Limit for Length of Data Bytes Filter"]
10pub type FltDlcLoR = crate::FieldReader;
11#[doc = "Field `FLT_DLC_LO` writer - Lower Limit for Length of Data Bytes Filter"]
12pub type FltDlcLoW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13impl R {
14    #[doc = "Bits 0:3 - Upper Limit for Length of Data Bytes Filter"]
15    #[inline(always)]
16    pub fn flt_dlc_hi(&self) -> FltDlcHiR {
17        FltDlcHiR::new((self.bits & 0x0f) as u8)
18    }
19    #[doc = "Bits 16:19 - Lower Limit for Length of Data Bytes Filter"]
20    #[inline(always)]
21    pub fn flt_dlc_lo(&self) -> FltDlcLoR {
22        FltDlcLoR::new(((self.bits >> 16) & 0x0f) as u8)
23    }
24}
25#[cfg(feature = "debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("FLT_DLC")
29            .field("flt_dlc_hi", &self.flt_dlc_hi())
30            .field("flt_dlc_lo", &self.flt_dlc_lo())
31            .finish()
32    }
33}
34impl W {
35    #[doc = "Bits 0:3 - Upper Limit for Length of Data Bytes Filter"]
36    #[inline(always)]
37    pub fn flt_dlc_hi(&mut self) -> FltDlcHiW<'_, FltDlcSpec> {
38        FltDlcHiW::new(self, 0)
39    }
40    #[doc = "Bits 16:19 - Lower Limit for Length of Data Bytes Filter"]
41    #[inline(always)]
42    pub fn flt_dlc_lo(&mut self) -> FltDlcLoW<'_, FltDlcSpec> {
43        FltDlcLoW::new(self, 16)
44    }
45}
46#[doc = "Pretended Networking Data Length Code (DLC) Filter\n\nYou can [`read`](crate::Reg::read) this register and get [`flt_dlc::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`flt_dlc::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct FltDlcSpec;
48impl crate::RegisterSpec for FltDlcSpec {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`flt_dlc::R`](R) reader structure"]
52impl crate::Readable for FltDlcSpec {}
53#[doc = "`write(|w| ..)` method takes [`flt_dlc::W`](W) writer structure"]
54impl crate::Writable for FltDlcSpec {
55    type Safety = crate::Unsafe;
56}
57#[doc = "`reset()` method sets FLT_DLC to value 0x08"]
58impl crate::Resettable for FltDlcSpec {
59    const RESET_VALUE: u32 = 0x08;
60}
mcxa_pac/can0/flt_dlc.rs

mcxa_pac/can0/
flt_dlc.rs
