1#[doc = "Register `VERID` reader"]
2pub type R = crate::R<VeridSpec>;
3#[doc = "Resolution\n\nValue on reset: 1"]
4#[cfg_attr(feature = "defmt", derive(defmt::Format))]
5#[derive(Clone, Copy, Debug, PartialEq, Eq)]
6pub enum Res {
7 #[doc = "0: Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."]
8 Max13Bit = 0,
9 #[doc = "1: Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."]
10 Max16Bit = 1,
11}
12impl From<Res> for bool {
13 #[inline(always)]
14 fn from(variant: Res) -> Self {
15 variant as u8 != 0
16 }
17}
18#[doc = "Field `RES` reader - Resolution"]
19pub type ResR = crate::BitReader<Res>;
20impl ResR {
21 #[doc = "Get enumerated values variant"]
22 #[inline(always)]
23 pub const fn variant(&self) -> Res {
24 match self.bits {
25 false => Res::Max13Bit,
26 true => Res::Max16Bit,
27 }
28 }
29 #[doc = "Up to 12-bit single ended resolution supported (and 13-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."]
30 #[inline(always)]
31 pub fn is_max_13_bit(&self) -> bool {
32 *self == Res::Max13Bit
33 }
34 #[doc = "Up to 16-bit single ended resolution supported (and 16-bit differential resolution if VERID\\[DIFFEN\\] = 1b)."]
35 #[inline(always)]
36 pub fn is_max_16_bit(&self) -> bool {
37 *self == Res::Max16Bit
38 }
39}
40#[doc = "Differential Supported\n\nValue on reset: 0"]
41#[cfg_attr(feature = "defmt", derive(defmt::Format))]
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum Diffen {
44 #[doc = "0: Differential operation not supported."]
45 DifferentialNotSupported = 0,
46 #[doc = "1: Differential operation supported."]
47 DifferentialSupported = 1,
48}
49impl From<Diffen> for bool {
50 #[inline(always)]
51 fn from(variant: Diffen) -> Self {
52 variant as u8 != 0
53 }
54}
55#[doc = "Field `DIFFEN` reader - Differential Supported"]
56pub type DiffenR = crate::BitReader<Diffen>;
57impl DiffenR {
58 #[doc = "Get enumerated values variant"]
59 #[inline(always)]
60 pub const fn variant(&self) -> Diffen {
61 match self.bits {
62 false => Diffen::DifferentialNotSupported,
63 true => Diffen::DifferentialSupported,
64 }
65 }
66 #[doc = "Differential operation not supported."]
67 #[inline(always)]
68 pub fn is_differential_not_supported(&self) -> bool {
69 *self == Diffen::DifferentialNotSupported
70 }
71 #[doc = "Differential operation supported."]
72 #[inline(always)]
73 pub fn is_differential_supported(&self) -> bool {
74 *self == Diffen::DifferentialSupported
75 }
76}
77#[doc = "Multi Vref Implemented\n\nValue on reset: 1"]
78#[cfg_attr(feature = "defmt", derive(defmt::Format))]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80pub enum Mvi {
81 #[doc = "0: Single voltage reference high (VREFH) input supported."]
82 MultipleRefNotSupported = 0,
83 #[doc = "1: Multiple voltage reference high (VREFH) inputs supported."]
84 MultipleRefSupported = 1,
85}
86impl From<Mvi> for bool {
87 #[inline(always)]
88 fn from(variant: Mvi) -> Self {
89 variant as u8 != 0
90 }
91}
92#[doc = "Field `MVI` reader - Multi Vref Implemented"]
93pub type MviR = crate::BitReader<Mvi>;
94impl MviR {
95 #[doc = "Get enumerated values variant"]
96 #[inline(always)]
97 pub const fn variant(&self) -> Mvi {
98 match self.bits {
99 false => Mvi::MultipleRefNotSupported,
100 true => Mvi::MultipleRefSupported,
101 }
102 }
103 #[doc = "Single voltage reference high (VREFH) input supported."]
104 #[inline(always)]
105 pub fn is_multiple_ref_not_supported(&self) -> bool {
106 *self == Mvi::MultipleRefNotSupported
107 }
108 #[doc = "Multiple voltage reference high (VREFH) inputs supported."]
109 #[inline(always)]
110 pub fn is_multiple_ref_supported(&self) -> bool {
111 *self == Mvi::MultipleRefSupported
112 }
113}
114#[doc = "Channel Scale Width\n\nValue on reset: 0"]
115#[cfg_attr(feature = "defmt", derive(defmt::Format))]
116#[derive(Clone, Copy, Debug, PartialEq, Eq)]
117#[repr(u8)]
118pub enum Csw {
119 #[doc = "0: Channel scaling not supported."]
120 CscaleNotSupported = 0,
121 #[doc = "1: Channel scaling supported. 1-bit CSCALE control field."]
122 BitWidth1 = 1,
123 #[doc = "6: Channel scaling supported. 6-bit CSCALE control field."]
124 BitWidth6 = 6,
125}
126impl From<Csw> for u8 {
127 #[inline(always)]
128 fn from(variant: Csw) -> Self {
129 variant as _
130 }
131}
132impl crate::FieldSpec for Csw {
133 type Ux = u8;
134}
135impl crate::IsEnum for Csw {}
136#[doc = "Field `CSW` reader - Channel Scale Width"]
137pub type CswR = crate::FieldReader<Csw>;
138impl CswR {
139 #[doc = "Get enumerated values variant"]
140 #[inline(always)]
141 pub const fn variant(&self) -> Option<Csw> {
142 match self.bits {
143 0 => Some(Csw::CscaleNotSupported),
144 1 => Some(Csw::BitWidth1),
145 6 => Some(Csw::BitWidth6),
146 _ => None,
147 }
148 }
149 #[doc = "Channel scaling not supported."]
150 #[inline(always)]
151 pub fn is_cscale_not_supported(&self) -> bool {
152 *self == Csw::CscaleNotSupported
153 }
154 #[doc = "Channel scaling supported. 1-bit CSCALE control field."]
155 #[inline(always)]
156 pub fn is_bit_width_1(&self) -> bool {
157 *self == Csw::BitWidth1
158 }
159 #[doc = "Channel scaling supported. 6-bit CSCALE control field."]
160 #[inline(always)]
161 pub fn is_bit_width_6(&self) -> bool {
162 *self == Csw::BitWidth6
163 }
164}
165#[doc = "Voltage Reference 1 Range Control Bit Implemented\n\nValue on reset: 0"]
166#[cfg_attr(feature = "defmt", derive(defmt::Format))]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum Vr1rngi {
169 #[doc = "0: Range control not required. CFG\\[VREF1RNG\\] is not implemented."]
170 Ref1FixedVoltageRange = 0,
171 #[doc = "1: Range control required. CFG\\[VREF1RNG\\] is implemented."]
172 Ref1SelectableVoltageRange = 1,
173}
174impl From<Vr1rngi> for bool {
175 #[inline(always)]
176 fn from(variant: Vr1rngi) -> Self {
177 variant as u8 != 0
178 }
179}
180#[doc = "Field `VR1RNGI` reader - Voltage Reference 1 Range Control Bit Implemented"]
181pub type Vr1rngiR = crate::BitReader<Vr1rngi>;
182impl Vr1rngiR {
183 #[doc = "Get enumerated values variant"]
184 #[inline(always)]
185 pub const fn variant(&self) -> Vr1rngi {
186 match self.bits {
187 false => Vr1rngi::Ref1FixedVoltageRange,
188 true => Vr1rngi::Ref1SelectableVoltageRange,
189 }
190 }
191 #[doc = "Range control not required. CFG\\[VREF1RNG\\] is not implemented."]
192 #[inline(always)]
193 pub fn is_ref1_fixed_voltage_range(&self) -> bool {
194 *self == Vr1rngi::Ref1FixedVoltageRange
195 }
196 #[doc = "Range control required. CFG\\[VREF1RNG\\] is implemented."]
197 #[inline(always)]
198 pub fn is_ref1_selectable_voltage_range(&self) -> bool {
199 *self == Vr1rngi::Ref1SelectableVoltageRange
200 }
201}
202#[doc = "Internal ADC Clock Implemented\n\nValue on reset: 0"]
203#[cfg_attr(feature = "defmt", derive(defmt::Format))]
204#[derive(Clone, Copy, Debug, PartialEq, Eq)]
205pub enum Iadcki {
206 #[doc = "0: Internal clock source not implemented."]
207 InternalClkNotAvailable = 0,
208 #[doc = "1: Internal clock source (and CFG\\[ADCKEN\\]) implemented."]
209 InternalClkAvailable = 1,
210}
211impl From<Iadcki> for bool {
212 #[inline(always)]
213 fn from(variant: Iadcki) -> Self {
214 variant as u8 != 0
215 }
216}
217#[doc = "Field `IADCKI` reader - Internal ADC Clock Implemented"]
218pub type IadckiR = crate::BitReader<Iadcki>;
219impl IadckiR {
220 #[doc = "Get enumerated values variant"]
221 #[inline(always)]
222 pub const fn variant(&self) -> Iadcki {
223 match self.bits {
224 false => Iadcki::InternalClkNotAvailable,
225 true => Iadcki::InternalClkAvailable,
226 }
227 }
228 #[doc = "Internal clock source not implemented."]
229 #[inline(always)]
230 pub fn is_internal_clk_not_available(&self) -> bool {
231 *self == Iadcki::InternalClkNotAvailable
232 }
233 #[doc = "Internal clock source (and CFG\\[ADCKEN\\]) implemented."]
234 #[inline(always)]
235 pub fn is_internal_clk_available(&self) -> bool {
236 *self == Iadcki::InternalClkAvailable
237 }
238}
239#[doc = "Calibration Function Implemented\n\nValue on reset: 1"]
240#[cfg_attr(feature = "defmt", derive(defmt::Format))]
241#[derive(Clone, Copy, Debug, PartialEq, Eq)]
242pub enum Calofsi {
243 #[doc = "0: Calibration Not Implemented."]
244 CalFunctionNotAvailable = 0,
245 #[doc = "1: Calibration Implemented."]
246 CalFunctionAvailable = 1,
247}
248impl From<Calofsi> for bool {
249 #[inline(always)]
250 fn from(variant: Calofsi) -> Self {
251 variant as u8 != 0
252 }
253}
254#[doc = "Field `CALOFSI` reader - Calibration Function Implemented"]
255pub type CalofsiR = crate::BitReader<Calofsi>;
256impl CalofsiR {
257 #[doc = "Get enumerated values variant"]
258 #[inline(always)]
259 pub const fn variant(&self) -> Calofsi {
260 match self.bits {
261 false => Calofsi::CalFunctionNotAvailable,
262 true => Calofsi::CalFunctionAvailable,
263 }
264 }
265 #[doc = "Calibration Not Implemented."]
266 #[inline(always)]
267 pub fn is_cal_function_not_available(&self) -> bool {
268 *self == Calofsi::CalFunctionNotAvailable
269 }
270 #[doc = "Calibration Implemented."]
271 #[inline(always)]
272 pub fn is_cal_function_available(&self) -> bool {
273 *self == Calofsi::CalFunctionAvailable
274 }
275}
276#[doc = "Number of Single Ended Outputs Supported\n\nValue on reset: 0"]
277#[cfg_attr(feature = "defmt", derive(defmt::Format))]
278#[derive(Clone, Copy, Debug, PartialEq, Eq)]
279pub enum NumSec {
280 #[doc = "0: This design supports one single ended conversion at a time."]
281 SingleConvertor = 0,
282 #[doc = "1: This design supports two simultaneous single ended conversions."]
283 DualConvertor = 1,
284}
285impl From<NumSec> for bool {
286 #[inline(always)]
287 fn from(variant: NumSec) -> Self {
288 variant as u8 != 0
289 }
290}
291#[doc = "Field `NUM_SEC` reader - Number of Single Ended Outputs Supported"]
292pub type NumSecR = crate::BitReader<NumSec>;
293impl NumSecR {
294 #[doc = "Get enumerated values variant"]
295 #[inline(always)]
296 pub const fn variant(&self) -> NumSec {
297 match self.bits {
298 false => NumSec::SingleConvertor,
299 true => NumSec::DualConvertor,
300 }
301 }
302 #[doc = "This design supports one single ended conversion at a time."]
303 #[inline(always)]
304 pub fn is_single_convertor(&self) -> bool {
305 *self == NumSec::SingleConvertor
306 }
307 #[doc = "This design supports two simultaneous single ended conversions."]
308 #[inline(always)]
309 pub fn is_dual_convertor(&self) -> bool {
310 *self == NumSec::DualConvertor
311 }
312}
313#[doc = "Number of FIFOs\n\nValue on reset: 1"]
314#[cfg_attr(feature = "defmt", derive(defmt::Format))]
315#[derive(Clone, Copy, Debug, PartialEq, Eq)]
316#[repr(u8)]
317pub enum NumFifo {
318 #[doc = "0: N/A"]
319 NoFifoImplemented = 0,
320 #[doc = "1: This design supports one result FIFO."]
321 Cnt1 = 1,
322 #[doc = "2: This design supports two result FIFOs."]
323 Cnt2 = 2,
324 #[doc = "3: This design supports three result FIFOs."]
325 Cnt3 = 3,
326 #[doc = "4: This design supports four result FIFOs."]
327 Cnt4 = 4,
328}
329impl From<NumFifo> for u8 {
330 #[inline(always)]
331 fn from(variant: NumFifo) -> Self {
332 variant as _
333 }
334}
335impl crate::FieldSpec for NumFifo {
336 type Ux = u8;
337}
338impl crate::IsEnum for NumFifo {}
339#[doc = "Field `NUM_FIFO` reader - Number of FIFOs"]
340pub type NumFifoR = crate::FieldReader<NumFifo>;
341impl NumFifoR {
342 #[doc = "Get enumerated values variant"]
343 #[inline(always)]
344 pub const fn variant(&self) -> Option<NumFifo> {
345 match self.bits {
346 0 => Some(NumFifo::NoFifoImplemented),
347 1 => Some(NumFifo::Cnt1),
348 2 => Some(NumFifo::Cnt2),
349 3 => Some(NumFifo::Cnt3),
350 4 => Some(NumFifo::Cnt4),
351 _ => None,
352 }
353 }
354 #[doc = "N/A"]
355 #[inline(always)]
356 pub fn is_no_fifo_implemented(&self) -> bool {
357 *self == NumFifo::NoFifoImplemented
358 }
359 #[doc = "This design supports one result FIFO."]
360 #[inline(always)]
361 pub fn is_cnt_1(&self) -> bool {
362 *self == NumFifo::Cnt1
363 }
364 #[doc = "This design supports two result FIFOs."]
365 #[inline(always)]
366 pub fn is_cnt_2(&self) -> bool {
367 *self == NumFifo::Cnt2
368 }
369 #[doc = "This design supports three result FIFOs."]
370 #[inline(always)]
371 pub fn is_cnt_3(&self) -> bool {
372 *self == NumFifo::Cnt3
373 }
374 #[doc = "This design supports four result FIFOs."]
375 #[inline(always)]
376 pub fn is_cnt_4(&self) -> bool {
377 *self == NumFifo::Cnt4
378 }
379}
380#[doc = "Field `MINOR` reader - Minor Version Number"]
381pub type MinorR = crate::FieldReader;
382#[doc = "Field `MAJOR` reader - Major Version Number"]
383pub type MajorR = crate::FieldReader;
384impl R {
385 #[doc = "Bit 0 - Resolution"]
386 #[inline(always)]
387 pub fn res(&self) -> ResR {
388 ResR::new((self.bits & 1) != 0)
389 }
390 #[doc = "Bit 1 - Differential Supported"]
391 #[inline(always)]
392 pub fn diffen(&self) -> DiffenR {
393 DiffenR::new(((self.bits >> 1) & 1) != 0)
394 }
395 #[doc = "Bit 3 - Multi Vref Implemented"]
396 #[inline(always)]
397 pub fn mvi(&self) -> MviR {
398 MviR::new(((self.bits >> 3) & 1) != 0)
399 }
400 #[doc = "Bits 4:6 - Channel Scale Width"]
401 #[inline(always)]
402 pub fn csw(&self) -> CswR {
403 CswR::new(((self.bits >> 4) & 7) as u8)
404 }
405 #[doc = "Bit 8 - Voltage Reference 1 Range Control Bit Implemented"]
406 #[inline(always)]
407 pub fn vr1rngi(&self) -> Vr1rngiR {
408 Vr1rngiR::new(((self.bits >> 8) & 1) != 0)
409 }
410 #[doc = "Bit 9 - Internal ADC Clock Implemented"]
411 #[inline(always)]
412 pub fn iadcki(&self) -> IadckiR {
413 IadckiR::new(((self.bits >> 9) & 1) != 0)
414 }
415 #[doc = "Bit 10 - Calibration Function Implemented"]
416 #[inline(always)]
417 pub fn calofsi(&self) -> CalofsiR {
418 CalofsiR::new(((self.bits >> 10) & 1) != 0)
419 }
420 #[doc = "Bit 11 - Number of Single Ended Outputs Supported"]
421 #[inline(always)]
422 pub fn num_sec(&self) -> NumSecR {
423 NumSecR::new(((self.bits >> 11) & 1) != 0)
424 }
425 #[doc = "Bits 12:14 - Number of FIFOs"]
426 #[inline(always)]
427 pub fn num_fifo(&self) -> NumFifoR {
428 NumFifoR::new(((self.bits >> 12) & 7) as u8)
429 }
430 #[doc = "Bits 16:23 - Minor Version Number"]
431 #[inline(always)]
432 pub fn minor(&self) -> MinorR {
433 MinorR::new(((self.bits >> 16) & 0xff) as u8)
434 }
435 #[doc = "Bits 24:31 - Major Version Number"]
436 #[inline(always)]
437 pub fn major(&self) -> MajorR {
438 MajorR::new(((self.bits >> 24) & 0xff) as u8)
439 }
440}
441#[cfg(feature = "debug")]
442impl core::fmt::Debug for R {
443 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
444 f.debug_struct("VERID")
445 .field("res", &self.res())
446 .field("diffen", &self.diffen())
447 .field("mvi", &self.mvi())
448 .field("csw", &self.csw())
449 .field("vr1rngi", &self.vr1rngi())
450 .field("iadcki", &self.iadcki())
451 .field("calofsi", &self.calofsi())
452 .field("num_sec", &self.num_sec())
453 .field("num_fifo", &self.num_fifo())
454 .field("minor", &self.minor())
455 .field("major", &self.major())
456 .finish()
457 }
458}
459#[doc = "Version ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`verid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
460pub struct VeridSpec;
461impl crate::RegisterSpec for VeridSpec {
462 type Ux = u32;
463}
464#[doc = "`read()` method returns [`verid::R`](R) reader structure"]
465impl crate::Readable for VeridSpec {}
466#[doc = "`reset()` method sets VERID to value 0x0200_1409"]
467impl crate::Resettable for VeridSpec {
468 const RESET_VALUE: u32 = 0x0200_1409;
469}