mcxa_pac/adc0/
de.rs

1#[doc = "Register `DE` reader"]
2pub type R = crate::R<DeSpec>;
3#[doc = "Register `DE` writer"]
4pub type W = crate::W<DeSpec>;
5#[doc = "FIFO 0 Watermark DMA Enable\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8pub enum Fwmde0 {
9    #[doc = "0: DMA request disabled."]
10    Disabled = 0,
11    #[doc = "1: DMA request enabled."]
12    Enabled = 1,
13}
14impl From<Fwmde0> for bool {
15    #[inline(always)]
16    fn from(variant: Fwmde0) -> Self {
17        variant as u8 != 0
18    }
19}
20#[doc = "Field `FWMDE0` reader - FIFO 0 Watermark DMA Enable"]
21pub type Fwmde0R = crate::BitReader<Fwmde0>;
22impl Fwmde0R {
23    #[doc = "Get enumerated values variant"]
24    #[inline(always)]
25    pub const fn variant(&self) -> Fwmde0 {
26        match self.bits {
27            false => Fwmde0::Disabled,
28            true => Fwmde0::Enabled,
29        }
30    }
31    #[doc = "DMA request disabled."]
32    #[inline(always)]
33    pub fn is_disabled(&self) -> bool {
34        *self == Fwmde0::Disabled
35    }
36    #[doc = "DMA request enabled."]
37    #[inline(always)]
38    pub fn is_enabled(&self) -> bool {
39        *self == Fwmde0::Enabled
40    }
41}
42#[doc = "Field `FWMDE0` writer - FIFO 0 Watermark DMA Enable"]
43pub type Fwmde0W<'a, REG> = crate::BitWriter<'a, REG, Fwmde0>;
44impl<'a, REG> Fwmde0W<'a, REG>
45where
46    REG: crate::Writable + crate::RegisterSpec,
47{
48    #[doc = "DMA request disabled."]
49    #[inline(always)]
50    pub fn disabled(self) -> &'a mut crate::W<REG> {
51        self.variant(Fwmde0::Disabled)
52    }
53    #[doc = "DMA request enabled."]
54    #[inline(always)]
55    pub fn enabled(self) -> &'a mut crate::W<REG> {
56        self.variant(Fwmde0::Enabled)
57    }
58}
59impl R {
60    #[doc = "Bit 0 - FIFO 0 Watermark DMA Enable"]
61    #[inline(always)]
62    pub fn fwmde0(&self) -> Fwmde0R {
63        Fwmde0R::new((self.bits & 1) != 0)
64    }
65}
66#[cfg(feature = "debug")]
67impl core::fmt::Debug for R {
68    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
69        f.debug_struct("DE").field("fwmde0", &self.fwmde0()).finish()
70    }
71}
72impl W {
73    #[doc = "Bit 0 - FIFO 0 Watermark DMA Enable"]
74    #[inline(always)]
75    pub fn fwmde0(&mut self) -> Fwmde0W<'_, DeSpec> {
76        Fwmde0W::new(self, 0)
77    }
78}
79#[doc = "DMA Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`de::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`de::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
80pub struct DeSpec;
81impl crate::RegisterSpec for DeSpec {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [`de::R`](R) reader structure"]
85impl crate::Readable for DeSpec {}
86#[doc = "`write(|w| ..)` method takes [`de::W`](W) writer structure"]
87impl crate::Writable for DeSpec {
88    type Safety = crate::Unsafe;
89}
90#[doc = "`reset()` method sets DE to value 0"]
91impl crate::Resettable for DeSpec {}
mcxa_pac/adc0/de.rs

mcxa_pac/adc0/
de.rs
