1#[doc = "Register `CFG2` reader"]
2pub type R = crate::R<Cfg2Spec>;
3#[doc = "Register `CFG2` writer"]
4pub type W = crate::W<Cfg2Spec>;
5#[doc = "Field `JLEFT` reader - Justified Left Enable register"]
6pub type JleftR = crate::BitReader;
7#[doc = "Field `JLEFT` writer - Justified Left Enable register"]
8pub type JleftW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "High Speed Enable register\n\nValue on reset: 0"]
10#[cfg_attr(feature = "defmt", derive(defmt::Format))]
11#[derive(Clone, Copy, Debug, PartialEq, Eq)]
12pub enum Hs {
13 #[doc = "0: High speed conversion mode disabled"]
14 Disabled = 0,
15 #[doc = "1: High speed conversion mode enabled"]
16 Enabled = 1,
17}
18impl From<Hs> for bool {
19 #[inline(always)]
20 fn from(variant: Hs) -> Self {
21 variant as u8 != 0
22 }
23}
24#[doc = "Field `HS` reader - High Speed Enable register"]
25pub type HsR = crate::BitReader<Hs>;
26impl HsR {
27 #[doc = "Get enumerated values variant"]
28 #[inline(always)]
29 pub const fn variant(&self) -> Hs {
30 match self.bits {
31 false => Hs::Disabled,
32 true => Hs::Enabled,
33 }
34 }
35 #[doc = "High speed conversion mode disabled"]
36 #[inline(always)]
37 pub fn is_disabled(&self) -> bool {
38 *self == Hs::Disabled
39 }
40 #[doc = "High speed conversion mode enabled"]
41 #[inline(always)]
42 pub fn is_enabled(&self) -> bool {
43 *self == Hs::Enabled
44 }
45}
46#[doc = "Field `HS` writer - High Speed Enable register"]
47pub type HsW<'a, REG> = crate::BitWriter<'a, REG, Hs>;
48impl<'a, REG> HsW<'a, REG>
49where
50 REG: crate::Writable + crate::RegisterSpec,
51{
52 #[doc = "High speed conversion mode disabled"]
53 #[inline(always)]
54 pub fn disabled(self) -> &'a mut crate::W<REG> {
55 self.variant(Hs::Disabled)
56 }
57 #[doc = "High speed conversion mode enabled"]
58 #[inline(always)]
59 pub fn enabled(self) -> &'a mut crate::W<REG> {
60 self.variant(Hs::Enabled)
61 }
62}
63#[doc = "High Speed Extra register\n\nValue on reset: 0"]
64#[cfg_attr(feature = "defmt", derive(defmt::Format))]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum Hsextra {
67 #[doc = "0: No extra cycle added"]
68 Hsextra0 = 0,
69 #[doc = "1: Extra cycle added"]
70 Hsextra1 = 1,
71}
72impl From<Hsextra> for bool {
73 #[inline(always)]
74 fn from(variant: Hsextra) -> Self {
75 variant as u8 != 0
76 }
77}
78#[doc = "Field `HSEXTRA` reader - High Speed Extra register"]
79pub type HsextraR = crate::BitReader<Hsextra>;
80impl HsextraR {
81 #[doc = "Get enumerated values variant"]
82 #[inline(always)]
83 pub const fn variant(&self) -> Hsextra {
84 match self.bits {
85 false => Hsextra::Hsextra0,
86 true => Hsextra::Hsextra1,
87 }
88 }
89 #[doc = "No extra cycle added"]
90 #[inline(always)]
91 pub fn is_hsextra_0(&self) -> bool {
92 *self == Hsextra::Hsextra0
93 }
94 #[doc = "Extra cycle added"]
95 #[inline(always)]
96 pub fn is_hsextra_1(&self) -> bool {
97 *self == Hsextra::Hsextra1
98 }
99}
100#[doc = "Field `HSEXTRA` writer - High Speed Extra register"]
101pub type HsextraW<'a, REG> = crate::BitWriter<'a, REG, Hsextra>;
102impl<'a, REG> HsextraW<'a, REG>
103where
104 REG: crate::Writable + crate::RegisterSpec,
105{
106 #[doc = "No extra cycle added"]
107 #[inline(always)]
108 pub fn hsextra_0(self) -> &'a mut crate::W<REG> {
109 self.variant(Hsextra::Hsextra0)
110 }
111 #[doc = "Extra cycle added"]
112 #[inline(always)]
113 pub fn hsextra_1(self) -> &'a mut crate::W<REG> {
114 self.variant(Hsextra::Hsextra1)
115 }
116}
117#[doc = "Field `TUNE` reader - Tune Mode register"]
118pub type TuneR = crate::FieldReader;
119#[doc = "Field `TUNE` writer - Tune Mode register"]
120pub type TuneW<'a, REG> = crate::FieldWriter<'a, REG, 2>;
121impl R {
122 #[doc = "Bit 8 - Justified Left Enable register"]
123 #[inline(always)]
124 pub fn jleft(&self) -> JleftR {
125 JleftR::new(((self.bits >> 8) & 1) != 0)
126 }
127 #[doc = "Bit 9 - High Speed Enable register"]
128 #[inline(always)]
129 pub fn hs(&self) -> HsR {
130 HsR::new(((self.bits >> 9) & 1) != 0)
131 }
132 #[doc = "Bit 10 - High Speed Extra register"]
133 #[inline(always)]
134 pub fn hsextra(&self) -> HsextraR {
135 HsextraR::new(((self.bits >> 10) & 1) != 0)
136 }
137 #[doc = "Bits 12:13 - Tune Mode register"]
138 #[inline(always)]
139 pub fn tune(&self) -> TuneR {
140 TuneR::new(((self.bits >> 12) & 3) as u8)
141 }
142}
143#[cfg(feature = "debug")]
144impl core::fmt::Debug for R {
145 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
146 f.debug_struct("CFG2")
147 .field("jleft", &self.jleft())
148 .field("hs", &self.hs())
149 .field("hsextra", &self.hsextra())
150 .field("tune", &self.tune())
151 .finish()
152 }
153}
154impl W {
155 #[doc = "Bit 8 - Justified Left Enable register"]
156 #[inline(always)]
157 pub fn jleft(&mut self) -> JleftW<'_, Cfg2Spec> {
158 JleftW::new(self, 8)
159 }
160 #[doc = "Bit 9 - High Speed Enable register"]
161 #[inline(always)]
162 pub fn hs(&mut self) -> HsW<'_, Cfg2Spec> {
163 HsW::new(self, 9)
164 }
165 #[doc = "Bit 10 - High Speed Extra register"]
166 #[inline(always)]
167 pub fn hsextra(&mut self) -> HsextraW<'_, Cfg2Spec> {
168 HsextraW::new(self, 10)
169 }
170 #[doc = "Bits 12:13 - Tune Mode register"]
171 #[inline(always)]
172 pub fn tune(&mut self) -> TuneW<'_, Cfg2Spec> {
173 TuneW::new(self, 12)
174 }
175}
176#[doc = "Configuration 2 Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
177pub struct Cfg2Spec;
178impl crate::RegisterSpec for Cfg2Spec {
179 type Ux = u32;
180}
181#[doc = "`read()` method returns [`cfg2::R`](R) reader structure"]
182impl crate::Readable for Cfg2Spec {}
183#[doc = "`write(|w| ..)` method takes [`cfg2::W`](W) writer structure"]
184impl crate::Writable for Cfg2Spec {
185 type Safety = crate::Unsafe;
186}
187#[doc = "`reset()` method sets CFG2 to value 0x1000"]
188impl crate::Resettable for Cfg2Spec {
189 const RESET_VALUE: u32 = 0x1000;
190}