mcxa_pac/adc0/
cfg.rs

1#[doc = "Register `CFG` reader"]
2pub type R = crate::R<CfgSpec>;
3#[doc = "Register `CFG` writer"]
4pub type W = crate::W<CfgSpec>;
5#[doc = "ADC Trigger Priority Control\n\nValue on reset: 0"]
6#[cfg_attr(feature = "defmt", derive(defmt::Format))]
7#[derive(Clone, Copy, Debug, PartialEq, Eq)]
8#[repr(u8)]
9pub enum Tprictrl {
10    #[doc = "0: If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."]
11    AbortCurrentOnPriority = 0,
12    #[doc = "1: If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa\\[LOOP\\] will be ignored and the higher priority trigger will be serviced."]
13    FinishCurrentOnPriority = 1,
14    #[doc = "2: If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger."]
15    FinishSequenceOnPriority = 2,
16}
17impl From<Tprictrl> for u8 {
18    #[inline(always)]
19    fn from(variant: Tprictrl) -> Self {
20        variant as _
21    }
22}
23impl crate::FieldSpec for Tprictrl {
24    type Ux = u8;
25}
26impl crate::IsEnum for Tprictrl {}
27#[doc = "Field `TPRICTRL` reader - ADC Trigger Priority Control"]
28pub type TprictrlR = crate::FieldReader<Tprictrl>;
29impl TprictrlR {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> Option<Tprictrl> {
33        match self.bits {
34            0 => Some(Tprictrl::AbortCurrentOnPriority),
35            1 => Some(Tprictrl::FinishCurrentOnPriority),
36            2 => Some(Tprictrl::FinishSequenceOnPriority),
37            _ => None,
38        }
39    }
40    #[doc = "If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."]
41    #[inline(always)]
42    pub fn is_abort_current_on_priority(&self) -> bool {
43        *self == Tprictrl::AbortCurrentOnPriority
44    }
45    #[doc = "If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa\\[LOOP\\] will be ignored and the higher priority trigger will be serviced."]
46    #[inline(always)]
47    pub fn is_finish_current_on_priority(&self) -> bool {
48        *self == Tprictrl::FinishCurrentOnPriority
49    }
50    #[doc = "If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger."]
51    #[inline(always)]
52    pub fn is_finish_sequence_on_priority(&self) -> bool {
53        *self == Tprictrl::FinishSequenceOnPriority
54    }
55}
56#[doc = "Field `TPRICTRL` writer - ADC Trigger Priority Control"]
57pub type TprictrlW<'a, REG> = crate::FieldWriter<'a, REG, 2, Tprictrl>;
58impl<'a, REG> TprictrlW<'a, REG>
59where
60    REG: crate::Writable + crate::RegisterSpec,
61    REG::Ux: From<u8>,
62{
63    #[doc = "If a higher priority trigger is detected during command processing, the current conversion is aborted and the new command specified by the trigger is started."]
64    #[inline(always)]
65    pub fn abort_current_on_priority(self) -> &'a mut crate::W<REG> {
66        self.variant(Tprictrl::AbortCurrentOnPriority)
67    }
68    #[doc = "If a higher priority trigger is received during command processing, the current command is stopped after completing the current conversion. If averaging is enabled, the averaging loop will be completed. However, CMDHa\\[LOOP\\] will be ignored and the higher priority trigger will be serviced."]
69    #[inline(always)]
70    pub fn finish_current_on_priority(self) -> &'a mut crate::W<REG> {
71        self.variant(Tprictrl::FinishCurrentOnPriority)
72    }
73    #[doc = "If a higher priority trigger is received during command processing, the current command will be completed (averaging, looping, compare) before servicing the higher priority trigger."]
74    #[inline(always)]
75    pub fn finish_sequence_on_priority(self) -> &'a mut crate::W<REG> {
76        self.variant(Tprictrl::FinishSequenceOnPriority)
77    }
78}
79#[doc = "Power Configuration Select\n\nValue on reset: 0"]
80#[cfg_attr(feature = "defmt", derive(defmt::Format))]
81#[derive(Clone, Copy, Debug, PartialEq, Eq)]
82pub enum Pwrsel {
83    #[doc = "0: Low power"]
84    Lowest = 0,
85    #[doc = "1: High power"]
86    Highest = 1,
87}
88impl From<Pwrsel> for bool {
89    #[inline(always)]
90    fn from(variant: Pwrsel) -> Self {
91        variant as u8 != 0
92    }
93}
94#[doc = "Field `PWRSEL` reader - Power Configuration Select"]
95pub type PwrselR = crate::BitReader<Pwrsel>;
96impl PwrselR {
97    #[doc = "Get enumerated values variant"]
98    #[inline(always)]
99    pub const fn variant(&self) -> Pwrsel {
100        match self.bits {
101            false => Pwrsel::Lowest,
102            true => Pwrsel::Highest,
103        }
104    }
105    #[doc = "Low power"]
106    #[inline(always)]
107    pub fn is_lowest(&self) -> bool {
108        *self == Pwrsel::Lowest
109    }
110    #[doc = "High power"]
111    #[inline(always)]
112    pub fn is_highest(&self) -> bool {
113        *self == Pwrsel::Highest
114    }
115}
116#[doc = "Field `PWRSEL` writer - Power Configuration Select"]
117pub type PwrselW<'a, REG> = crate::BitWriter<'a, REG, Pwrsel>;
118impl<'a, REG> PwrselW<'a, REG>
119where
120    REG: crate::Writable + crate::RegisterSpec,
121{
122    #[doc = "Low power"]
123    #[inline(always)]
124    pub fn lowest(self) -> &'a mut crate::W<REG> {
125        self.variant(Pwrsel::Lowest)
126    }
127    #[doc = "High power"]
128    #[inline(always)]
129    pub fn highest(self) -> &'a mut crate::W<REG> {
130        self.variant(Pwrsel::Highest)
131    }
132}
133#[doc = "Voltage Reference Selection\n\nValue on reset: 0"]
134#[cfg_attr(feature = "defmt", derive(defmt::Format))]
135#[derive(Clone, Copy, Debug, PartialEq, Eq)]
136#[repr(u8)]
137pub enum Refsel {
138    #[doc = "0: (Default) Option 1 setting."]
139    Option1 = 0,
140    #[doc = "1: Option 2 setting."]
141    Option2 = 1,
142    #[doc = "2: Option 3 setting."]
143    Option3 = 2,
144}
145impl From<Refsel> for u8 {
146    #[inline(always)]
147    fn from(variant: Refsel) -> Self {
148        variant as _
149    }
150}
151impl crate::FieldSpec for Refsel {
152    type Ux = u8;
153}
154impl crate::IsEnum for Refsel {}
155#[doc = "Field `REFSEL` reader - Voltage Reference Selection"]
156pub type RefselR = crate::FieldReader<Refsel>;
157impl RefselR {
158    #[doc = "Get enumerated values variant"]
159    #[inline(always)]
160    pub const fn variant(&self) -> Option<Refsel> {
161        match self.bits {
162            0 => Some(Refsel::Option1),
163            1 => Some(Refsel::Option2),
164            2 => Some(Refsel::Option3),
165            _ => None,
166        }
167    }
168    #[doc = "(Default) Option 1 setting."]
169    #[inline(always)]
170    pub fn is_option_1(&self) -> bool {
171        *self == Refsel::Option1
172    }
173    #[doc = "Option 2 setting."]
174    #[inline(always)]
175    pub fn is_option_2(&self) -> bool {
176        *self == Refsel::Option2
177    }
178    #[doc = "Option 3 setting."]
179    #[inline(always)]
180    pub fn is_option_3(&self) -> bool {
181        *self == Refsel::Option3
182    }
183}
184#[doc = "Field `REFSEL` writer - Voltage Reference Selection"]
185pub type RefselW<'a, REG> = crate::FieldWriter<'a, REG, 2, Refsel>;
186impl<'a, REG> RefselW<'a, REG>
187where
188    REG: crate::Writable + crate::RegisterSpec,
189    REG::Ux: From<u8>,
190{
191    #[doc = "(Default) Option 1 setting."]
192    #[inline(always)]
193    pub fn option_1(self) -> &'a mut crate::W<REG> {
194        self.variant(Refsel::Option1)
195    }
196    #[doc = "Option 2 setting."]
197    #[inline(always)]
198    pub fn option_2(self) -> &'a mut crate::W<REG> {
199        self.variant(Refsel::Option2)
200    }
201    #[doc = "Option 3 setting."]
202    #[inline(always)]
203    pub fn option_3(self) -> &'a mut crate::W<REG> {
204        self.variant(Refsel::Option3)
205    }
206}
207#[doc = "Trigger Resume Enable\n\nValue on reset: 0"]
208#[cfg_attr(feature = "defmt", derive(defmt::Format))]
209#[derive(Clone, Copy, Debug, PartialEq, Eq)]
210pub enum Tres {
211    #[doc = "0: Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted."]
212    Disabled = 0,
213    #[doc = "1: Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted."]
214    Enabled = 1,
215}
216impl From<Tres> for bool {
217    #[inline(always)]
218    fn from(variant: Tres) -> Self {
219        variant as u8 != 0
220    }
221}
222#[doc = "Field `TRES` reader - Trigger Resume Enable"]
223pub type TresR = crate::BitReader<Tres>;
224impl TresR {
225    #[doc = "Get enumerated values variant"]
226    #[inline(always)]
227    pub const fn variant(&self) -> Tres {
228        match self.bits {
229            false => Tres::Disabled,
230            true => Tres::Enabled,
231        }
232    }
233    #[doc = "Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted."]
234    #[inline(always)]
235    pub fn is_disabled(&self) -> bool {
236        *self == Tres::Disabled
237    }
238    #[doc = "Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted."]
239    #[inline(always)]
240    pub fn is_enabled(&self) -> bool {
241        *self == Tres::Enabled
242    }
243}
244#[doc = "Field `TRES` writer - Trigger Resume Enable"]
245pub type TresW<'a, REG> = crate::BitWriter<'a, REG, Tres>;
246impl<'a, REG> TresW<'a, REG>
247where
248    REG: crate::Writable + crate::RegisterSpec,
249{
250    #[doc = "Trigger sequences interrupted by a high priority trigger exception are not automatically resumed or restarted."]
251    #[inline(always)]
252    pub fn disabled(self) -> &'a mut crate::W<REG> {
253        self.variant(Tres::Disabled)
254    }
255    #[doc = "Trigger sequences interrupted by a high priority trigger exception are automatically resumed or restarted."]
256    #[inline(always)]
257    pub fn enabled(self) -> &'a mut crate::W<REG> {
258        self.variant(Tres::Enabled)
259    }
260}
261#[doc = "Trigger Command Resume\n\nValue on reset: 0"]
262#[cfg_attr(feature = "defmt", derive(defmt::Format))]
263#[derive(Clone, Copy, Debug, PartialEq, Eq)]
264pub enum Tcmdres {
265    #[doc = "0: Trigger sequences interrupted by a high priority trigger exception is automatically restarted."]
266    Disabled = 0,
267    #[doc = "1: Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception."]
268    Enabled = 1,
269}
270impl From<Tcmdres> for bool {
271    #[inline(always)]
272    fn from(variant: Tcmdres) -> Self {
273        variant as u8 != 0
274    }
275}
276#[doc = "Field `TCMDRES` reader - Trigger Command Resume"]
277pub type TcmdresR = crate::BitReader<Tcmdres>;
278impl TcmdresR {
279    #[doc = "Get enumerated values variant"]
280    #[inline(always)]
281    pub const fn variant(&self) -> Tcmdres {
282        match self.bits {
283            false => Tcmdres::Disabled,
284            true => Tcmdres::Enabled,
285        }
286    }
287    #[doc = "Trigger sequences interrupted by a high priority trigger exception is automatically restarted."]
288    #[inline(always)]
289    pub fn is_disabled(&self) -> bool {
290        *self == Tcmdres::Disabled
291    }
292    #[doc = "Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception."]
293    #[inline(always)]
294    pub fn is_enabled(&self) -> bool {
295        *self == Tcmdres::Enabled
296    }
297}
298#[doc = "Field `TCMDRES` writer - Trigger Command Resume"]
299pub type TcmdresW<'a, REG> = crate::BitWriter<'a, REG, Tcmdres>;
300impl<'a, REG> TcmdresW<'a, REG>
301where
302    REG: crate::Writable + crate::RegisterSpec,
303{
304    #[doc = "Trigger sequences interrupted by a high priority trigger exception is automatically restarted."]
305    #[inline(always)]
306    pub fn disabled(self) -> &'a mut crate::W<REG> {
307        self.variant(Tcmdres::Disabled)
308    }
309    #[doc = "Trigger sequences interrupted by a high priority trigger exception is resumed from the command executing before the exception."]
310    #[inline(always)]
311    pub fn enabled(self) -> &'a mut crate::W<REG> {
312        self.variant(Tcmdres::Enabled)
313    }
314}
315#[doc = "High Priority Trigger Exception Disable\n\nValue on reset: 0"]
316#[cfg_attr(feature = "defmt", derive(defmt::Format))]
317#[derive(Clone, Copy, Debug, PartialEq, Eq)]
318pub enum HptExdi {
319    #[doc = "0: High priority trigger exceptions are enabled."]
320    Enabled = 0,
321    #[doc = "1: High priority trigger exceptions are disabled."]
322    Disabled = 1,
323}
324impl From<HptExdi> for bool {
325    #[inline(always)]
326    fn from(variant: HptExdi) -> Self {
327        variant as u8 != 0
328    }
329}
330#[doc = "Field `HPT_EXDI` reader - High Priority Trigger Exception Disable"]
331pub type HptExdiR = crate::BitReader<HptExdi>;
332impl HptExdiR {
333    #[doc = "Get enumerated values variant"]
334    #[inline(always)]
335    pub const fn variant(&self) -> HptExdi {
336        match self.bits {
337            false => HptExdi::Enabled,
338            true => HptExdi::Disabled,
339        }
340    }
341    #[doc = "High priority trigger exceptions are enabled."]
342    #[inline(always)]
343    pub fn is_enabled(&self) -> bool {
344        *self == HptExdi::Enabled
345    }
346    #[doc = "High priority trigger exceptions are disabled."]
347    #[inline(always)]
348    pub fn is_disabled(&self) -> bool {
349        *self == HptExdi::Disabled
350    }
351}
352#[doc = "Field `HPT_EXDI` writer - High Priority Trigger Exception Disable"]
353pub type HptExdiW<'a, REG> = crate::BitWriter<'a, REG, HptExdi>;
354impl<'a, REG> HptExdiW<'a, REG>
355where
356    REG: crate::Writable + crate::RegisterSpec,
357{
358    #[doc = "High priority trigger exceptions are enabled."]
359    #[inline(always)]
360    pub fn enabled(self) -> &'a mut crate::W<REG> {
361        self.variant(HptExdi::Enabled)
362    }
363    #[doc = "High priority trigger exceptions are disabled."]
364    #[inline(always)]
365    pub fn disabled(self) -> &'a mut crate::W<REG> {
366        self.variant(HptExdi::Disabled)
367    }
368}
369#[doc = "Field `PUDLY` reader - Power Up Delay"]
370pub type PudlyR = crate::FieldReader;
371#[doc = "Field `PUDLY` writer - Power Up Delay"]
372pub type PudlyW<'a, REG> = crate::FieldWriter<'a, REG, 8>;
373#[doc = "ADC Analog Pre-Enable\n\nValue on reset: 0"]
374#[cfg_attr(feature = "defmt", derive(defmt::Format))]
375#[derive(Clone, Copy, Debug, PartialEq, Eq)]
376pub enum Pwren {
377    #[doc = "0: ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays."]
378    NotPreEnabled = 0,
379    #[doc = "1: ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). Note that a single power up delay (CFG\\[PUDLY\\]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog remains pre-enabled and no additional delays are executed."]
380    PreEnabled = 1,
381}
382impl From<Pwren> for bool {
383    #[inline(always)]
384    fn from(variant: Pwren) -> Self {
385        variant as u8 != 0
386    }
387}
388#[doc = "Field `PWREN` reader - ADC Analog Pre-Enable"]
389pub type PwrenR = crate::BitReader<Pwren>;
390impl PwrenR {
391    #[doc = "Get enumerated values variant"]
392    #[inline(always)]
393    pub const fn variant(&self) -> Pwren {
394        match self.bits {
395            false => Pwren::NotPreEnabled,
396            true => Pwren::PreEnabled,
397        }
398    }
399    #[doc = "ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays."]
400    #[inline(always)]
401    pub fn is_not_pre_enabled(&self) -> bool {
402        *self == Pwren::NotPreEnabled
403    }
404    #[doc = "ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). Note that a single power up delay (CFG\\[PUDLY\\]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog remains pre-enabled and no additional delays are executed."]
405    #[inline(always)]
406    pub fn is_pre_enabled(&self) -> bool {
407        *self == Pwren::PreEnabled
408    }
409}
410#[doc = "Field `PWREN` writer - ADC Analog Pre-Enable"]
411pub type PwrenW<'a, REG> = crate::BitWriter<'a, REG, Pwren>;
412impl<'a, REG> PwrenW<'a, REG>
413where
414    REG: crate::Writable + crate::RegisterSpec,
415{
416    #[doc = "ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays."]
417    #[inline(always)]
418    pub fn not_pre_enabled(self) -> &'a mut crate::W<REG> {
419        self.variant(Pwren::NotPreEnabled)
420    }
421    #[doc = "ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost of higher DC current consumption). Note that a single power up delay (CFG\\[PUDLY\\]) is executed immediately once PWREN is set, and any detected trigger does not begin ADC operation until the power up delay time has passed. After this initial delay expires the analog remains pre-enabled and no additional delays are executed."]
422    #[inline(always)]
423    pub fn pre_enabled(self) -> &'a mut crate::W<REG> {
424        self.variant(Pwren::PreEnabled)
425    }
426}
427impl R {
428    #[doc = "Bits 0:1 - ADC Trigger Priority Control"]
429    #[inline(always)]
430    pub fn tprictrl(&self) -> TprictrlR {
431        TprictrlR::new((self.bits & 3) as u8)
432    }
433    #[doc = "Bit 5 - Power Configuration Select"]
434    #[inline(always)]
435    pub fn pwrsel(&self) -> PwrselR {
436        PwrselR::new(((self.bits >> 5) & 1) != 0)
437    }
438    #[doc = "Bits 6:7 - Voltage Reference Selection"]
439    #[inline(always)]
440    pub fn refsel(&self) -> RefselR {
441        RefselR::new(((self.bits >> 6) & 3) as u8)
442    }
443    #[doc = "Bit 8 - Trigger Resume Enable"]
444    #[inline(always)]
445    pub fn tres(&self) -> TresR {
446        TresR::new(((self.bits >> 8) & 1) != 0)
447    }
448    #[doc = "Bit 9 - Trigger Command Resume"]
449    #[inline(always)]
450    pub fn tcmdres(&self) -> TcmdresR {
451        TcmdresR::new(((self.bits >> 9) & 1) != 0)
452    }
453    #[doc = "Bit 10 - High Priority Trigger Exception Disable"]
454    #[inline(always)]
455    pub fn hpt_exdi(&self) -> HptExdiR {
456        HptExdiR::new(((self.bits >> 10) & 1) != 0)
457    }
458    #[doc = "Bits 16:23 - Power Up Delay"]
459    #[inline(always)]
460    pub fn pudly(&self) -> PudlyR {
461        PudlyR::new(((self.bits >> 16) & 0xff) as u8)
462    }
463    #[doc = "Bit 28 - ADC Analog Pre-Enable"]
464    #[inline(always)]
465    pub fn pwren(&self) -> PwrenR {
466        PwrenR::new(((self.bits >> 28) & 1) != 0)
467    }
468}
469#[cfg(feature = "debug")]
470impl core::fmt::Debug for R {
471    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
472        f.debug_struct("CFG")
473            .field("tprictrl", &self.tprictrl())
474            .field("pwrsel", &self.pwrsel())
475            .field("refsel", &self.refsel())
476            .field("tres", &self.tres())
477            .field("tcmdres", &self.tcmdres())
478            .field("hpt_exdi", &self.hpt_exdi())
479            .field("pudly", &self.pudly())
480            .field("pwren", &self.pwren())
481            .finish()
482    }
483}
484impl W {
485    #[doc = "Bits 0:1 - ADC Trigger Priority Control"]
486    #[inline(always)]
487    pub fn tprictrl(&mut self) -> TprictrlW<'_, CfgSpec> {
488        TprictrlW::new(self, 0)
489    }
490    #[doc = "Bit 5 - Power Configuration Select"]
491    #[inline(always)]
492    pub fn pwrsel(&mut self) -> PwrselW<'_, CfgSpec> {
493        PwrselW::new(self, 5)
494    }
495    #[doc = "Bits 6:7 - Voltage Reference Selection"]
496    #[inline(always)]
497    pub fn refsel(&mut self) -> RefselW<'_, CfgSpec> {
498        RefselW::new(self, 6)
499    }
500    #[doc = "Bit 8 - Trigger Resume Enable"]
501    #[inline(always)]
502    pub fn tres(&mut self) -> TresW<'_, CfgSpec> {
503        TresW::new(self, 8)
504    }
505    #[doc = "Bit 9 - Trigger Command Resume"]
506    #[inline(always)]
507    pub fn tcmdres(&mut self) -> TcmdresW<'_, CfgSpec> {
508        TcmdresW::new(self, 9)
509    }
510    #[doc = "Bit 10 - High Priority Trigger Exception Disable"]
511    #[inline(always)]
512    pub fn hpt_exdi(&mut self) -> HptExdiW<'_, CfgSpec> {
513        HptExdiW::new(self, 10)
514    }
515    #[doc = "Bits 16:23 - Power Up Delay"]
516    #[inline(always)]
517    pub fn pudly(&mut self) -> PudlyW<'_, CfgSpec> {
518        PudlyW::new(self, 16)
519    }
520    #[doc = "Bit 28 - ADC Analog Pre-Enable"]
521    #[inline(always)]
522    pub fn pwren(&mut self) -> PwrenW<'_, CfgSpec> {
523        PwrenW::new(self, 28)
524    }
525}
526#[doc = "Configuration Register\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
527pub struct CfgSpec;
528impl crate::RegisterSpec for CfgSpec {
529    type Ux = u32;
530}
531#[doc = "`read()` method returns [`cfg::R`](R) reader structure"]
532impl crate::Readable for CfgSpec {}
533#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"]
534impl crate::Writable for CfgSpec {
535    type Safety = crate::Unsafe;
536}
537#[doc = "`reset()` method sets CFG to value 0x0080_0000"]
538impl crate::Resettable for CfgSpec {
539    const RESET_VALUE: u32 = 0x0080_0000;
540}
mcxa_pac/adc0/cfg.rs

mcxa_pac/adc0/
cfg.rs
