mcan/
reg.rs

1//! Low-level access to peripheral registers
2
3#![allow(non_camel_case_types)]
4pub mod generic;
5
6/// Blanket implementation trait that provides convenience method for recasting
7/// the pointer type to specific [`RegisterBlock`] type.
8///
9/// This is necessary, as [`mcan_core::CanId`] and [`mcan_core`] itself does not
10/// know the concrete low-level access type definition.
11pub trait AccessRegisterBlock {
12    /// Returns a raw pointer to the peripheral registers
13    fn register_block() -> *const RegisterBlock;
14}
15
16impl<T: mcan_core::CanId> AccessRegisterBlock for T {
17    fn register_block() -> *const RegisterBlock {
18        T::ADDRESS as *const _
19    }
20}
21
22/// Provides raw register access
23pub struct Can<Id>(core::marker::PhantomData<(*const (), Id)>);
24
25unsafe impl<Id> Send for Can<Id> {}
26
27impl<Id> Can<Id> {
28    /// # Safety
29    /// Constructing multiple `Can` instances with the same `Id` will lead to
30    /// aliasing of `RegisterBlock`
31    pub unsafe fn new() -> Self {
32        Self(core::marker::PhantomData)
33    }
34}
35
36impl<Id: mcan_core::CanId> Can<Id> {
37    fn set_init(&self, value: bool) {
38        // Ensure the peripheral leaves the "power down" mode properly if it was
39        // previously entered.
40        if !value {
41            self.cccr.modify(|_, w| w.csr().clear_bit());
42            while self.cccr.read().csa().bit_is_set() {}
43        }
44
45        self.cccr.modify(|_, w| w.init().bit(value));
46        while self.cccr.read().init().bit() != value {}
47    }
48
49    fn enable_cce(&self) {
50        self.cccr.modify(|_, w| w.cce().set_bit());
51        while !self.cccr.read().cce().bit() {}
52    }
53
54    pub(crate) fn configuration_mode(&self) {
55        self.set_init(true);
56        self.enable_cce();
57    }
58
59    pub(crate) fn initialization_mode(&self) {
60        self.set_init(true);
61    }
62
63    pub(crate) fn operational_mode(&self) {
64        self.set_init(false);
65    }
66
67    pub(crate) fn is_operational(&self) -> bool {
68        self.cccr.read().init().bit_is_clear()
69    }
70}
71
72impl<Id: mcan_core::CanId> core::ops::Deref for Can<Id> {
73    type Target = RegisterBlock;
74    #[inline(always)]
75    fn deref(&self) -> &Self::Target {
76        unsafe { &*Id::register_block() }
77    }
78}
79
80#[doc = r"Register block"]
81#[repr(C)]
82pub struct RegisterBlock {
83    #[doc = "0x00 - Core Release"]
84    pub crel: crate::Reg<crel::CREL_SPEC>,
85    #[doc = "0x04 - Endian"]
86    pub endn: crate::Reg<endn::ENDN_SPEC>,
87    #[doc = "0x08 - Customer Register"]
88    pub cust: crate::Reg<cust::CUST_SPEC>,
89    #[doc = "0x0c - Fast Bit Timing and Prescaler"]
90    pub dbtp: crate::Reg<dbtp::DBTP_SPEC>,
91    #[doc = "0x10 - Test"]
92    pub test: crate::Reg<test::TEST_SPEC>,
93    #[doc = "0x14 - RAM Watchdog"]
94    pub rwd: crate::Reg<rwd::RWD_SPEC>,
95    #[doc = "0x18 - CC Control"]
96    pub cccr: crate::Reg<cccr::CCCR_SPEC>,
97    #[doc = "0x1c - Nominal Bit Timing and Prescaler"]
98    pub nbtp: crate::Reg<nbtp::NBTP_SPEC>,
99    #[doc = "0x20 - Timestamp Counter Configuration"]
100    pub tscc: crate::Reg<tscc::TSCC_SPEC>,
101    #[doc = "0x24 - Timestamp Counter Value"]
102    pub tscv: crate::Reg<tscv::TSCV_SPEC>,
103    #[doc = "0x28 - Timeout Counter Configuration"]
104    pub tocc: crate::Reg<tocc::TOCC_SPEC>,
105    #[doc = "0x2c - Timeout Counter Value"]
106    pub tocv: crate::Reg<tocv::TOCV_SPEC>,
107    _reserved12: [u8; 0x10],
108    #[doc = "0x40 - Error Counter"]
109    pub ecr: crate::Reg<ecr::ECR_SPEC>,
110    #[doc = "0x44 - Protocol Status"]
111    pub psr: crate::Reg<psr::PSR_SPEC>,
112    #[doc = "0x48 - Transmitter Delay Compensation"]
113    pub tdcr: crate::Reg<tdcr::TDCR_SPEC>,
114    _reserved15: [u8; 0x04],
115    #[doc = "0x50 - Interrupt"]
116    pub ir: crate::Reg<ir::IR_SPEC>,
117    #[doc = "0x54 - Interrupt Enable"]
118    pub ie: crate::Reg<ie::IE_SPEC>,
119    #[doc = "0x58 - Interrupt Line Select"]
120    pub ils: crate::Reg<ils::ILS_SPEC>,
121    #[doc = "0x5c - Interrupt Line Enable"]
122    pub ile: crate::Reg<ile::ILE_SPEC>,
123    _reserved19: [u8; 0x20],
124    #[doc = "0x80 - Global Filter Configuration"]
125    pub gfc: crate::Reg<gfc::GFC_SPEC>,
126    #[doc = "0x84 - Standard ID Filter Configuration"]
127    pub sidfc: crate::Reg<sidfc::SIDFC_SPEC>,
128    #[doc = "0x88 - Extended ID Filter Configuration"]
129    pub xidfc: crate::Reg<xidfc::XIDFC_SPEC>,
130    _reserved22: [u8; 0x04],
131    #[doc = "0x90 - Extended ID AND Mask"]
132    pub xidam: crate::Reg<xidam::XIDAM_SPEC>,
133    #[doc = "0x94 - High Priority Message Status"]
134    pub hpms: crate::Reg<hpms::HPMS_SPEC>,
135    #[doc = "0x98 - New Data 1"]
136    pub ndat1: crate::Reg<ndat1::NDAT1_SPEC>,
137    #[doc = "0x9c - New Data 2"]
138    pub ndat2: crate::Reg<ndat2::NDAT2_SPEC>,
139    #[doc = "0xa0 - Rx FIFO 0 registers"]
140    pub rxf0: RxFifoRegs,
141    #[doc = "0xac - Rx Buffer Configuration"]
142    pub rxbc: crate::Reg<rxbc::RXBC_SPEC>,
143    #[doc = "0xb0 - Rx FIFO 1 registers"]
144    pub rxf1: RxFifoRegs,
145    #[doc = "0xbc - Rx Buffer / FIFO Element Size Configuration"]
146    pub rxesc: crate::Reg<rxesc::RXESC_SPEC>,
147    #[doc = "0xc0 - Tx Buffer Configuration"]
148    pub txbc: crate::Reg<txbc::TXBC_SPEC>,
149    #[doc = "0xc4 - Tx FIFO / Queue Status"]
150    pub txfqs: crate::Reg<txfqs::TXFQS_SPEC>,
151    #[doc = "0xc8 - Tx Buffer Element Size Configuration"]
152    pub txesc: crate::Reg<txesc::TXESC_SPEC>,
153    #[doc = "0xcc - Tx Buffer Request Pending"]
154    pub txbrp: crate::Reg<txbrp::TXBRP_SPEC>,
155    #[doc = "0xd0 - Tx Buffer Add Request"]
156    pub txbar: crate::Reg<txbar::TXBAR_SPEC>,
157    #[doc = "0xd4 - Tx Buffer Cancellation Request"]
158    pub txbcr: crate::Reg<txbcr::TXBCR_SPEC>,
159    #[doc = "0xd8 - Tx Buffer Transmission Occurred"]
160    pub txbto: crate::Reg<txbto::TXBTO_SPEC>,
161    #[doc = "0xdc - Tx Buffer Cancellation Finished"]
162    pub txbcf: crate::Reg<txbcf::TXBCF_SPEC>,
163    #[doc = "0xe0 - Tx Buffer Transmission Interrupt Enable"]
164    pub txbtie: crate::Reg<txbtie::TXBTIE_SPEC>,
165    #[doc = "0xe4 - Tx Buffer Cancellation Finished Interrupt Enable"]
166    pub txbcie: crate::Reg<txbcie::TXBCIE_SPEC>,
167    _reserved44: [u8; 0x08],
168    #[doc = "0xf0 - Tx Event FIFO Configuration"]
169    pub txefc: crate::Reg<txefc::TXEFC_SPEC>,
170    #[doc = "0xf4 - Tx Event FIFO Status"]
171    pub txefs: crate::Reg<txefs::TXEFS_SPEC>,
172    #[doc = "0xf8 - Tx Event FIFO Acknowledge"]
173    pub txefa: crate::Reg<txefa::TXEFA_SPEC>,
174}
175
176/// Group of receive FIFO registers
177#[repr(C)]
178pub struct RxFifoRegs {
179    #[doc = "Rx FIFO Configuration"]
180    pub c: crate::Reg<rxfc::RXFC_SPEC>,
181    #[doc = "Rx FIFO Status"]
182    pub s: crate::Reg<rxfs::RXFS_SPEC>,
183    #[doc = "Rx FIFO Acknowledge"]
184    pub a: crate::Reg<rxfa::RXFA_SPEC>,
185}
186
187#[doc = "CREL register accessor: an alias for `Reg<CREL_SPEC>`"]
188pub type CREL = crate::Reg<crel::CREL_SPEC>;
189#[doc = "Core Release"]
190pub mod crel;
191#[doc = "ENDN register accessor: an alias for `Reg<ENDN_SPEC>`"]
192pub type ENDN = crate::Reg<endn::ENDN_SPEC>;
193#[doc = "Endian"]
194pub mod endn;
195#[doc = "CUST register accessor: an alias for `Reg<CUST_SPEC>`"]
196pub type CUST = crate::Reg<cust::CUST_SPEC>;
197#[doc = "Customer Register"]
198pub mod cust;
199#[doc = "DBTP register accessor: an alias for `Reg<DBTP_SPEC>`"]
200pub type DBTP = crate::Reg<dbtp::DBTP_SPEC>;
201#[doc = "Fast Bit Timing and Prescaler"]
202pub mod dbtp;
203#[doc = "TEST register accessor: an alias for `Reg<TEST_SPEC>`"]
204pub type TEST = crate::Reg<test::TEST_SPEC>;
205#[doc = "Test"]
206pub mod test;
207#[doc = "RWD register accessor: an alias for `Reg<RWD_SPEC>`"]
208pub type RWD = crate::Reg<rwd::RWD_SPEC>;
209#[doc = "RAM Watchdog"]
210pub mod rwd;
211#[doc = "CCCR register accessor: an alias for `Reg<CCCR_SPEC>`"]
212pub type CCCR = crate::Reg<cccr::CCCR_SPEC>;
213#[doc = "CC Control"]
214pub mod cccr;
215#[doc = "NBTP register accessor: an alias for `Reg<NBTP_SPEC>`"]
216pub type NBTP = crate::Reg<nbtp::NBTP_SPEC>;
217#[doc = "Nominal Bit Timing and Prescaler"]
218pub mod nbtp;
219#[doc = "TSCC register accessor: an alias for `Reg<TSCC_SPEC>`"]
220pub type TSCC = crate::Reg<tscc::TSCC_SPEC>;
221#[doc = "Timestamp Counter Configuration"]
222pub mod tscc;
223#[doc = "TSCV register accessor: an alias for `Reg<TSCV_SPEC>`"]
224pub type TSCV = crate::Reg<tscv::TSCV_SPEC>;
225#[doc = "Timestamp Counter Value"]
226pub mod tscv;
227#[doc = "TOCC register accessor: an alias for `Reg<TOCC_SPEC>`"]
228pub type TOCC = crate::Reg<tocc::TOCC_SPEC>;
229#[doc = "Timeout Counter Configuration"]
230pub mod tocc;
231#[doc = "TOCV register accessor: an alias for `Reg<TOCV_SPEC>`"]
232pub type TOCV = crate::Reg<tocv::TOCV_SPEC>;
233#[doc = "Timeout Counter Value"]
234pub mod tocv;
235#[doc = "ECR register accessor: an alias for `Reg<ECR_SPEC>`"]
236pub type ECR = crate::Reg<ecr::ECR_SPEC>;
237#[doc = "Error Counter"]
238pub mod ecr;
239#[doc = "PSR register accessor: an alias for `Reg<PSR_SPEC>`"]
240pub type PSR = crate::Reg<psr::PSR_SPEC>;
241#[doc = "Protocol Status"]
242pub mod psr;
243#[doc = "TDCR register accessor: an alias for `Reg<TDCR_SPEC>`"]
244pub type TDCR = crate::Reg<tdcr::TDCR_SPEC>;
245#[doc = "Extended ID Filter Configuration"]
246pub mod tdcr;
247#[doc = "IR register accessor: an alias for `Reg<IR_SPEC>`"]
248pub type IR = crate::Reg<ir::IR_SPEC>;
249#[doc = "Interrupt"]
250pub mod ir;
251#[doc = "IE register accessor: an alias for `Reg<IE_SPEC>`"]
252pub type IE = crate::Reg<ie::IE_SPEC>;
253#[doc = "Interrupt Enable"]
254pub mod ie;
255#[doc = "ILS register accessor: an alias for `Reg<ILS_SPEC>`"]
256pub type ILS = crate::Reg<ils::ILS_SPEC>;
257#[doc = "Interrupt Line Select"]
258pub mod ils;
259#[doc = "ILE register accessor: an alias for `Reg<ILE_SPEC>`"]
260pub type ILE = crate::Reg<ile::ILE_SPEC>;
261#[doc = "Interrupt Line Enable"]
262pub mod ile;
263#[doc = "GFC register accessor: an alias for `Reg<GFC_SPEC>`"]
264pub type GFC = crate::Reg<gfc::GFC_SPEC>;
265#[doc = "Global Filter Configuration"]
266pub mod gfc;
267#[doc = "SIDFC register accessor: an alias for `Reg<SIDFC_SPEC>`"]
268pub type SIDFC = crate::Reg<sidfc::SIDFC_SPEC>;
269#[doc = "Standard ID Filter Configuration"]
270pub mod sidfc;
271#[doc = "XIDFC register accessor: an alias for `Reg<XIDFC_SPEC>`"]
272pub type XIDFC = crate::Reg<xidfc::XIDFC_SPEC>;
273#[doc = "Extended ID Filter Configuration"]
274pub mod xidfc;
275#[doc = "XIDAM register accessor: an alias for `Reg<XIDAM_SPEC>`"]
276pub type XIDAM = crate::Reg<xidam::XIDAM_SPEC>;
277#[doc = "Extended ID AND Mask"]
278pub mod xidam;
279#[doc = "HPMS register accessor: an alias for `Reg<HPMS_SPEC>`"]
280pub type HPMS = crate::Reg<hpms::HPMS_SPEC>;
281#[doc = "High Priority Message Status"]
282pub mod hpms;
283#[doc = "NDAT1 register accessor: an alias for `Reg<NDAT1_SPEC>`"]
284pub type NDAT1 = crate::Reg<ndat1::NDAT1_SPEC>;
285#[doc = "New Data 1"]
286pub mod ndat1;
287#[doc = "NDAT2 register accessor: an alias for `Reg<NDAT2_SPEC>`"]
288pub type NDAT2 = crate::Reg<ndat2::NDAT2_SPEC>;
289#[doc = "New Data 2"]
290pub mod ndat2;
291#[doc = "RXFC register accessor: an alias for `Reg<RXFC_SPEC>`"]
292pub type RXFC = crate::Reg<rxfc::RXFC_SPEC>;
293#[doc = "Rx FIFO Configuration"]
294pub mod rxfc;
295#[doc = "RXFS register accessor: an alias for `Reg<RXFS_SPEC>`"]
296pub type RXFS = crate::Reg<rxfs::RXFS_SPEC>;
297#[doc = "Rx FIFO Status"]
298pub mod rxfs;
299#[doc = "RXFA register accessor: an alias for `Reg<RXFA_SPEC>`"]
300pub type RXFA = crate::Reg<rxfa::RXFA_SPEC>;
301#[doc = "Rx FIFO Acknowledge"]
302pub mod rxfa;
303#[doc = "RXBC register accessor: an alias for `Reg<RXBC_SPEC>`"]
304pub type RXBC = crate::Reg<rxbc::RXBC_SPEC>;
305#[doc = "Rx Buffer Configuration"]
306pub mod rxbc;
307#[doc = "RXESC register accessor: an alias for `Reg<RXESC_SPEC>`"]
308pub type RXESC = crate::Reg<rxesc::RXESC_SPEC>;
309#[doc = "Rx Buffer / FIFO Element Size Configuration"]
310pub mod rxesc;
311#[doc = "TXBC register accessor: an alias for `Reg<TXBC_SPEC>`"]
312pub type TXBC = crate::Reg<txbc::TXBC_SPEC>;
313#[doc = "Tx Buffer Configuration"]
314pub mod txbc;
315#[doc = "TXFQS register accessor: an alias for `Reg<TXFQS_SPEC>`"]
316pub type TXFQS = crate::Reg<txfqs::TXFQS_SPEC>;
317#[doc = "Tx FIFO / Queue Status"]
318pub mod txfqs;
319#[doc = "TXESC register accessor: an alias for `Reg<TXESC_SPEC>`"]
320pub type TXESC = crate::Reg<txesc::TXESC_SPEC>;
321#[doc = "Tx Buffer Element Size Configuration"]
322pub mod txesc;
323#[doc = "TXBRP register accessor: an alias for `Reg<TXBRP_SPEC>`"]
324pub type TXBRP = crate::Reg<txbrp::TXBRP_SPEC>;
325#[doc = "Tx Buffer Request Pending"]
326pub mod txbrp;
327#[doc = "TXBAR register accessor: an alias for `Reg<TXBAR_SPEC>`"]
328pub type TXBAR = crate::Reg<txbar::TXBAR_SPEC>;
329#[doc = "Tx Buffer Add Request"]
330pub mod txbar;
331#[doc = "TXBCR register accessor: an alias for `Reg<TXBCR_SPEC>`"]
332pub type TXBCR = crate::Reg<txbcr::TXBCR_SPEC>;
333#[doc = "Tx Buffer Cancellation Request"]
334pub mod txbcr;
335#[doc = "TXBTO register accessor: an alias for `Reg<TXBTO_SPEC>`"]
336pub type TXBTO = crate::Reg<txbto::TXBTO_SPEC>;
337#[doc = "Tx Buffer Transmission Occurred"]
338pub mod txbto;
339#[doc = "TXBCF register accessor: an alias for `Reg<TXBCF_SPEC>`"]
340pub type TXBCF = crate::Reg<txbcf::TXBCF_SPEC>;
341#[doc = "Tx Buffer Cancellation Finished"]
342pub mod txbcf;
343#[doc = "TXBTIE register accessor: an alias for `Reg<TXBTIE_SPEC>`"]
344pub type TXBTIE = crate::Reg<txbtie::TXBTIE_SPEC>;
345#[doc = "Tx Buffer Transmission Interrupt Enable"]
346pub mod txbtie;
347#[doc = "TXBCIE register accessor: an alias for `Reg<TXBCIE_SPEC>`"]
348pub type TXBCIE = crate::Reg<txbcie::TXBCIE_SPEC>;
349#[doc = "Tx Buffer Cancellation Finished Interrupt Enable"]
350pub mod txbcie;
351#[doc = "TXEFC register accessor: an alias for `Reg<TXEFC_SPEC>`"]
352pub type TXEFC = crate::Reg<txefc::TXEFC_SPEC>;
353#[doc = "Tx Event FIFO Configuration"]
354pub mod txefc;
355#[doc = "TXEFS register accessor: an alias for `Reg<TXEFS_SPEC>`"]
356pub type TXEFS = crate::Reg<txefs::TXEFS_SPEC>;
357#[doc = "Tx Event FIFO Status"]
358pub mod txefs;
359#[doc = "TXEFA register accessor: an alias for `Reg<TXEFA_SPEC>`"]
360pub type TXEFA = crate::Reg<txefa::TXEFA_SPEC>;
361#[doc = "Tx Event FIFO Acknowledge"]
362pub mod txefa;
mcan/reg.rs

mcan/
reg.rs
