mc6809_core/
memory.rs

1//   Copyright 2026 Martin Åkesson
2//
3//   Licensed under the Apache License, Version 2.0 (the "License");
4//   you may not use this file except in compliance with the License.
5//   You may obtain a copy of the License at
6//
7//       http://www.apache.org/licenses/LICENSE-2.0
8//
9//   Unless required by applicable law or agreed to in writing, software
10//   distributed under the License is distributed on an "AS IS" BASIS,
11//   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12//   See the License for the specific language governing permissions and
13//   limitations under the License.
14
15/// Memory trait for the 6809 CPU.
16///
17/// Implement this trait to provide the CPU with access to memory and I/O.
18/// The 6809 has a 16-bit address bus (64KB address space) and an 8-bit data bus.
19/// Re-implementations of word read/write methods must use big-endian byte order
20/// (high byte at `addr`, low byte at `addr + 1`).
21pub trait Memory {
22    /// Read a byte from the given address.
23    fn read(&mut self, addr: u16) -> u8;
24
25    /// Write a byte to the given address.
26    fn write(&mut self, addr: u16, val: u8);
27
28    /// Read a big-endian 16-bit word (high byte at `addr`, low byte at `addr + 1`).
29    fn read_word(&mut self, addr: u16) -> u16 {
30        let hi = self.read(addr) as u16;
31        let lo = self.read(addr.wrapping_add(1)) as u16;
32        (hi << 8) | lo
33    }
34
35    /// Write a big-endian 16-bit word (high byte at `addr`, low byte at `addr + 1`).
36    fn write_word(&mut self, addr: u16, val: u16) {
37        self.write(addr, (val >> 8) as u8);
38        self.write(addr.wrapping_add(1), val as u8);
39    }
40}
mc6809_core/memory.rs

mc6809_core/
memory.rs
