max78000_pac/spi0/
clkctrl.rs

1#[doc = "Register `CLKCTRL` reader"]
2pub type R = crate::R<ClkctrlSpec>;
3#[doc = "Register `CLKCTRL` writer"]
4pub type W = crate::W<ClkctrlSpec>;
5#[doc = "Low duty cycle control. In timer mode, reload\\[7:0\\].\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Lo {
9    #[doc = "0: Duty cycle control of serial clock generation is disabled."]
10    Dis = 0,
11}
12impl From<Lo> for u8 {
13    #[inline(always)]
14    fn from(variant: Lo) -> Self {
15        variant as _
16    }
17}
18impl crate::FieldSpec for Lo {
19    type Ux = u8;
20}
21impl crate::IsEnum for Lo {}
22#[doc = "Field `LO` reader - Low duty cycle control. In timer mode, reload\\[7:0\\]."]
23pub type LoR = crate::FieldReader<Lo>;
24impl LoR {
25    #[doc = "Get enumerated values variant"]
26    #[inline(always)]
27    pub const fn variant(&self) -> Option<Lo> {
28        match self.bits {
29            0 => Some(Lo::Dis),
30            _ => None,
31        }
32    }
33    #[doc = "Duty cycle control of serial clock generation is disabled."]
34    #[inline(always)]
35    pub fn is_dis(&self) -> bool {
36        *self == Lo::Dis
37    }
38}
39#[doc = "Field `LO` writer - Low duty cycle control. In timer mode, reload\\[7:0\\]."]
40pub type LoW<'a, REG> = crate::FieldWriter<'a, REG, 8, Lo>;
41impl<'a, REG> LoW<'a, REG>
42where
43    REG: crate::Writable + crate::RegisterSpec,
44    REG::Ux: From<u8>,
45{
46    #[doc = "Duty cycle control of serial clock generation is disabled."]
47    #[inline(always)]
48    pub fn dis(self) -> &'a mut crate::W<REG> {
49        self.variant(Lo::Dis)
50    }
51}
52#[doc = "High duty cycle control. In timer mode, reload\\[15:8\\].\n\nValue on reset: 0"]
53#[derive(Clone, Copy, Debug, PartialEq, Eq)]
54#[repr(u8)]
55pub enum Hi {
56    #[doc = "0: Duty cycle control of serial clock generation is disabled."]
57    Dis = 0,
58}
59impl From<Hi> for u8 {
60    #[inline(always)]
61    fn from(variant: Hi) -> Self {
62        variant as _
63    }
64}
65impl crate::FieldSpec for Hi {
66    type Ux = u8;
67}
68impl crate::IsEnum for Hi {}
69#[doc = "Field `HI` reader - High duty cycle control. In timer mode, reload\\[15:8\\]."]
70pub type HiR = crate::FieldReader<Hi>;
71impl HiR {
72    #[doc = "Get enumerated values variant"]
73    #[inline(always)]
74    pub const fn variant(&self) -> Option<Hi> {
75        match self.bits {
76            0 => Some(Hi::Dis),
77            _ => None,
78        }
79    }
80    #[doc = "Duty cycle control of serial clock generation is disabled."]
81    #[inline(always)]
82    pub fn is_dis(&self) -> bool {
83        *self == Hi::Dis
84    }
85}
86#[doc = "Field `HI` writer - High duty cycle control. In timer mode, reload\\[15:8\\]."]
87pub type HiW<'a, REG> = crate::FieldWriter<'a, REG, 8, Hi>;
88impl<'a, REG> HiW<'a, REG>
89where
90    REG: crate::Writable + crate::RegisterSpec,
91    REG::Ux: From<u8>,
92{
93    #[doc = "Duty cycle control of serial clock generation is disabled."]
94    #[inline(always)]
95    pub fn dis(self) -> &'a mut crate::W<REG> {
96        self.variant(Hi::Dis)
97    }
98}
99#[doc = "Field `CLKDIV` reader - System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."]
100pub type ClkdivR = crate::FieldReader;
101#[doc = "Field `CLKDIV` writer - System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."]
102pub type ClkdivW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
103impl R {
104    #[doc = "Bits 0:7 - Low duty cycle control. In timer mode, reload\\[7:0\\]."]
105    #[inline(always)]
106    pub fn lo(&self) -> LoR {
107        LoR::new((self.bits & 0xff) as u8)
108    }
109    #[doc = "Bits 8:15 - High duty cycle control. In timer mode, reload\\[15:8\\]."]
110    #[inline(always)]
111    pub fn hi(&self) -> HiR {
112        HiR::new(((self.bits >> 8) & 0xff) as u8)
113    }
114    #[doc = "Bits 16:19 - System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."]
115    #[inline(always)]
116    pub fn clkdiv(&self) -> ClkdivR {
117        ClkdivR::new(((self.bits >> 16) & 0x0f) as u8)
118    }
119}
120impl W {
121    #[doc = "Bits 0:7 - Low duty cycle control. In timer mode, reload\\[7:0\\]."]
122    #[inline(always)]
123    pub fn lo(&mut self) -> LoW<ClkctrlSpec> {
124        LoW::new(self, 0)
125    }
126    #[doc = "Bits 8:15 - High duty cycle control. In timer mode, reload\\[15:8\\]."]
127    #[inline(always)]
128    pub fn hi(&mut self) -> HiW<ClkctrlSpec> {
129        HiW::new(self, 8)
130    }
131    #[doc = "Bits 16:19 - System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock."]
132    #[inline(always)]
133    pub fn clkdiv(&mut self) -> ClkdivW<ClkctrlSpec> {
134        ClkdivW::new(self, 16)
135    }
136}
137#[doc = "Register for controlling SPI clock rate.\n\nYou can [`read`](crate::Reg::read) this register and get [`clkctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
138pub struct ClkctrlSpec;
139impl crate::RegisterSpec for ClkctrlSpec {
140    type Ux = u32;
141}
142#[doc = "`read()` method returns [`clkctrl::R`](R) reader structure"]
143impl crate::Readable for ClkctrlSpec {}
144#[doc = "`write(|w| ..)` method takes [`clkctrl::W`](W) writer structure"]
145impl crate::Writable for ClkctrlSpec {
146    type Safety = crate::Unsafe;
147    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
149}
150#[doc = "`reset()` method sets CLKCTRL to value 0"]
151impl crate::Resettable for ClkctrlSpec {
152    const RESET_VALUE: u32 = 0;
153}
max78000_pac/spi0/clkctrl.rs

max78000_pac/spi0/
clkctrl.rs
