max78000_pac/mcr/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Field `INRO_EN` reader - INRO Enable."]
6pub type InroEnR = crate::BitReader;
7#[doc = "Field `INRO_EN` writer - INRO Enable."]
8pub type InroEnW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ERTCO_EN` reader - ERTCO Enable."]
10pub type ErtcoEnR = crate::BitReader;
11#[doc = "Field `ERTCO_EN` writer - ERTCO Enable."]
12pub type ErtcoEnW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SIMO_CLKSCL_EN` reader - SIMO Clock Scaling Enable."]
14pub type SimoClksclEnR = crate::BitReader;
15#[doc = "Field `SIMO_CLKSCL_EN` writer - SIMO Clock Scaling Enable."]
16pub type SimoClksclEnW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SIMO_RSTD` reader - SIMO System Reset Disable."]
18pub type SimoRstdR = crate::BitReader;
19#[doc = "Field `SIMO_RSTD` writer - SIMO System Reset Disable."]
20pub type SimoRstdW<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 2 - INRO Enable."]
23    #[inline(always)]
24    pub fn inro_en(&self) -> InroEnR {
25        InroEnR::new(((self.bits >> 2) & 1) != 0)
26    }
27    #[doc = "Bit 3 - ERTCO Enable."]
28    #[inline(always)]
29    pub fn ertco_en(&self) -> ErtcoEnR {
30        ErtcoEnR::new(((self.bits >> 3) & 1) != 0)
31    }
32    #[doc = "Bit 8 - SIMO Clock Scaling Enable."]
33    #[inline(always)]
34    pub fn simo_clkscl_en(&self) -> SimoClksclEnR {
35        SimoClksclEnR::new(((self.bits >> 8) & 1) != 0)
36    }
37    #[doc = "Bit 9 - SIMO System Reset Disable."]
38    #[inline(always)]
39    pub fn simo_rstd(&self) -> SimoRstdR {
40        SimoRstdR::new(((self.bits >> 9) & 1) != 0)
41    }
42}
43impl W {
44    #[doc = "Bit 2 - INRO Enable."]
45    #[inline(always)]
46    pub fn inro_en(&mut self) -> InroEnW<CtrlSpec> {
47        InroEnW::new(self, 2)
48    }
49    #[doc = "Bit 3 - ERTCO Enable."]
50    #[inline(always)]
51    pub fn ertco_en(&mut self) -> ErtcoEnW<CtrlSpec> {
52        ErtcoEnW::new(self, 3)
53    }
54    #[doc = "Bit 8 - SIMO Clock Scaling Enable."]
55    #[inline(always)]
56    pub fn simo_clkscl_en(&mut self) -> SimoClksclEnW<CtrlSpec> {
57        SimoClksclEnW::new(self, 8)
58    }
59    #[doc = "Bit 9 - SIMO System Reset Disable."]
60    #[inline(always)]
61    pub fn simo_rstd(&mut self) -> SimoRstdW<CtrlSpec> {
62        SimoRstdW::new(self, 9)
63    }
64}
65#[doc = "Miscellaneous Control Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
66pub struct CtrlSpec;
67impl crate::RegisterSpec for CtrlSpec {
68    type Ux = u32;
69}
70#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
71impl crate::Readable for CtrlSpec {}
72#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
73impl crate::Writable for CtrlSpec {
74    type Safety = crate::Unsafe;
75    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
76    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
77}
78#[doc = "`reset()` method sets CTRL to value 0"]
79impl crate::Resettable for CtrlSpec {
80    const RESET_VALUE: u32 = 0;
81}
max78000_pac/mcr/ctrl.rs

max78000_pac/mcr/
ctrl.rs
