1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4 addr: Addr,
5 clkdiv: Clkdiv,
6 ctrl: Ctrl,
7 _reserved3: [u8; 0x18],
8 intr: Intr,
9 eccdata: Eccdata,
10 _reserved5: [u8; 0x04],
11 data: [Data; 4],
12 actrl: Actrl,
13 _reserved7: [u8; 0x3c],
14 welr0: Welr0,
15 _reserved8: [u8; 0x04],
16 welr1: Welr1,
17 _reserved9: [u8; 0x04],
18 rlr0: Rlr0,
19 _reserved10: [u8; 0x04],
20 rlr1: Rlr1,
21}
22impl RegisterBlock {
23 #[doc = "0x00 - Flash Write Address."]
24 #[inline(always)]
25 pub const fn addr(&self) -> &Addr {
26 &self.addr
27 }
28 #[doc = "0x04 - Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller."]
29 #[inline(always)]
30 pub const fn clkdiv(&self) -> &Clkdiv {
31 &self.clkdiv
32 }
33 #[doc = "0x08 - Flash Control Register."]
34 #[inline(always)]
35 pub const fn ctrl(&self) -> &Ctrl {
36 &self.ctrl
37 }
38 #[doc = "0x24 - Flash Interrupt Register."]
39 #[inline(always)]
40 pub const fn intr(&self) -> &Intr {
41 &self.intr
42 }
43 #[doc = "0x28 - ECC Data Register."]
44 #[inline(always)]
45 pub const fn eccdata(&self) -> &Eccdata {
46 &self.eccdata
47 }
48 #[doc = "0x30..0x40 - Flash Write Data."]
49 #[inline(always)]
50 pub const fn data(&self, n: usize) -> &Data {
51 &self.data[n]
52 }
53 #[doc = "Iterator for array of:"]
54 #[doc = "0x30..0x40 - Flash Write Data."]
55 #[inline(always)]
56 pub fn data_iter(&self) -> impl Iterator<Item = &Data> {
57 self.data.iter()
58 }
59 #[doc = "0x40 - Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero."]
60 #[inline(always)]
61 pub const fn actrl(&self) -> &Actrl {
62 &self.actrl
63 }
64 #[doc = "0x80 - WELR0"]
65 #[inline(always)]
66 pub const fn welr0(&self) -> &Welr0 {
67 &self.welr0
68 }
69 #[doc = "0x88 - WELR1"]
70 #[inline(always)]
71 pub const fn welr1(&self) -> &Welr1 {
72 &self.welr1
73 }
74 #[doc = "0x90 - RLR0"]
75 #[inline(always)]
76 pub const fn rlr0(&self) -> &Rlr0 {
77 &self.rlr0
78 }
79 #[doc = "0x98 - RLR1"]
80 #[inline(always)]
81 pub const fn rlr1(&self) -> &Rlr1 {
82 &self.rlr1
83 }
84}
85#[doc = "ADDR (rw) register accessor: Flash Write Address.\n\nYou can [`read`](crate::Reg::read) this register and get [`addr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`addr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@addr`]
86module"]
87#[doc(alias = "ADDR")]
88pub type Addr = crate::Reg<addr::AddrSpec>;
89#[doc = "Flash Write Address."]
90pub mod addr;
91#[doc = "CLKDIV (rw) register accessor: Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.\n\nYou can [`read`](crate::Reg::read) this register and get [`clkdiv::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkdiv::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clkdiv`]
92module"]
93#[doc(alias = "CLKDIV")]
94pub type Clkdiv = crate::Reg<clkdiv::ClkdivSpec>;
95#[doc = "Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller."]
96pub mod clkdiv;
97#[doc = "CTRL (rw) register accessor: Flash Control Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl`]
98module"]
99#[doc(alias = "CTRL")]
100pub type Ctrl = crate::Reg<ctrl::CtrlSpec>;
101#[doc = "Flash Control Register."]
102pub mod ctrl;
103#[doc = "INTR (rw) register accessor: Flash Interrupt Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`intr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intr`]
104module"]
105#[doc(alias = "INTR")]
106pub type Intr = crate::Reg<intr::IntrSpec>;
107#[doc = "Flash Interrupt Register."]
108pub mod intr;
109#[doc = "ECCDATA (rw) register accessor: ECC Data Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`eccdata::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`eccdata::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@eccdata`]
110module"]
111#[doc(alias = "ECCDATA")]
112pub type Eccdata = crate::Reg<eccdata::EccdataSpec>;
113#[doc = "ECC Data Register."]
114pub mod eccdata;
115#[doc = "DATA (rw) register accessor: Flash Write Data.\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
116module"]
117#[doc(alias = "DATA")]
118pub type Data = crate::Reg<data::DataSpec>;
119#[doc = "Flash Write Data."]
120pub mod data;
121#[doc = "ACTRL (w) register accessor: Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`actrl::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@actrl`]
122module"]
123#[doc(alias = "ACTRL")]
124pub type Actrl = crate::Reg<actrl::ActrlSpec>;
125#[doc = "Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero."]
126pub mod actrl;
127#[doc = "WELR0 (rw) register accessor: WELR0\n\nYou can [`read`](crate::Reg::read) this register and get [`welr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`welr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@welr0`]
128module"]
129#[doc(alias = "WELR0")]
130pub type Welr0 = crate::Reg<welr0::Welr0Spec>;
131#[doc = "WELR0"]
132pub mod welr0;
133#[doc = "WELR1 (rw) register accessor: WELR1\n\nYou can [`read`](crate::Reg::read) this register and get [`welr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`welr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@welr1`]
134module"]
135#[doc(alias = "WELR1")]
136pub type Welr1 = crate::Reg<welr1::Welr1Spec>;
137#[doc = "WELR1"]
138pub mod welr1;
139#[doc = "RLR0 (rw) register accessor: RLR0\n\nYou can [`read`](crate::Reg::read) this register and get [`rlr0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rlr0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rlr0`]
140module"]
141#[doc(alias = "RLR0")]
142pub type Rlr0 = crate::Reg<rlr0::Rlr0Spec>;
143#[doc = "RLR0"]
144pub mod rlr0;
145#[doc = "RLR1 (rw) register accessor: RLR1\n\nYou can [`read`](crate::Reg::read) this register and get [`rlr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rlr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rlr1`]
146module"]
147#[doc(alias = "RLR1")]
148pub type Rlr1 = crate::Reg<rlr1::Rlr1Spec>;
149#[doc = "RLR1"]
150pub mod rlr1;