max78000_pac/dma/ch/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum En {
8    #[doc = "0: Disable."]
9    Dis = 0,
10    #[doc = "1: Enable."]
11    En = 1,
12}
13impl From<En> for bool {
14    #[inline(always)]
15    fn from(variant: En) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `EN` reader - Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0."]
20pub type EnR = crate::BitReader<En>;
21impl EnR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> En {
25        match self.bits {
26            false => En::Dis,
27            true => En::En,
28        }
29    }
30    #[doc = "Disable."]
31    #[inline(always)]
32    pub fn is_dis(&self) -> bool {
33        *self == En::Dis
34    }
35    #[doc = "Enable."]
36    #[inline(always)]
37    pub fn is_en(&self) -> bool {
38        *self == En::En
39    }
40}
41#[doc = "Field `EN` writer - Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0."]
42pub type EnW<'a, REG> = crate::BitWriter<'a, REG, En>;
43impl<'a, REG> EnW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable."]
48    #[inline(always)]
49    pub fn dis(self) -> &'a mut crate::W<REG> {
50        self.variant(En::Dis)
51    }
52    #[doc = "Enable."]
53    #[inline(always)]
54    pub fn en(self) -> &'a mut crate::W<REG> {
55        self.variant(En::En)
56    }
57}
58#[doc = "Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum Rlden {
61    #[doc = "0: Disable."]
62    Dis = 0,
63    #[doc = "1: Enable."]
64    En = 1,
65}
66impl From<Rlden> for bool {
67    #[inline(always)]
68    fn from(variant: Rlden) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `RLDEN` reader - Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed."]
73pub type RldenR = crate::BitReader<Rlden>;
74impl RldenR {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> Rlden {
78        match self.bits {
79            false => Rlden::Dis,
80            true => Rlden::En,
81        }
82    }
83    #[doc = "Disable."]
84    #[inline(always)]
85    pub fn is_dis(&self) -> bool {
86        *self == Rlden::Dis
87    }
88    #[doc = "Enable."]
89    #[inline(always)]
90    pub fn is_en(&self) -> bool {
91        *self == Rlden::En
92    }
93}
94#[doc = "Field `RLDEN` writer - Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed."]
95pub type RldenW<'a, REG> = crate::BitWriter<'a, REG, Rlden>;
96impl<'a, REG> RldenW<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Disable."]
101    #[inline(always)]
102    pub fn dis(self) -> &'a mut crate::W<REG> {
103        self.variant(Rlden::Dis)
104    }
105    #[doc = "Enable."]
106    #[inline(always)]
107    pub fn en(self) -> &'a mut crate::W<REG> {
108        self.variant(Rlden::En)
109    }
110}
111#[doc = "DMA Priority.\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113#[repr(u8)]
114pub enum Pri {
115    #[doc = "0: Highest Priority."]
116    High = 0,
117    #[doc = "1: Medium High Priority."]
118    MedHigh = 1,
119    #[doc = "2: Medium Low Priority."]
120    MedLow = 2,
121    #[doc = "3: Lowest Priority."]
122    Low = 3,
123}
124impl From<Pri> for u8 {
125    #[inline(always)]
126    fn from(variant: Pri) -> Self {
127        variant as _
128    }
129}
130impl crate::FieldSpec for Pri {
131    type Ux = u8;
132}
133impl crate::IsEnum for Pri {}
134#[doc = "Field `PRI` reader - DMA Priority."]
135pub type PriR = crate::FieldReader<Pri>;
136impl PriR {
137    #[doc = "Get enumerated values variant"]
138    #[inline(always)]
139    pub const fn variant(&self) -> Pri {
140        match self.bits {
141            0 => Pri::High,
142            1 => Pri::MedHigh,
143            2 => Pri::MedLow,
144            3 => Pri::Low,
145            _ => unreachable!(),
146        }
147    }
148    #[doc = "Highest Priority."]
149    #[inline(always)]
150    pub fn is_high(&self) -> bool {
151        *self == Pri::High
152    }
153    #[doc = "Medium High Priority."]
154    #[inline(always)]
155    pub fn is_med_high(&self) -> bool {
156        *self == Pri::MedHigh
157    }
158    #[doc = "Medium Low Priority."]
159    #[inline(always)]
160    pub fn is_med_low(&self) -> bool {
161        *self == Pri::MedLow
162    }
163    #[doc = "Lowest Priority."]
164    #[inline(always)]
165    pub fn is_low(&self) -> bool {
166        *self == Pri::Low
167    }
168}
169#[doc = "Field `PRI` writer - DMA Priority."]
170pub type PriW<'a, REG> = crate::FieldWriter<'a, REG, 2, Pri, crate::Safe>;
171impl<'a, REG> PriW<'a, REG>
172where
173    REG: crate::Writable + crate::RegisterSpec,
174    REG::Ux: From<u8>,
175{
176    #[doc = "Highest Priority."]
177    #[inline(always)]
178    pub fn high(self) -> &'a mut crate::W<REG> {
179        self.variant(Pri::High)
180    }
181    #[doc = "Medium High Priority."]
182    #[inline(always)]
183    pub fn med_high(self) -> &'a mut crate::W<REG> {
184        self.variant(Pri::MedHigh)
185    }
186    #[doc = "Medium Low Priority."]
187    #[inline(always)]
188    pub fn med_low(self) -> &'a mut crate::W<REG> {
189        self.variant(Pri::MedLow)
190    }
191    #[doc = "Lowest Priority."]
192    #[inline(always)]
193    pub fn low(self) -> &'a mut crate::W<REG> {
194        self.variant(Pri::Low)
195    }
196}
197#[doc = "Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.\n\nValue on reset: 0"]
198#[derive(Clone, Copy, Debug, PartialEq, Eq)]
199#[repr(u8)]
200pub enum Request {
201    #[doc = "0: Memory To Memory"]
202    Memtomem = 0,
203    #[doc = "1: SPI1 RX"]
204    Spi1rx = 1,
205    #[doc = "4: UART0 RX"]
206    Uart0rx = 4,
207    #[doc = "5: UART1 RX"]
208    Uart1rx = 5,
209    #[doc = "7: I2C0 RX"]
210    I2c0rx = 7,
211    #[doc = "8: I2C1 RX"]
212    I2c1rx = 8,
213    #[doc = "9: ADC"]
214    Adc = 9,
215    #[doc = "10: I2C2 RX"]
216    I2c2rx = 10,
217    #[doc = "14: UART2 RX"]
218    Uart2rx = 14,
219    #[doc = "15: SPI0 RX"]
220    Spi0rx = 15,
221    #[doc = "16: AES RX"]
222    Aesrx = 16,
223    #[doc = "28: UART3 RX"]
224    Uart3rx = 28,
225    #[doc = "30: I2S RX"]
226    I2srx = 30,
227    #[doc = "33: SPI1 TX"]
228    Spi1tx = 33,
229    #[doc = "36: UART0 TX"]
230    Uart0tx = 36,
231    #[doc = "37: UART1 TX"]
232    Uart1tx = 37,
233    #[doc = "39: I2C0 TX"]
234    I2c0tx = 39,
235    #[doc = "40: I2C1 TX"]
236    I2c1tx = 40,
237    #[doc = "42: I2C2 TX"]
238    I2c2tx = 42,
239    #[doc = "44: CRC TX"]
240    Crctx = 44,
241    #[doc = "45: PCIF TX"]
242    Pciftx = 45,
243    #[doc = "46: UART2 TX"]
244    Uart2tx = 46,
245    #[doc = "47: SPI0 TX"]
246    Spi0tx = 47,
247    #[doc = "48: AES TX"]
248    Aestx = 48,
249    #[doc = "60: UART3 TX"]
250    Uart3tx = 60,
251    #[doc = "62: I2S TX"]
252    I2stx = 62,
253}
254impl From<Request> for u8 {
255    #[inline(always)]
256    fn from(variant: Request) -> Self {
257        variant as _
258    }
259}
260impl crate::FieldSpec for Request {
261    type Ux = u8;
262}
263impl crate::IsEnum for Request {}
264#[doc = "Field `REQUEST` reader - Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active."]
265pub type RequestR = crate::FieldReader<Request>;
266impl RequestR {
267    #[doc = "Get enumerated values variant"]
268    #[inline(always)]
269    pub const fn variant(&self) -> Option<Request> {
270        match self.bits {
271            0 => Some(Request::Memtomem),
272            1 => Some(Request::Spi1rx),
273            4 => Some(Request::Uart0rx),
274            5 => Some(Request::Uart1rx),
275            7 => Some(Request::I2c0rx),
276            8 => Some(Request::I2c1rx),
277            9 => Some(Request::Adc),
278            10 => Some(Request::I2c2rx),
279            14 => Some(Request::Uart2rx),
280            15 => Some(Request::Spi0rx),
281            16 => Some(Request::Aesrx),
282            28 => Some(Request::Uart3rx),
283            30 => Some(Request::I2srx),
284            33 => Some(Request::Spi1tx),
285            36 => Some(Request::Uart0tx),
286            37 => Some(Request::Uart1tx),
287            39 => Some(Request::I2c0tx),
288            40 => Some(Request::I2c1tx),
289            42 => Some(Request::I2c2tx),
290            44 => Some(Request::Crctx),
291            45 => Some(Request::Pciftx),
292            46 => Some(Request::Uart2tx),
293            47 => Some(Request::Spi0tx),
294            48 => Some(Request::Aestx),
295            60 => Some(Request::Uart3tx),
296            62 => Some(Request::I2stx),
297            _ => None,
298        }
299    }
300    #[doc = "Memory To Memory"]
301    #[inline(always)]
302    pub fn is_memtomem(&self) -> bool {
303        *self == Request::Memtomem
304    }
305    #[doc = "SPI1 RX"]
306    #[inline(always)]
307    pub fn is_spi1rx(&self) -> bool {
308        *self == Request::Spi1rx
309    }
310    #[doc = "UART0 RX"]
311    #[inline(always)]
312    pub fn is_uart0rx(&self) -> bool {
313        *self == Request::Uart0rx
314    }
315    #[doc = "UART1 RX"]
316    #[inline(always)]
317    pub fn is_uart1rx(&self) -> bool {
318        *self == Request::Uart1rx
319    }
320    #[doc = "I2C0 RX"]
321    #[inline(always)]
322    pub fn is_i2c0rx(&self) -> bool {
323        *self == Request::I2c0rx
324    }
325    #[doc = "I2C1 RX"]
326    #[inline(always)]
327    pub fn is_i2c1rx(&self) -> bool {
328        *self == Request::I2c1rx
329    }
330    #[doc = "ADC"]
331    #[inline(always)]
332    pub fn is_adc(&self) -> bool {
333        *self == Request::Adc
334    }
335    #[doc = "I2C2 RX"]
336    #[inline(always)]
337    pub fn is_i2c2rx(&self) -> bool {
338        *self == Request::I2c2rx
339    }
340    #[doc = "UART2 RX"]
341    #[inline(always)]
342    pub fn is_uart2rx(&self) -> bool {
343        *self == Request::Uart2rx
344    }
345    #[doc = "SPI0 RX"]
346    #[inline(always)]
347    pub fn is_spi0rx(&self) -> bool {
348        *self == Request::Spi0rx
349    }
350    #[doc = "AES RX"]
351    #[inline(always)]
352    pub fn is_aesrx(&self) -> bool {
353        *self == Request::Aesrx
354    }
355    #[doc = "UART3 RX"]
356    #[inline(always)]
357    pub fn is_uart3rx(&self) -> bool {
358        *self == Request::Uart3rx
359    }
360    #[doc = "I2S RX"]
361    #[inline(always)]
362    pub fn is_i2srx(&self) -> bool {
363        *self == Request::I2srx
364    }
365    #[doc = "SPI1 TX"]
366    #[inline(always)]
367    pub fn is_spi1tx(&self) -> bool {
368        *self == Request::Spi1tx
369    }
370    #[doc = "UART0 TX"]
371    #[inline(always)]
372    pub fn is_uart0tx(&self) -> bool {
373        *self == Request::Uart0tx
374    }
375    #[doc = "UART1 TX"]
376    #[inline(always)]
377    pub fn is_uart1tx(&self) -> bool {
378        *self == Request::Uart1tx
379    }
380    #[doc = "I2C0 TX"]
381    #[inline(always)]
382    pub fn is_i2c0tx(&self) -> bool {
383        *self == Request::I2c0tx
384    }
385    #[doc = "I2C1 TX"]
386    #[inline(always)]
387    pub fn is_i2c1tx(&self) -> bool {
388        *self == Request::I2c1tx
389    }
390    #[doc = "I2C2 TX"]
391    #[inline(always)]
392    pub fn is_i2c2tx(&self) -> bool {
393        *self == Request::I2c2tx
394    }
395    #[doc = "CRC TX"]
396    #[inline(always)]
397    pub fn is_crctx(&self) -> bool {
398        *self == Request::Crctx
399    }
400    #[doc = "PCIF TX"]
401    #[inline(always)]
402    pub fn is_pciftx(&self) -> bool {
403        *self == Request::Pciftx
404    }
405    #[doc = "UART2 TX"]
406    #[inline(always)]
407    pub fn is_uart2tx(&self) -> bool {
408        *self == Request::Uart2tx
409    }
410    #[doc = "SPI0 TX"]
411    #[inline(always)]
412    pub fn is_spi0tx(&self) -> bool {
413        *self == Request::Spi0tx
414    }
415    #[doc = "AES TX"]
416    #[inline(always)]
417    pub fn is_aestx(&self) -> bool {
418        *self == Request::Aestx
419    }
420    #[doc = "UART3 TX"]
421    #[inline(always)]
422    pub fn is_uart3tx(&self) -> bool {
423        *self == Request::Uart3tx
424    }
425    #[doc = "I2S TX"]
426    #[inline(always)]
427    pub fn is_i2stx(&self) -> bool {
428        *self == Request::I2stx
429    }
430}
431#[doc = "Field `REQUEST` writer - Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active."]
432pub type RequestW<'a, REG> = crate::FieldWriter<'a, REG, 6, Request>;
433impl<'a, REG> RequestW<'a, REG>
434where
435    REG: crate::Writable + crate::RegisterSpec,
436    REG::Ux: From<u8>,
437{
438    #[doc = "Memory To Memory"]
439    #[inline(always)]
440    pub fn memtomem(self) -> &'a mut crate::W<REG> {
441        self.variant(Request::Memtomem)
442    }
443    #[doc = "SPI1 RX"]
444    #[inline(always)]
445    pub fn spi1rx(self) -> &'a mut crate::W<REG> {
446        self.variant(Request::Spi1rx)
447    }
448    #[doc = "UART0 RX"]
449    #[inline(always)]
450    pub fn uart0rx(self) -> &'a mut crate::W<REG> {
451        self.variant(Request::Uart0rx)
452    }
453    #[doc = "UART1 RX"]
454    #[inline(always)]
455    pub fn uart1rx(self) -> &'a mut crate::W<REG> {
456        self.variant(Request::Uart1rx)
457    }
458    #[doc = "I2C0 RX"]
459    #[inline(always)]
460    pub fn i2c0rx(self) -> &'a mut crate::W<REG> {
461        self.variant(Request::I2c0rx)
462    }
463    #[doc = "I2C1 RX"]
464    #[inline(always)]
465    pub fn i2c1rx(self) -> &'a mut crate::W<REG> {
466        self.variant(Request::I2c1rx)
467    }
468    #[doc = "ADC"]
469    #[inline(always)]
470    pub fn adc(self) -> &'a mut crate::W<REG> {
471        self.variant(Request::Adc)
472    }
473    #[doc = "I2C2 RX"]
474    #[inline(always)]
475    pub fn i2c2rx(self) -> &'a mut crate::W<REG> {
476        self.variant(Request::I2c2rx)
477    }
478    #[doc = "UART2 RX"]
479    #[inline(always)]
480    pub fn uart2rx(self) -> &'a mut crate::W<REG> {
481        self.variant(Request::Uart2rx)
482    }
483    #[doc = "SPI0 RX"]
484    #[inline(always)]
485    pub fn spi0rx(self) -> &'a mut crate::W<REG> {
486        self.variant(Request::Spi0rx)
487    }
488    #[doc = "AES RX"]
489    #[inline(always)]
490    pub fn aesrx(self) -> &'a mut crate::W<REG> {
491        self.variant(Request::Aesrx)
492    }
493    #[doc = "UART3 RX"]
494    #[inline(always)]
495    pub fn uart3rx(self) -> &'a mut crate::W<REG> {
496        self.variant(Request::Uart3rx)
497    }
498    #[doc = "I2S RX"]
499    #[inline(always)]
500    pub fn i2srx(self) -> &'a mut crate::W<REG> {
501        self.variant(Request::I2srx)
502    }
503    #[doc = "SPI1 TX"]
504    #[inline(always)]
505    pub fn spi1tx(self) -> &'a mut crate::W<REG> {
506        self.variant(Request::Spi1tx)
507    }
508    #[doc = "UART0 TX"]
509    #[inline(always)]
510    pub fn uart0tx(self) -> &'a mut crate::W<REG> {
511        self.variant(Request::Uart0tx)
512    }
513    #[doc = "UART1 TX"]
514    #[inline(always)]
515    pub fn uart1tx(self) -> &'a mut crate::W<REG> {
516        self.variant(Request::Uart1tx)
517    }
518    #[doc = "I2C0 TX"]
519    #[inline(always)]
520    pub fn i2c0tx(self) -> &'a mut crate::W<REG> {
521        self.variant(Request::I2c0tx)
522    }
523    #[doc = "I2C1 TX"]
524    #[inline(always)]
525    pub fn i2c1tx(self) -> &'a mut crate::W<REG> {
526        self.variant(Request::I2c1tx)
527    }
528    #[doc = "I2C2 TX"]
529    #[inline(always)]
530    pub fn i2c2tx(self) -> &'a mut crate::W<REG> {
531        self.variant(Request::I2c2tx)
532    }
533    #[doc = "CRC TX"]
534    #[inline(always)]
535    pub fn crctx(self) -> &'a mut crate::W<REG> {
536        self.variant(Request::Crctx)
537    }
538    #[doc = "PCIF TX"]
539    #[inline(always)]
540    pub fn pciftx(self) -> &'a mut crate::W<REG> {
541        self.variant(Request::Pciftx)
542    }
543    #[doc = "UART2 TX"]
544    #[inline(always)]
545    pub fn uart2tx(self) -> &'a mut crate::W<REG> {
546        self.variant(Request::Uart2tx)
547    }
548    #[doc = "SPI0 TX"]
549    #[inline(always)]
550    pub fn spi0tx(self) -> &'a mut crate::W<REG> {
551        self.variant(Request::Spi0tx)
552    }
553    #[doc = "AES TX"]
554    #[inline(always)]
555    pub fn aestx(self) -> &'a mut crate::W<REG> {
556        self.variant(Request::Aestx)
557    }
558    #[doc = "UART3 TX"]
559    #[inline(always)]
560    pub fn uart3tx(self) -> &'a mut crate::W<REG> {
561        self.variant(Request::Uart3tx)
562    }
563    #[doc = "I2S TX"]
564    #[inline(always)]
565    pub fn i2stx(self) -> &'a mut crate::W<REG> {
566        self.variant(Request::I2stx)
567    }
568}
569#[doc = "Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.\n\nValue on reset: 0"]
570#[derive(Clone, Copy, Debug, PartialEq, Eq)]
571pub enum ToWait {
572    #[doc = "0: Disable."]
573    Dis = 0,
574    #[doc = "1: Enable."]
575    En = 1,
576}
577impl From<ToWait> for bool {
578    #[inline(always)]
579    fn from(variant: ToWait) -> Self {
580        variant as u8 != 0
581    }
582}
583#[doc = "Field `TO_WAIT` reader - Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive."]
584pub type ToWaitR = crate::BitReader<ToWait>;
585impl ToWaitR {
586    #[doc = "Get enumerated values variant"]
587    #[inline(always)]
588    pub const fn variant(&self) -> ToWait {
589        match self.bits {
590            false => ToWait::Dis,
591            true => ToWait::En,
592        }
593    }
594    #[doc = "Disable."]
595    #[inline(always)]
596    pub fn is_dis(&self) -> bool {
597        *self == ToWait::Dis
598    }
599    #[doc = "Enable."]
600    #[inline(always)]
601    pub fn is_en(&self) -> bool {
602        *self == ToWait::En
603    }
604}
605#[doc = "Field `TO_WAIT` writer - Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive."]
606pub type ToWaitW<'a, REG> = crate::BitWriter<'a, REG, ToWait>;
607impl<'a, REG> ToWaitW<'a, REG>
608where
609    REG: crate::Writable + crate::RegisterSpec,
610{
611    #[doc = "Disable."]
612    #[inline(always)]
613    pub fn dis(self) -> &'a mut crate::W<REG> {
614        self.variant(ToWait::Dis)
615    }
616    #[doc = "Enable."]
617    #[inline(always)]
618    pub fn en(self) -> &'a mut crate::W<REG> {
619        self.variant(ToWait::En)
620    }
621}
622#[doc = "Timeout Period Select.\n\nValue on reset: 0"]
623#[derive(Clone, Copy, Debug, PartialEq, Eq)]
624#[repr(u8)]
625pub enum ToPer {
626    #[doc = "0: Timeout of 3 to 4 prescale clocks."]
627    To4 = 0,
628    #[doc = "1: Timeout of 7 to 8 prescale clocks."]
629    To8 = 1,
630    #[doc = "2: Timeout of 15 to 16 prescale clocks."]
631    To16 = 2,
632    #[doc = "3: Timeout of 31 to 32 prescale clocks."]
633    To32 = 3,
634    #[doc = "4: Timeout of 63 to 64 prescale clocks."]
635    To64 = 4,
636    #[doc = "5: Timeout of 127 to 128 prescale clocks."]
637    To128 = 5,
638    #[doc = "6: Timeout of 255 to 256 prescale clocks."]
639    To256 = 6,
640    #[doc = "7: Timeout of 511 to 512 prescale clocks."]
641    To512 = 7,
642}
643impl From<ToPer> for u8 {
644    #[inline(always)]
645    fn from(variant: ToPer) -> Self {
646        variant as _
647    }
648}
649impl crate::FieldSpec for ToPer {
650    type Ux = u8;
651}
652impl crate::IsEnum for ToPer {}
653#[doc = "Field `TO_PER` reader - Timeout Period Select."]
654pub type ToPerR = crate::FieldReader<ToPer>;
655impl ToPerR {
656    #[doc = "Get enumerated values variant"]
657    #[inline(always)]
658    pub const fn variant(&self) -> ToPer {
659        match self.bits {
660            0 => ToPer::To4,
661            1 => ToPer::To8,
662            2 => ToPer::To16,
663            3 => ToPer::To32,
664            4 => ToPer::To64,
665            5 => ToPer::To128,
666            6 => ToPer::To256,
667            7 => ToPer::To512,
668            _ => unreachable!(),
669        }
670    }
671    #[doc = "Timeout of 3 to 4 prescale clocks."]
672    #[inline(always)]
673    pub fn is_to4(&self) -> bool {
674        *self == ToPer::To4
675    }
676    #[doc = "Timeout of 7 to 8 prescale clocks."]
677    #[inline(always)]
678    pub fn is_to8(&self) -> bool {
679        *self == ToPer::To8
680    }
681    #[doc = "Timeout of 15 to 16 prescale clocks."]
682    #[inline(always)]
683    pub fn is_to16(&self) -> bool {
684        *self == ToPer::To16
685    }
686    #[doc = "Timeout of 31 to 32 prescale clocks."]
687    #[inline(always)]
688    pub fn is_to32(&self) -> bool {
689        *self == ToPer::To32
690    }
691    #[doc = "Timeout of 63 to 64 prescale clocks."]
692    #[inline(always)]
693    pub fn is_to64(&self) -> bool {
694        *self == ToPer::To64
695    }
696    #[doc = "Timeout of 127 to 128 prescale clocks."]
697    #[inline(always)]
698    pub fn is_to128(&self) -> bool {
699        *self == ToPer::To128
700    }
701    #[doc = "Timeout of 255 to 256 prescale clocks."]
702    #[inline(always)]
703    pub fn is_to256(&self) -> bool {
704        *self == ToPer::To256
705    }
706    #[doc = "Timeout of 511 to 512 prescale clocks."]
707    #[inline(always)]
708    pub fn is_to512(&self) -> bool {
709        *self == ToPer::To512
710    }
711}
712#[doc = "Field `TO_PER` writer - Timeout Period Select."]
713pub type ToPerW<'a, REG> = crate::FieldWriter<'a, REG, 3, ToPer, crate::Safe>;
714impl<'a, REG> ToPerW<'a, REG>
715where
716    REG: crate::Writable + crate::RegisterSpec,
717    REG::Ux: From<u8>,
718{
719    #[doc = "Timeout of 3 to 4 prescale clocks."]
720    #[inline(always)]
721    pub fn to4(self) -> &'a mut crate::W<REG> {
722        self.variant(ToPer::To4)
723    }
724    #[doc = "Timeout of 7 to 8 prescale clocks."]
725    #[inline(always)]
726    pub fn to8(self) -> &'a mut crate::W<REG> {
727        self.variant(ToPer::To8)
728    }
729    #[doc = "Timeout of 15 to 16 prescale clocks."]
730    #[inline(always)]
731    pub fn to16(self) -> &'a mut crate::W<REG> {
732        self.variant(ToPer::To16)
733    }
734    #[doc = "Timeout of 31 to 32 prescale clocks."]
735    #[inline(always)]
736    pub fn to32(self) -> &'a mut crate::W<REG> {
737        self.variant(ToPer::To32)
738    }
739    #[doc = "Timeout of 63 to 64 prescale clocks."]
740    #[inline(always)]
741    pub fn to64(self) -> &'a mut crate::W<REG> {
742        self.variant(ToPer::To64)
743    }
744    #[doc = "Timeout of 127 to 128 prescale clocks."]
745    #[inline(always)]
746    pub fn to128(self) -> &'a mut crate::W<REG> {
747        self.variant(ToPer::To128)
748    }
749    #[doc = "Timeout of 255 to 256 prescale clocks."]
750    #[inline(always)]
751    pub fn to256(self) -> &'a mut crate::W<REG> {
752        self.variant(ToPer::To256)
753    }
754    #[doc = "Timeout of 511 to 512 prescale clocks."]
755    #[inline(always)]
756    pub fn to512(self) -> &'a mut crate::W<REG> {
757        self.variant(ToPer::To512)
758    }
759}
760#[doc = "Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.\n\nValue on reset: 0"]
761#[derive(Clone, Copy, Debug, PartialEq, Eq)]
762#[repr(u8)]
763pub enum ToClkdiv {
764    #[doc = "0: Disable timer."]
765    Dis = 0,
766    #[doc = "1: hclk / 256."]
767    Div256 = 1,
768    #[doc = "2: hclk / 64k."]
769    Div64k = 2,
770    #[doc = "3: hclk / 16M."]
771    Div16m = 3,
772}
773impl From<ToClkdiv> for u8 {
774    #[inline(always)]
775    fn from(variant: ToClkdiv) -> Self {
776        variant as _
777    }
778}
779impl crate::FieldSpec for ToClkdiv {
780    type Ux = u8;
781}
782impl crate::IsEnum for ToClkdiv {}
783#[doc = "Field `TO_CLKDIV` reader - Pre-Scale Select. Selects the Pre-Scale divider for timer clock input."]
784pub type ToClkdivR = crate::FieldReader<ToClkdiv>;
785impl ToClkdivR {
786    #[doc = "Get enumerated values variant"]
787    #[inline(always)]
788    pub const fn variant(&self) -> ToClkdiv {
789        match self.bits {
790            0 => ToClkdiv::Dis,
791            1 => ToClkdiv::Div256,
792            2 => ToClkdiv::Div64k,
793            3 => ToClkdiv::Div16m,
794            _ => unreachable!(),
795        }
796    }
797    #[doc = "Disable timer."]
798    #[inline(always)]
799    pub fn is_dis(&self) -> bool {
800        *self == ToClkdiv::Dis
801    }
802    #[doc = "hclk / 256."]
803    #[inline(always)]
804    pub fn is_div256(&self) -> bool {
805        *self == ToClkdiv::Div256
806    }
807    #[doc = "hclk / 64k."]
808    #[inline(always)]
809    pub fn is_div64k(&self) -> bool {
810        *self == ToClkdiv::Div64k
811    }
812    #[doc = "hclk / 16M."]
813    #[inline(always)]
814    pub fn is_div16m(&self) -> bool {
815        *self == ToClkdiv::Div16m
816    }
817}
818#[doc = "Field `TO_CLKDIV` writer - Pre-Scale Select. Selects the Pre-Scale divider for timer clock input."]
819pub type ToClkdivW<'a, REG> = crate::FieldWriter<'a, REG, 2, ToClkdiv, crate::Safe>;
820impl<'a, REG> ToClkdivW<'a, REG>
821where
822    REG: crate::Writable + crate::RegisterSpec,
823    REG::Ux: From<u8>,
824{
825    #[doc = "Disable timer."]
826    #[inline(always)]
827    pub fn dis(self) -> &'a mut crate::W<REG> {
828        self.variant(ToClkdiv::Dis)
829    }
830    #[doc = "hclk / 256."]
831    #[inline(always)]
832    pub fn div256(self) -> &'a mut crate::W<REG> {
833        self.variant(ToClkdiv::Div256)
834    }
835    #[doc = "hclk / 64k."]
836    #[inline(always)]
837    pub fn div64k(self) -> &'a mut crate::W<REG> {
838        self.variant(ToClkdiv::Div64k)
839    }
840    #[doc = "hclk / 16M."]
841    #[inline(always)]
842    pub fn div16m(self) -> &'a mut crate::W<REG> {
843        self.variant(ToClkdiv::Div16m)
844    }
845}
846#[doc = "Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.\n\nValue on reset: 0"]
847#[derive(Clone, Copy, Debug, PartialEq, Eq)]
848#[repr(u8)]
849pub enum Srcwd {
850    #[doc = "0: Byte."]
851    Byte = 0,
852    #[doc = "1: Halfword."]
853    HalfWord = 1,
854    #[doc = "2: Word."]
855    Word = 2,
856}
857impl From<Srcwd> for u8 {
858    #[inline(always)]
859    fn from(variant: Srcwd) -> Self {
860        variant as _
861    }
862}
863impl crate::FieldSpec for Srcwd {
864    type Ux = u8;
865}
866impl crate::IsEnum for Srcwd {}
867#[doc = "Field `SRCWD` reader - Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value."]
868pub type SrcwdR = crate::FieldReader<Srcwd>;
869impl SrcwdR {
870    #[doc = "Get enumerated values variant"]
871    #[inline(always)]
872    pub const fn variant(&self) -> Option<Srcwd> {
873        match self.bits {
874            0 => Some(Srcwd::Byte),
875            1 => Some(Srcwd::HalfWord),
876            2 => Some(Srcwd::Word),
877            _ => None,
878        }
879    }
880    #[doc = "Byte."]
881    #[inline(always)]
882    pub fn is_byte(&self) -> bool {
883        *self == Srcwd::Byte
884    }
885    #[doc = "Halfword."]
886    #[inline(always)]
887    pub fn is_half_word(&self) -> bool {
888        *self == Srcwd::HalfWord
889    }
890    #[doc = "Word."]
891    #[inline(always)]
892    pub fn is_word(&self) -> bool {
893        *self == Srcwd::Word
894    }
895}
896#[doc = "Field `SRCWD` writer - Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value."]
897pub type SrcwdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Srcwd>;
898impl<'a, REG> SrcwdW<'a, REG>
899where
900    REG: crate::Writable + crate::RegisterSpec,
901    REG::Ux: From<u8>,
902{
903    #[doc = "Byte."]
904    #[inline(always)]
905    pub fn byte(self) -> &'a mut crate::W<REG> {
906        self.variant(Srcwd::Byte)
907    }
908    #[doc = "Halfword."]
909    #[inline(always)]
910    pub fn half_word(self) -> &'a mut crate::W<REG> {
911        self.variant(Srcwd::HalfWord)
912    }
913    #[doc = "Word."]
914    #[inline(always)]
915    pub fn word(self) -> &'a mut crate::W<REG> {
916        self.variant(Srcwd::Word)
917    }
918}
919#[doc = "Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.\n\nValue on reset: 0"]
920#[derive(Clone, Copy, Debug, PartialEq, Eq)]
921pub enum Srcinc {
922    #[doc = "0: Disable."]
923    Dis = 0,
924    #[doc = "1: Enable."]
925    En = 1,
926}
927impl From<Srcinc> for bool {
928    #[inline(always)]
929    fn from(variant: Srcinc) -> Self {
930        variant as u8 != 0
931    }
932}
933#[doc = "Field `SRCINC` reader - Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals."]
934pub type SrcincR = crate::BitReader<Srcinc>;
935impl SrcincR {
936    #[doc = "Get enumerated values variant"]
937    #[inline(always)]
938    pub const fn variant(&self) -> Srcinc {
939        match self.bits {
940            false => Srcinc::Dis,
941            true => Srcinc::En,
942        }
943    }
944    #[doc = "Disable."]
945    #[inline(always)]
946    pub fn is_dis(&self) -> bool {
947        *self == Srcinc::Dis
948    }
949    #[doc = "Enable."]
950    #[inline(always)]
951    pub fn is_en(&self) -> bool {
952        *self == Srcinc::En
953    }
954}
955#[doc = "Field `SRCINC` writer - Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals."]
956pub type SrcincW<'a, REG> = crate::BitWriter<'a, REG, Srcinc>;
957impl<'a, REG> SrcincW<'a, REG>
958where
959    REG: crate::Writable + crate::RegisterSpec,
960{
961    #[doc = "Disable."]
962    #[inline(always)]
963    pub fn dis(self) -> &'a mut crate::W<REG> {
964        self.variant(Srcinc::Dis)
965    }
966    #[doc = "Enable."]
967    #[inline(always)]
968    pub fn en(self) -> &'a mut crate::W<REG> {
969        self.variant(Srcinc::En)
970    }
971}
972#[doc = "Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).\n\nValue on reset: 0"]
973#[derive(Clone, Copy, Debug, PartialEq, Eq)]
974#[repr(u8)]
975pub enum Dstwd {
976    #[doc = "0: Byte."]
977    Byte = 0,
978    #[doc = "1: Halfword."]
979    HalfWord = 1,
980    #[doc = "2: Word."]
981    Word = 2,
982}
983impl From<Dstwd> for u8 {
984    #[inline(always)]
985    fn from(variant: Dstwd) -> Self {
986        variant as _
987    }
988}
989impl crate::FieldSpec for Dstwd {
990    type Ux = u8;
991}
992impl crate::IsEnum for Dstwd {}
993#[doc = "Field `DSTWD` reader - Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width)."]
994pub type DstwdR = crate::FieldReader<Dstwd>;
995impl DstwdR {
996    #[doc = "Get enumerated values variant"]
997    #[inline(always)]
998    pub const fn variant(&self) -> Option<Dstwd> {
999        match self.bits {
1000            0 => Some(Dstwd::Byte),
1001            1 => Some(Dstwd::HalfWord),
1002            2 => Some(Dstwd::Word),
1003            _ => None,
1004        }
1005    }
1006    #[doc = "Byte."]
1007    #[inline(always)]
1008    pub fn is_byte(&self) -> bool {
1009        *self == Dstwd::Byte
1010    }
1011    #[doc = "Halfword."]
1012    #[inline(always)]
1013    pub fn is_half_word(&self) -> bool {
1014        *self == Dstwd::HalfWord
1015    }
1016    #[doc = "Word."]
1017    #[inline(always)]
1018    pub fn is_word(&self) -> bool {
1019        *self == Dstwd::Word
1020    }
1021}
1022#[doc = "Field `DSTWD` writer - Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width)."]
1023pub type DstwdW<'a, REG> = crate::FieldWriter<'a, REG, 2, Dstwd>;
1024impl<'a, REG> DstwdW<'a, REG>
1025where
1026    REG: crate::Writable + crate::RegisterSpec,
1027    REG::Ux: From<u8>,
1028{
1029    #[doc = "Byte."]
1030    #[inline(always)]
1031    pub fn byte(self) -> &'a mut crate::W<REG> {
1032        self.variant(Dstwd::Byte)
1033    }
1034    #[doc = "Halfword."]
1035    #[inline(always)]
1036    pub fn half_word(self) -> &'a mut crate::W<REG> {
1037        self.variant(Dstwd::HalfWord)
1038    }
1039    #[doc = "Word."]
1040    #[inline(always)]
1041    pub fn word(self) -> &'a mut crate::W<REG> {
1042        self.variant(Dstwd::Word)
1043    }
1044}
1045#[doc = "Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.\n\nValue on reset: 0"]
1046#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1047pub enum Dstinc {
1048    #[doc = "0: Disable."]
1049    Dis = 0,
1050    #[doc = "1: Enable."]
1051    En = 1,
1052}
1053impl From<Dstinc> for bool {
1054    #[inline(always)]
1055    fn from(variant: Dstinc) -> Self {
1056        variant as u8 != 0
1057    }
1058}
1059#[doc = "Field `DSTINC` reader - Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals."]
1060pub type DstincR = crate::BitReader<Dstinc>;
1061impl DstincR {
1062    #[doc = "Get enumerated values variant"]
1063    #[inline(always)]
1064    pub const fn variant(&self) -> Dstinc {
1065        match self.bits {
1066            false => Dstinc::Dis,
1067            true => Dstinc::En,
1068        }
1069    }
1070    #[doc = "Disable."]
1071    #[inline(always)]
1072    pub fn is_dis(&self) -> bool {
1073        *self == Dstinc::Dis
1074    }
1075    #[doc = "Enable."]
1076    #[inline(always)]
1077    pub fn is_en(&self) -> bool {
1078        *self == Dstinc::En
1079    }
1080}
1081#[doc = "Field `DSTINC` writer - Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals."]
1082pub type DstincW<'a, REG> = crate::BitWriter<'a, REG, Dstinc>;
1083impl<'a, REG> DstincW<'a, REG>
1084where
1085    REG: crate::Writable + crate::RegisterSpec,
1086{
1087    #[doc = "Disable."]
1088    #[inline(always)]
1089    pub fn dis(self) -> &'a mut crate::W<REG> {
1090        self.variant(Dstinc::Dis)
1091    }
1092    #[doc = "Enable."]
1093    #[inline(always)]
1094    pub fn en(self) -> &'a mut crate::W<REG> {
1095        self.variant(Dstinc::En)
1096    }
1097}
1098#[doc = "Field `BURST_SIZE` reader - Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field."]
1099pub type BurstSizeR = crate::FieldReader;
1100#[doc = "Field `BURST_SIZE` writer - Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field."]
1101pub type BurstSizeW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
1102#[doc = "Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.\n\nValue on reset: 0"]
1103#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1104pub enum DisIe {
1105    #[doc = "0: Disable."]
1106    Dis = 0,
1107    #[doc = "1: Enable."]
1108    En = 1,
1109}
1110impl From<DisIe> for bool {
1111    #[inline(always)]
1112    fn from(variant: DisIe) -> Self {
1113        variant as u8 != 0
1114    }
1115}
1116#[doc = "Field `DIS_IE` reader - Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0."]
1117pub type DisIeR = crate::BitReader<DisIe>;
1118impl DisIeR {
1119    #[doc = "Get enumerated values variant"]
1120    #[inline(always)]
1121    pub const fn variant(&self) -> DisIe {
1122        match self.bits {
1123            false => DisIe::Dis,
1124            true => DisIe::En,
1125        }
1126    }
1127    #[doc = "Disable."]
1128    #[inline(always)]
1129    pub fn is_dis(&self) -> bool {
1130        *self == DisIe::Dis
1131    }
1132    #[doc = "Enable."]
1133    #[inline(always)]
1134    pub fn is_en(&self) -> bool {
1135        *self == DisIe::En
1136    }
1137}
1138#[doc = "Field `DIS_IE` writer - Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0."]
1139pub type DisIeW<'a, REG> = crate::BitWriter<'a, REG, DisIe>;
1140impl<'a, REG> DisIeW<'a, REG>
1141where
1142    REG: crate::Writable + crate::RegisterSpec,
1143{
1144    #[doc = "Disable."]
1145    #[inline(always)]
1146    pub fn dis(self) -> &'a mut crate::W<REG> {
1147        self.variant(DisIe::Dis)
1148    }
1149    #[doc = "Enable."]
1150    #[inline(always)]
1151    pub fn en(self) -> &'a mut crate::W<REG> {
1152        self.variant(DisIe::En)
1153    }
1154}
1155#[doc = "Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.\n\nValue on reset: 0"]
1156#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1157pub enum CtzIe {
1158    #[doc = "0: Disable."]
1159    Dis = 0,
1160    #[doc = "1: Enable."]
1161    En = 1,
1162}
1163impl From<CtzIe> for bool {
1164    #[inline(always)]
1165    fn from(variant: CtzIe) -> Self {
1166        variant as u8 != 0
1167    }
1168}
1169#[doc = "Field `CTZ_IE` reader - Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs."]
1170pub type CtzIeR = crate::BitReader<CtzIe>;
1171impl CtzIeR {
1172    #[doc = "Get enumerated values variant"]
1173    #[inline(always)]
1174    pub const fn variant(&self) -> CtzIe {
1175        match self.bits {
1176            false => CtzIe::Dis,
1177            true => CtzIe::En,
1178        }
1179    }
1180    #[doc = "Disable."]
1181    #[inline(always)]
1182    pub fn is_dis(&self) -> bool {
1183        *self == CtzIe::Dis
1184    }
1185    #[doc = "Enable."]
1186    #[inline(always)]
1187    pub fn is_en(&self) -> bool {
1188        *self == CtzIe::En
1189    }
1190}
1191#[doc = "Field `CTZ_IE` writer - Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs."]
1192pub type CtzIeW<'a, REG> = crate::BitWriter<'a, REG, CtzIe>;
1193impl<'a, REG> CtzIeW<'a, REG>
1194where
1195    REG: crate::Writable + crate::RegisterSpec,
1196{
1197    #[doc = "Disable."]
1198    #[inline(always)]
1199    pub fn dis(self) -> &'a mut crate::W<REG> {
1200        self.variant(CtzIe::Dis)
1201    }
1202    #[doc = "Enable."]
1203    #[inline(always)]
1204    pub fn en(self) -> &'a mut crate::W<REG> {
1205        self.variant(CtzIe::En)
1206    }
1207}
1208impl R {
1209    #[doc = "Bit 0 - Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0."]
1210    #[inline(always)]
1211    pub fn en(&self) -> EnR {
1212        EnR::new((self.bits & 1) != 0)
1213    }
1214    #[doc = "Bit 1 - Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed."]
1215    #[inline(always)]
1216    pub fn rlden(&self) -> RldenR {
1217        RldenR::new(((self.bits >> 1) & 1) != 0)
1218    }
1219    #[doc = "Bits 2:3 - DMA Priority."]
1220    #[inline(always)]
1221    pub fn pri(&self) -> PriR {
1222        PriR::new(((self.bits >> 2) & 3) as u8)
1223    }
1224    #[doc = "Bits 4:9 - Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active."]
1225    #[inline(always)]
1226    pub fn request(&self) -> RequestR {
1227        RequestR::new(((self.bits >> 4) & 0x3f) as u8)
1228    }
1229    #[doc = "Bit 10 - Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive."]
1230    #[inline(always)]
1231    pub fn to_wait(&self) -> ToWaitR {
1232        ToWaitR::new(((self.bits >> 10) & 1) != 0)
1233    }
1234    #[doc = "Bits 11:13 - Timeout Period Select."]
1235    #[inline(always)]
1236    pub fn to_per(&self) -> ToPerR {
1237        ToPerR::new(((self.bits >> 11) & 7) as u8)
1238    }
1239    #[doc = "Bits 14:15 - Pre-Scale Select. Selects the Pre-Scale divider for timer clock input."]
1240    #[inline(always)]
1241    pub fn to_clkdiv(&self) -> ToClkdivR {
1242        ToClkdivR::new(((self.bits >> 14) & 3) as u8)
1243    }
1244    #[doc = "Bits 16:17 - Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value."]
1245    #[inline(always)]
1246    pub fn srcwd(&self) -> SrcwdR {
1247        SrcwdR::new(((self.bits >> 16) & 3) as u8)
1248    }
1249    #[doc = "Bit 18 - Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals."]
1250    #[inline(always)]
1251    pub fn srcinc(&self) -> SrcincR {
1252        SrcincR::new(((self.bits >> 18) & 1) != 0)
1253    }
1254    #[doc = "Bits 20:21 - Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width)."]
1255    #[inline(always)]
1256    pub fn dstwd(&self) -> DstwdR {
1257        DstwdR::new(((self.bits >> 20) & 3) as u8)
1258    }
1259    #[doc = "Bit 22 - Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals."]
1260    #[inline(always)]
1261    pub fn dstinc(&self) -> DstincR {
1262        DstincR::new(((self.bits >> 22) & 1) != 0)
1263    }
1264    #[doc = "Bits 24:28 - Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field."]
1265    #[inline(always)]
1266    pub fn burst_size(&self) -> BurstSizeR {
1267        BurstSizeR::new(((self.bits >> 24) & 0x1f) as u8)
1268    }
1269    #[doc = "Bit 30 - Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0."]
1270    #[inline(always)]
1271    pub fn dis_ie(&self) -> DisIeR {
1272        DisIeR::new(((self.bits >> 30) & 1) != 0)
1273    }
1274    #[doc = "Bit 31 - Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs."]
1275    #[inline(always)]
1276    pub fn ctz_ie(&self) -> CtzIeR {
1277        CtzIeR::new(((self.bits >> 31) & 1) != 0)
1278    }
1279}
1280impl W {
1281    #[doc = "Bit 0 - Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0."]
1282    #[inline(always)]
1283    pub fn en(&mut self) -> EnW<CtrlSpec> {
1284        EnW::new(self, 0)
1285    }
1286    #[doc = "Bit 1 - Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed."]
1287    #[inline(always)]
1288    pub fn rlden(&mut self) -> RldenW<CtrlSpec> {
1289        RldenW::new(self, 1)
1290    }
1291    #[doc = "Bits 2:3 - DMA Priority."]
1292    #[inline(always)]
1293    pub fn pri(&mut self) -> PriW<CtrlSpec> {
1294        PriW::new(self, 2)
1295    }
1296    #[doc = "Bits 4:9 - Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active."]
1297    #[inline(always)]
1298    pub fn request(&mut self) -> RequestW<CtrlSpec> {
1299        RequestW::new(self, 4)
1300    }
1301    #[doc = "Bit 10 - Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive."]
1302    #[inline(always)]
1303    pub fn to_wait(&mut self) -> ToWaitW<CtrlSpec> {
1304        ToWaitW::new(self, 10)
1305    }
1306    #[doc = "Bits 11:13 - Timeout Period Select."]
1307    #[inline(always)]
1308    pub fn to_per(&mut self) -> ToPerW<CtrlSpec> {
1309        ToPerW::new(self, 11)
1310    }
1311    #[doc = "Bits 14:15 - Pre-Scale Select. Selects the Pre-Scale divider for timer clock input."]
1312    #[inline(always)]
1313    pub fn to_clkdiv(&mut self) -> ToClkdivW<CtrlSpec> {
1314        ToClkdivW::new(self, 14)
1315    }
1316    #[doc = "Bits 16:17 - Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value."]
1317    #[inline(always)]
1318    pub fn srcwd(&mut self) -> SrcwdW<CtrlSpec> {
1319        SrcwdW::new(self, 16)
1320    }
1321    #[doc = "Bit 18 - Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals."]
1322    #[inline(always)]
1323    pub fn srcinc(&mut self) -> SrcincW<CtrlSpec> {
1324        SrcincW::new(self, 18)
1325    }
1326    #[doc = "Bits 20:21 - Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width)."]
1327    #[inline(always)]
1328    pub fn dstwd(&mut self) -> DstwdW<CtrlSpec> {
1329        DstwdW::new(self, 20)
1330    }
1331    #[doc = "Bit 22 - Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals."]
1332    #[inline(always)]
1333    pub fn dstinc(&mut self) -> DstincW<CtrlSpec> {
1334        DstincW::new(self, 22)
1335    }
1336    #[doc = "Bits 24:28 - Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field."]
1337    #[inline(always)]
1338    pub fn burst_size(&mut self) -> BurstSizeW<CtrlSpec> {
1339        BurstSizeW::new(self, 24)
1340    }
1341    #[doc = "Bit 30 - Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0."]
1342    #[inline(always)]
1343    pub fn dis_ie(&mut self) -> DisIeW<CtrlSpec> {
1344        DisIeW::new(self, 30)
1345    }
1346    #[doc = "Bit 31 - Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs."]
1347    #[inline(always)]
1348    pub fn ctz_ie(&mut self) -> CtzIeW<CtrlSpec> {
1349        CtzIeW::new(self, 31)
1350    }
1351}
1352#[doc = "DMA Channel Control Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1353pub struct CtrlSpec;
1354impl crate::RegisterSpec for CtrlSpec {
1355    type Ux = u32;
1356}
1357#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
1358impl crate::Readable for CtrlSpec {}
1359#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
1360impl crate::Writable for CtrlSpec {
1361    type Safety = crate::Unsafe;
1362    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1363    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
1364}
1365#[doc = "`reset()` method sets CTRL to value 0"]
1366impl crate::Resettable for CtrlSpec {
1367    const RESET_VALUE: u32 = 0;
1368}
max78000_pac/dma/ch/ctrl.rs

max78000_pac/dma/ch/
ctrl.rs
