max78000_pac/wut/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Timer Mode.\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum Tmode {
9    #[doc = "0: One Shot Mode."]
10    OneShot = 0,
11    #[doc = "1: Continuous Mode."]
12    Continuous = 1,
13    #[doc = "2: Counter Mode."]
14    Counter = 2,
15    #[doc = "4: Capture Mode."]
16    Capture = 4,
17    #[doc = "5: Compare Mode."]
18    Compare = 5,
19    #[doc = "6: Gated Mode."]
20    Gated = 6,
21    #[doc = "7: Capture/Compare Mode."]
22    CaptureCompare = 7,
23}
24impl From<Tmode> for u8 {
25    #[inline(always)]
26    fn from(variant: Tmode) -> Self {
27        variant as _
28    }
29}
30impl crate::FieldSpec for Tmode {
31    type Ux = u8;
32}
33impl crate::IsEnum for Tmode {}
34#[doc = "Field `TMODE` reader - Timer Mode."]
35pub type TmodeR = crate::FieldReader<Tmode>;
36impl TmodeR {
37    #[doc = "Get enumerated values variant"]
38    #[inline(always)]
39    pub const fn variant(&self) -> Option<Tmode> {
40        match self.bits {
41            0 => Some(Tmode::OneShot),
42            1 => Some(Tmode::Continuous),
43            2 => Some(Tmode::Counter),
44            4 => Some(Tmode::Capture),
45            5 => Some(Tmode::Compare),
46            6 => Some(Tmode::Gated),
47            7 => Some(Tmode::CaptureCompare),
48            _ => None,
49        }
50    }
51    #[doc = "One Shot Mode."]
52    #[inline(always)]
53    pub fn is_one_shot(&self) -> bool {
54        *self == Tmode::OneShot
55    }
56    #[doc = "Continuous Mode."]
57    #[inline(always)]
58    pub fn is_continuous(&self) -> bool {
59        *self == Tmode::Continuous
60    }
61    #[doc = "Counter Mode."]
62    #[inline(always)]
63    pub fn is_counter(&self) -> bool {
64        *self == Tmode::Counter
65    }
66    #[doc = "Capture Mode."]
67    #[inline(always)]
68    pub fn is_capture(&self) -> bool {
69        *self == Tmode::Capture
70    }
71    #[doc = "Compare Mode."]
72    #[inline(always)]
73    pub fn is_compare(&self) -> bool {
74        *self == Tmode::Compare
75    }
76    #[doc = "Gated Mode."]
77    #[inline(always)]
78    pub fn is_gated(&self) -> bool {
79        *self == Tmode::Gated
80    }
81    #[doc = "Capture/Compare Mode."]
82    #[inline(always)]
83    pub fn is_capture_compare(&self) -> bool {
84        *self == Tmode::CaptureCompare
85    }
86}
87#[doc = "Field `TMODE` writer - Timer Mode."]
88pub type TmodeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Tmode>;
89impl<'a, REG> TmodeW<'a, REG>
90where
91    REG: crate::Writable + crate::RegisterSpec,
92    REG::Ux: From<u8>,
93{
94    #[doc = "One Shot Mode."]
95    #[inline(always)]
96    pub fn one_shot(self) -> &'a mut crate::W<REG> {
97        self.variant(Tmode::OneShot)
98    }
99    #[doc = "Continuous Mode."]
100    #[inline(always)]
101    pub fn continuous(self) -> &'a mut crate::W<REG> {
102        self.variant(Tmode::Continuous)
103    }
104    #[doc = "Counter Mode."]
105    #[inline(always)]
106    pub fn counter(self) -> &'a mut crate::W<REG> {
107        self.variant(Tmode::Counter)
108    }
109    #[doc = "Capture Mode."]
110    #[inline(always)]
111    pub fn capture(self) -> &'a mut crate::W<REG> {
112        self.variant(Tmode::Capture)
113    }
114    #[doc = "Compare Mode."]
115    #[inline(always)]
116    pub fn compare(self) -> &'a mut crate::W<REG> {
117        self.variant(Tmode::Compare)
118    }
119    #[doc = "Gated Mode."]
120    #[inline(always)]
121    pub fn gated(self) -> &'a mut crate::W<REG> {
122        self.variant(Tmode::Gated)
123    }
124    #[doc = "Capture/Compare Mode."]
125    #[inline(always)]
126    pub fn capture_compare(self) -> &'a mut crate::W<REG> {
127        self.variant(Tmode::CaptureCompare)
128    }
129}
130#[doc = "Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres\\[2:0\\].\n\nValue on reset: 0"]
131#[derive(Clone, Copy, Debug, PartialEq, Eq)]
132#[repr(u8)]
133pub enum Pres {
134    #[doc = "0: Divide by 1."]
135    Div1 = 0,
136    #[doc = "1: Divide by 2."]
137    Div2 = 1,
138    #[doc = "2: Divide by 4."]
139    Div4 = 2,
140    #[doc = "3: Divide by 8."]
141    Div8 = 3,
142    #[doc = "4: Divide by 16."]
143    Div16 = 4,
144    #[doc = "5: Divide by 32."]
145    Div32 = 5,
146    #[doc = "6: Divide by 64."]
147    Div64 = 6,
148    #[doc = "7: Divide by 128."]
149    Div128 = 7,
150}
151impl From<Pres> for u8 {
152    #[inline(always)]
153    fn from(variant: Pres) -> Self {
154        variant as _
155    }
156}
157impl crate::FieldSpec for Pres {
158    type Ux = u8;
159}
160impl crate::IsEnum for Pres {}
161#[doc = "Field `PRES` reader - Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres\\[2:0\\]."]
162pub type PresR = crate::FieldReader<Pres>;
163impl PresR {
164    #[doc = "Get enumerated values variant"]
165    #[inline(always)]
166    pub const fn variant(&self) -> Pres {
167        match self.bits {
168            0 => Pres::Div1,
169            1 => Pres::Div2,
170            2 => Pres::Div4,
171            3 => Pres::Div8,
172            4 => Pres::Div16,
173            5 => Pres::Div32,
174            6 => Pres::Div64,
175            7 => Pres::Div128,
176            _ => unreachable!(),
177        }
178    }
179    #[doc = "Divide by 1."]
180    #[inline(always)]
181    pub fn is_div1(&self) -> bool {
182        *self == Pres::Div1
183    }
184    #[doc = "Divide by 2."]
185    #[inline(always)]
186    pub fn is_div2(&self) -> bool {
187        *self == Pres::Div2
188    }
189    #[doc = "Divide by 4."]
190    #[inline(always)]
191    pub fn is_div4(&self) -> bool {
192        *self == Pres::Div4
193    }
194    #[doc = "Divide by 8."]
195    #[inline(always)]
196    pub fn is_div8(&self) -> bool {
197        *self == Pres::Div8
198    }
199    #[doc = "Divide by 16."]
200    #[inline(always)]
201    pub fn is_div16(&self) -> bool {
202        *self == Pres::Div16
203    }
204    #[doc = "Divide by 32."]
205    #[inline(always)]
206    pub fn is_div32(&self) -> bool {
207        *self == Pres::Div32
208    }
209    #[doc = "Divide by 64."]
210    #[inline(always)]
211    pub fn is_div64(&self) -> bool {
212        *self == Pres::Div64
213    }
214    #[doc = "Divide by 128."]
215    #[inline(always)]
216    pub fn is_div128(&self) -> bool {
217        *self == Pres::Div128
218    }
219}
220#[doc = "Field `PRES` writer - Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres\\[2:0\\]."]
221pub type PresW<'a, REG> = crate::FieldWriter<'a, REG, 3, Pres, crate::Safe>;
222impl<'a, REG> PresW<'a, REG>
223where
224    REG: crate::Writable + crate::RegisterSpec,
225    REG::Ux: From<u8>,
226{
227    #[doc = "Divide by 1."]
228    #[inline(always)]
229    pub fn div1(self) -> &'a mut crate::W<REG> {
230        self.variant(Pres::Div1)
231    }
232    #[doc = "Divide by 2."]
233    #[inline(always)]
234    pub fn div2(self) -> &'a mut crate::W<REG> {
235        self.variant(Pres::Div2)
236    }
237    #[doc = "Divide by 4."]
238    #[inline(always)]
239    pub fn div4(self) -> &'a mut crate::W<REG> {
240        self.variant(Pres::Div4)
241    }
242    #[doc = "Divide by 8."]
243    #[inline(always)]
244    pub fn div8(self) -> &'a mut crate::W<REG> {
245        self.variant(Pres::Div8)
246    }
247    #[doc = "Divide by 16."]
248    #[inline(always)]
249    pub fn div16(self) -> &'a mut crate::W<REG> {
250        self.variant(Pres::Div16)
251    }
252    #[doc = "Divide by 32."]
253    #[inline(always)]
254    pub fn div32(self) -> &'a mut crate::W<REG> {
255        self.variant(Pres::Div32)
256    }
257    #[doc = "Divide by 64."]
258    #[inline(always)]
259    pub fn div64(self) -> &'a mut crate::W<REG> {
260        self.variant(Pres::Div64)
261    }
262    #[doc = "Divide by 128."]
263    #[inline(always)]
264    pub fn div128(self) -> &'a mut crate::W<REG> {
265        self.variant(Pres::Div128)
266    }
267}
268#[doc = "Timer input/output polarity bit.\n\nValue on reset: 0"]
269#[derive(Clone, Copy, Debug, PartialEq, Eq)]
270pub enum Tpol {
271    #[doc = "0: Active High."]
272    ActiveHi = 0,
273    #[doc = "1: Active Low."]
274    ActiveLo = 1,
275}
276impl From<Tpol> for bool {
277    #[inline(always)]
278    fn from(variant: Tpol) -> Self {
279        variant as u8 != 0
280    }
281}
282#[doc = "Field `TPOL` reader - Timer input/output polarity bit."]
283pub type TpolR = crate::BitReader<Tpol>;
284impl TpolR {
285    #[doc = "Get enumerated values variant"]
286    #[inline(always)]
287    pub const fn variant(&self) -> Tpol {
288        match self.bits {
289            false => Tpol::ActiveHi,
290            true => Tpol::ActiveLo,
291        }
292    }
293    #[doc = "Active High."]
294    #[inline(always)]
295    pub fn is_active_hi(&self) -> bool {
296        *self == Tpol::ActiveHi
297    }
298    #[doc = "Active Low."]
299    #[inline(always)]
300    pub fn is_active_lo(&self) -> bool {
301        *self == Tpol::ActiveLo
302    }
303}
304#[doc = "Field `TPOL` writer - Timer input/output polarity bit."]
305pub type TpolW<'a, REG> = crate::BitWriter<'a, REG, Tpol>;
306impl<'a, REG> TpolW<'a, REG>
307where
308    REG: crate::Writable + crate::RegisterSpec,
309{
310    #[doc = "Active High."]
311    #[inline(always)]
312    pub fn active_hi(self) -> &'a mut crate::W<REG> {
313        self.variant(Tpol::ActiveHi)
314    }
315    #[doc = "Active Low."]
316    #[inline(always)]
317    pub fn active_lo(self) -> &'a mut crate::W<REG> {
318        self.variant(Tpol::ActiveLo)
319    }
320}
321#[doc = "Timer Enable.\n\nValue on reset: 0"]
322#[derive(Clone, Copy, Debug, PartialEq, Eq)]
323pub enum Ten {
324    #[doc = "0: Disable."]
325    Dis = 0,
326    #[doc = "1: Enable."]
327    En = 1,
328}
329impl From<Ten> for bool {
330    #[inline(always)]
331    fn from(variant: Ten) -> Self {
332        variant as u8 != 0
333    }
334}
335#[doc = "Field `TEN` reader - Timer Enable."]
336pub type TenR = crate::BitReader<Ten>;
337impl TenR {
338    #[doc = "Get enumerated values variant"]
339    #[inline(always)]
340    pub const fn variant(&self) -> Ten {
341        match self.bits {
342            false => Ten::Dis,
343            true => Ten::En,
344        }
345    }
346    #[doc = "Disable."]
347    #[inline(always)]
348    pub fn is_dis(&self) -> bool {
349        *self == Ten::Dis
350    }
351    #[doc = "Enable."]
352    #[inline(always)]
353    pub fn is_en(&self) -> bool {
354        *self == Ten::En
355    }
356}
357#[doc = "Field `TEN` writer - Timer Enable."]
358pub type TenW<'a, REG> = crate::BitWriter<'a, REG, Ten>;
359impl<'a, REG> TenW<'a, REG>
360where
361    REG: crate::Writable + crate::RegisterSpec,
362{
363    #[doc = "Disable."]
364    #[inline(always)]
365    pub fn dis(self) -> &'a mut crate::W<REG> {
366        self.variant(Ten::Dis)
367    }
368    #[doc = "Enable."]
369    #[inline(always)]
370    pub fn en(self) -> &'a mut crate::W<REG> {
371        self.variant(Ten::En)
372    }
373}
374#[doc = "Field `PRES3` reader - MSB of prescaler value."]
375pub type Pres3R = crate::BitReader;
376#[doc = "Field `PRES3` writer - MSB of prescaler value."]
377pub type Pres3W<'a, REG> = crate::BitWriter<'a, REG>;
378impl R {
379    #[doc = "Bits 0:2 - Timer Mode."]
380    #[inline(always)]
381    pub fn tmode(&self) -> TmodeR {
382        TmodeR::new((self.bits & 7) as u8)
383    }
384    #[doc = "Bits 3:5 - Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres\\[2:0\\]."]
385    #[inline(always)]
386    pub fn pres(&self) -> PresR {
387        PresR::new(((self.bits >> 3) & 7) as u8)
388    }
389    #[doc = "Bit 6 - Timer input/output polarity bit."]
390    #[inline(always)]
391    pub fn tpol(&self) -> TpolR {
392        TpolR::new(((self.bits >> 6) & 1) != 0)
393    }
394    #[doc = "Bit 7 - Timer Enable."]
395    #[inline(always)]
396    pub fn ten(&self) -> TenR {
397        TenR::new(((self.bits >> 7) & 1) != 0)
398    }
399    #[doc = "Bit 8 - MSB of prescaler value."]
400    #[inline(always)]
401    pub fn pres3(&self) -> Pres3R {
402        Pres3R::new(((self.bits >> 8) & 1) != 0)
403    }
404}
405impl W {
406    #[doc = "Bits 0:2 - Timer Mode."]
407    #[inline(always)]
408    pub fn tmode(&mut self) -> TmodeW<CtrlSpec> {
409        TmodeW::new(self, 0)
410    }
411    #[doc = "Bits 3:5 - Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres\\[2:0\\]."]
412    #[inline(always)]
413    pub fn pres(&mut self) -> PresW<CtrlSpec> {
414        PresW::new(self, 3)
415    }
416    #[doc = "Bit 6 - Timer input/output polarity bit."]
417    #[inline(always)]
418    pub fn tpol(&mut self) -> TpolW<CtrlSpec> {
419        TpolW::new(self, 6)
420    }
421    #[doc = "Bit 7 - Timer Enable."]
422    #[inline(always)]
423    pub fn ten(&mut self) -> TenW<CtrlSpec> {
424        TenW::new(self, 7)
425    }
426    #[doc = "Bit 8 - MSB of prescaler value."]
427    #[inline(always)]
428    pub fn pres3(&mut self) -> Pres3W<CtrlSpec> {
429        Pres3W::new(self, 8)
430    }
431}
432#[doc = "Timer Control Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
433pub struct CtrlSpec;
434impl crate::RegisterSpec for CtrlSpec {
435    type Ux = u32;
436}
437#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
438impl crate::Readable for CtrlSpec {}
439#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
440impl crate::Writable for CtrlSpec {
441    type Safety = crate::Unsafe;
442    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
443    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
444}
445#[doc = "`reset()` method sets CTRL to value 0"]
446impl crate::Resettable for CtrlSpec {
447    const RESET_VALUE: u32 = 0;
448}
max78000_pac/wut/ctrl.rs

max78000_pac/wut/
ctrl.rs
