1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum En {
8 #[doc = "0: Disable."]
9 Dis = 0,
10 #[doc = "1: Enable."]
11 En = 1,
12}
13impl From<En> for bool {
14 #[inline(always)]
15 fn from(variant: En) -> Self {
16 variant as u8 != 0
17 }
18}
19#[doc = "Field `EN` reader - Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
20pub type EnR = crate::BitReader<En>;
21impl EnR {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> En {
25 match self.bits {
26 false => En::Dis,
27 true => En::En,
28 }
29 }
30 #[doc = "Disable."]
31 #[inline(always)]
32 pub fn is_dis(&self) -> bool {
33 *self == En::Dis
34 }
35 #[doc = "Enable."]
36 #[inline(always)]
37 pub fn is_en(&self) -> bool {
38 *self == En::En
39 }
40}
41#[doc = "Field `EN` writer - Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
42pub type EnW<'a, REG> = crate::BitWriter<'a, REG, En>;
43impl<'a, REG> EnW<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "Disable."]
48 #[inline(always)]
49 pub fn dis(self) -> &'a mut crate::W<REG> {
50 self.variant(En::Dis)
51 }
52 #[doc = "Enable."]
53 #[inline(always)]
54 pub fn en(self) -> &'a mut crate::W<REG> {
55 self.variant(En::En)
56 }
57}
58#[doc = "Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum TodAlarmIe {
61 #[doc = "0: Disable."]
62 Dis = 0,
63 #[doc = "1: Enable."]
64 En = 1,
65}
66impl From<TodAlarmIe> for bool {
67 #[inline(always)]
68 fn from(variant: TodAlarmIe) -> Self {
69 variant as u8 != 0
70 }
71}
72#[doc = "Field `TOD_ALARM_IE` reader - Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
73pub type TodAlarmIeR = crate::BitReader<TodAlarmIe>;
74impl TodAlarmIeR {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub const fn variant(&self) -> TodAlarmIe {
78 match self.bits {
79 false => TodAlarmIe::Dis,
80 true => TodAlarmIe::En,
81 }
82 }
83 #[doc = "Disable."]
84 #[inline(always)]
85 pub fn is_dis(&self) -> bool {
86 *self == TodAlarmIe::Dis
87 }
88 #[doc = "Enable."]
89 #[inline(always)]
90 pub fn is_en(&self) -> bool {
91 *self == TodAlarmIe::En
92 }
93}
94#[doc = "Field `TOD_ALARM_IE` writer - Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
95pub type TodAlarmIeW<'a, REG> = crate::BitWriter<'a, REG, TodAlarmIe>;
96impl<'a, REG> TodAlarmIeW<'a, REG>
97where
98 REG: crate::Writable + crate::RegisterSpec,
99{
100 #[doc = "Disable."]
101 #[inline(always)]
102 pub fn dis(self) -> &'a mut crate::W<REG> {
103 self.variant(TodAlarmIe::Dis)
104 }
105 #[doc = "Enable."]
106 #[inline(always)]
107 pub fn en(self) -> &'a mut crate::W<REG> {
108 self.variant(TodAlarmIe::En)
109 }
110}
111#[doc = "Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum SsecAlarmIe {
114 #[doc = "0: Disable."]
115 Dis = 0,
116 #[doc = "1: Enable."]
117 En = 1,
118}
119impl From<SsecAlarmIe> for bool {
120 #[inline(always)]
121 fn from(variant: SsecAlarmIe) -> Self {
122 variant as u8 != 0
123 }
124}
125#[doc = "Field `SSEC_ALARM_IE` reader - Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
126pub type SsecAlarmIeR = crate::BitReader<SsecAlarmIe>;
127impl SsecAlarmIeR {
128 #[doc = "Get enumerated values variant"]
129 #[inline(always)]
130 pub const fn variant(&self) -> SsecAlarmIe {
131 match self.bits {
132 false => SsecAlarmIe::Dis,
133 true => SsecAlarmIe::En,
134 }
135 }
136 #[doc = "Disable."]
137 #[inline(always)]
138 pub fn is_dis(&self) -> bool {
139 *self == SsecAlarmIe::Dis
140 }
141 #[doc = "Enable."]
142 #[inline(always)]
143 pub fn is_en(&self) -> bool {
144 *self == SsecAlarmIe::En
145 }
146}
147#[doc = "Field `SSEC_ALARM_IE` writer - Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
148pub type SsecAlarmIeW<'a, REG> = crate::BitWriter<'a, REG, SsecAlarmIe>;
149impl<'a, REG> SsecAlarmIeW<'a, REG>
150where
151 REG: crate::Writable + crate::RegisterSpec,
152{
153 #[doc = "Disable."]
154 #[inline(always)]
155 pub fn dis(self) -> &'a mut crate::W<REG> {
156 self.variant(SsecAlarmIe::Dis)
157 }
158 #[doc = "Enable."]
159 #[inline(always)]
160 pub fn en(self) -> &'a mut crate::W<REG> {
161 self.variant(SsecAlarmIe::En)
162 }
163}
164#[doc = "RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.\n\nValue on reset: 1"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum Busy {
167 #[doc = "0: Idle."]
168 Idle = 0,
169 #[doc = "1: Busy."]
170 Busy = 1,
171}
172impl From<Busy> for bool {
173 #[inline(always)]
174 fn from(variant: Busy) -> Self {
175 variant as u8 != 0
176 }
177}
178#[doc = "Field `BUSY` reader - RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware."]
179pub type BusyR = crate::BitReader<Busy>;
180impl BusyR {
181 #[doc = "Get enumerated values variant"]
182 #[inline(always)]
183 pub const fn variant(&self) -> Busy {
184 match self.bits {
185 false => Busy::Idle,
186 true => Busy::Busy,
187 }
188 }
189 #[doc = "Idle."]
190 #[inline(always)]
191 pub fn is_idle(&self) -> bool {
192 *self == Busy::Idle
193 }
194 #[doc = "Busy."]
195 #[inline(always)]
196 pub fn is_busy(&self) -> bool {
197 *self == Busy::Busy
198 }
199}
200#[doc = "RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.\n\nValue on reset: 0"]
201#[derive(Clone, Copy, Debug, PartialEq, Eq)]
202pub enum Rdy {
203 #[doc = "0: Register has not updated."]
204 Busy = 0,
205 #[doc = "1: Ready."]
206 Ready = 1,
207}
208impl From<Rdy> for bool {
209 #[inline(always)]
210 fn from(variant: Rdy) -> Self {
211 variant as u8 != 0
212 }
213}
214#[doc = "Field `RDY` reader - RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register."]
215pub type RdyR = crate::BitReader<Rdy>;
216impl RdyR {
217 #[doc = "Get enumerated values variant"]
218 #[inline(always)]
219 pub const fn variant(&self) -> Rdy {
220 match self.bits {
221 false => Rdy::Busy,
222 true => Rdy::Ready,
223 }
224 }
225 #[doc = "Register has not updated."]
226 #[inline(always)]
227 pub fn is_busy(&self) -> bool {
228 *self == Rdy::Busy
229 }
230 #[doc = "Ready."]
231 #[inline(always)]
232 pub fn is_ready(&self) -> bool {
233 *self == Rdy::Ready
234 }
235}
236#[doc = "Field `RDY` writer - RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register."]
237pub type RdyW<'a, REG> = crate::BitWriter<'a, REG, Rdy>;
238impl<'a, REG> RdyW<'a, REG>
239where
240 REG: crate::Writable + crate::RegisterSpec,
241{
242 #[doc = "Register has not updated."]
243 #[inline(always)]
244 pub fn busy(self) -> &'a mut crate::W<REG> {
245 self.variant(Rdy::Busy)
246 }
247 #[doc = "Ready."]
248 #[inline(always)]
249 pub fn ready(self) -> &'a mut crate::W<REG> {
250 self.variant(Rdy::Ready)
251 }
252}
253#[doc = "RTC Ready Interrupt Enable.\n\nValue on reset: 0"]
254#[derive(Clone, Copy, Debug, PartialEq, Eq)]
255pub enum RdyIe {
256 #[doc = "0: Disable."]
257 Dis = 0,
258 #[doc = "1: Enable."]
259 En = 1,
260}
261impl From<RdyIe> for bool {
262 #[inline(always)]
263 fn from(variant: RdyIe) -> Self {
264 variant as u8 != 0
265 }
266}
267#[doc = "Field `RDY_IE` reader - RTC Ready Interrupt Enable."]
268pub type RdyIeR = crate::BitReader<RdyIe>;
269impl RdyIeR {
270 #[doc = "Get enumerated values variant"]
271 #[inline(always)]
272 pub const fn variant(&self) -> RdyIe {
273 match self.bits {
274 false => RdyIe::Dis,
275 true => RdyIe::En,
276 }
277 }
278 #[doc = "Disable."]
279 #[inline(always)]
280 pub fn is_dis(&self) -> bool {
281 *self == RdyIe::Dis
282 }
283 #[doc = "Enable."]
284 #[inline(always)]
285 pub fn is_en(&self) -> bool {
286 *self == RdyIe::En
287 }
288}
289#[doc = "Field `RDY_IE` writer - RTC Ready Interrupt Enable."]
290pub type RdyIeW<'a, REG> = crate::BitWriter<'a, REG, RdyIe>;
291impl<'a, REG> RdyIeW<'a, REG>
292where
293 REG: crate::Writable + crate::RegisterSpec,
294{
295 #[doc = "Disable."]
296 #[inline(always)]
297 pub fn dis(self) -> &'a mut crate::W<REG> {
298 self.variant(RdyIe::Dis)
299 }
300 #[doc = "Enable."]
301 #[inline(always)]
302 pub fn en(self) -> &'a mut crate::W<REG> {
303 self.variant(RdyIe::En)
304 }
305}
306#[doc = "Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.\n\nValue on reset: 0"]
307#[derive(Clone, Copy, Debug, PartialEq, Eq)]
308pub enum TodAlarm {
309 #[doc = "0: Not active"]
310 Inactive = 0,
311 #[doc = "1: Active"]
312 Pending = 1,
313}
314impl From<TodAlarm> for bool {
315 #[inline(always)]
316 fn from(variant: TodAlarm) -> Self {
317 variant as u8 != 0
318 }
319}
320#[doc = "Field `TOD_ALARM` reader - Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor."]
321pub type TodAlarmR = crate::BitReader<TodAlarm>;
322impl TodAlarmR {
323 #[doc = "Get enumerated values variant"]
324 #[inline(always)]
325 pub const fn variant(&self) -> TodAlarm {
326 match self.bits {
327 false => TodAlarm::Inactive,
328 true => TodAlarm::Pending,
329 }
330 }
331 #[doc = "Not active"]
332 #[inline(always)]
333 pub fn is_inactive(&self) -> bool {
334 *self == TodAlarm::Inactive
335 }
336 #[doc = "Active"]
337 #[inline(always)]
338 pub fn is_pending(&self) -> bool {
339 *self == TodAlarm::Pending
340 }
341}
342#[doc = "Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.\n\nValue on reset: 0"]
343#[derive(Clone, Copy, Debug, PartialEq, Eq)]
344pub enum SsecAlarm {
345 #[doc = "0: Not active"]
346 Inactive = 0,
347 #[doc = "1: Active"]
348 Pending = 1,
349}
350impl From<SsecAlarm> for bool {
351 #[inline(always)]
352 fn from(variant: SsecAlarm) -> Self {
353 variant as u8 != 0
354 }
355}
356#[doc = "Field `SSEC_ALARM` reader - Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor."]
357pub type SsecAlarmR = crate::BitReader<SsecAlarm>;
358impl SsecAlarmR {
359 #[doc = "Get enumerated values variant"]
360 #[inline(always)]
361 pub const fn variant(&self) -> SsecAlarm {
362 match self.bits {
363 false => SsecAlarm::Inactive,
364 true => SsecAlarm::Pending,
365 }
366 }
367 #[doc = "Not active"]
368 #[inline(always)]
369 pub fn is_inactive(&self) -> bool {
370 *self == SsecAlarm::Inactive
371 }
372 #[doc = "Active"]
373 #[inline(always)]
374 pub fn is_pending(&self) -> bool {
375 *self == SsecAlarm::Pending
376 }
377}
378#[doc = "Square Wave Output Enable.\n\nValue on reset: 0"]
379#[derive(Clone, Copy, Debug, PartialEq, Eq)]
380pub enum SqwEn {
381 #[doc = "0: Not active"]
382 Inactive = 0,
383 #[doc = "1: Active"]
384 Pending = 1,
385}
386impl From<SqwEn> for bool {
387 #[inline(always)]
388 fn from(variant: SqwEn) -> Self {
389 variant as u8 != 0
390 }
391}
392#[doc = "Field `SQW_EN` reader - Square Wave Output Enable."]
393pub type SqwEnR = crate::BitReader<SqwEn>;
394impl SqwEnR {
395 #[doc = "Get enumerated values variant"]
396 #[inline(always)]
397 pub const fn variant(&self) -> SqwEn {
398 match self.bits {
399 false => SqwEn::Inactive,
400 true => SqwEn::Pending,
401 }
402 }
403 #[doc = "Not active"]
404 #[inline(always)]
405 pub fn is_inactive(&self) -> bool {
406 *self == SqwEn::Inactive
407 }
408 #[doc = "Active"]
409 #[inline(always)]
410 pub fn is_pending(&self) -> bool {
411 *self == SqwEn::Pending
412 }
413}
414#[doc = "Field `SQW_EN` writer - Square Wave Output Enable."]
415pub type SqwEnW<'a, REG> = crate::BitWriter<'a, REG, SqwEn>;
416impl<'a, REG> SqwEnW<'a, REG>
417where
418 REG: crate::Writable + crate::RegisterSpec,
419{
420 #[doc = "Not active"]
421 #[inline(always)]
422 pub fn inactive(self) -> &'a mut crate::W<REG> {
423 self.variant(SqwEn::Inactive)
424 }
425 #[doc = "Active"]
426 #[inline(always)]
427 pub fn pending(self) -> &'a mut crate::W<REG> {
428 self.variant(SqwEn::Pending)
429 }
430}
431#[doc = "Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.\n\nValue on reset: 0"]
432#[derive(Clone, Copy, Debug, PartialEq, Eq)]
433#[repr(u8)]
434pub enum SqwSel {
435 #[doc = "0: 1 Hz (Compensated)."]
436 Freq1hz = 0,
437 #[doc = "1: 512 Hz (Compensated)."]
438 Freq512hz = 1,
439 #[doc = "2: 4 KHz."]
440 Freq4khz = 2,
441 #[doc = "3: RTC Input Clock / 8."]
442 ClkDiv8 = 3,
443}
444impl From<SqwSel> for u8 {
445 #[inline(always)]
446 fn from(variant: SqwSel) -> Self {
447 variant as _
448 }
449}
450impl crate::FieldSpec for SqwSel {
451 type Ux = u8;
452}
453impl crate::IsEnum for SqwSel {}
454#[doc = "Field `SQW_SEL` reader - Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin."]
455pub type SqwSelR = crate::FieldReader<SqwSel>;
456impl SqwSelR {
457 #[doc = "Get enumerated values variant"]
458 #[inline(always)]
459 pub const fn variant(&self) -> SqwSel {
460 match self.bits {
461 0 => SqwSel::Freq1hz,
462 1 => SqwSel::Freq512hz,
463 2 => SqwSel::Freq4khz,
464 3 => SqwSel::ClkDiv8,
465 _ => unreachable!(),
466 }
467 }
468 #[doc = "1 Hz (Compensated)."]
469 #[inline(always)]
470 pub fn is_freq1hz(&self) -> bool {
471 *self == SqwSel::Freq1hz
472 }
473 #[doc = "512 Hz (Compensated)."]
474 #[inline(always)]
475 pub fn is_freq512hz(&self) -> bool {
476 *self == SqwSel::Freq512hz
477 }
478 #[doc = "4 KHz."]
479 #[inline(always)]
480 pub fn is_freq4khz(&self) -> bool {
481 *self == SqwSel::Freq4khz
482 }
483 #[doc = "RTC Input Clock / 8."]
484 #[inline(always)]
485 pub fn is_clk_div8(&self) -> bool {
486 *self == SqwSel::ClkDiv8
487 }
488}
489#[doc = "Field `SQW_SEL` writer - Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin."]
490pub type SqwSelW<'a, REG> = crate::FieldWriter<'a, REG, 2, SqwSel, crate::Safe>;
491impl<'a, REG> SqwSelW<'a, REG>
492where
493 REG: crate::Writable + crate::RegisterSpec,
494 REG::Ux: From<u8>,
495{
496 #[doc = "1 Hz (Compensated)."]
497 #[inline(always)]
498 pub fn freq1hz(self) -> &'a mut crate::W<REG> {
499 self.variant(SqwSel::Freq1hz)
500 }
501 #[doc = "512 Hz (Compensated)."]
502 #[inline(always)]
503 pub fn freq512hz(self) -> &'a mut crate::W<REG> {
504 self.variant(SqwSel::Freq512hz)
505 }
506 #[doc = "4 KHz."]
507 #[inline(always)]
508 pub fn freq4khz(self) -> &'a mut crate::W<REG> {
509 self.variant(SqwSel::Freq4khz)
510 }
511 #[doc = "RTC Input Clock / 8."]
512 #[inline(always)]
513 pub fn clk_div8(self) -> &'a mut crate::W<REG> {
514 self.variant(SqwSel::ClkDiv8)
515 }
516}
517#[doc = "Field `RD_EN` reader - Asynchronous Counter Read Enable."]
518pub type RdEnR = crate::BitReader;
519#[doc = "Field `RD_EN` writer - Asynchronous Counter Read Enable."]
520pub type RdEnW<'a, REG> = crate::BitWriter<'a, REG>;
521#[doc = "Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.\n\nValue on reset: 0"]
522#[derive(Clone, Copy, Debug, PartialEq, Eq)]
523pub enum WrEn {
524 #[doc = "0: Not active"]
525 Inactive = 0,
526 #[doc = "1: Active"]
527 Pending = 1,
528}
529impl From<WrEn> for bool {
530 #[inline(always)]
531 fn from(variant: WrEn) -> Self {
532 variant as u8 != 0
533 }
534}
535#[doc = "Field `WR_EN` reader - Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits."]
536pub type WrEnR = crate::BitReader<WrEn>;
537impl WrEnR {
538 #[doc = "Get enumerated values variant"]
539 #[inline(always)]
540 pub const fn variant(&self) -> WrEn {
541 match self.bits {
542 false => WrEn::Inactive,
543 true => WrEn::Pending,
544 }
545 }
546 #[doc = "Not active"]
547 #[inline(always)]
548 pub fn is_inactive(&self) -> bool {
549 *self == WrEn::Inactive
550 }
551 #[doc = "Active"]
552 #[inline(always)]
553 pub fn is_pending(&self) -> bool {
554 *self == WrEn::Pending
555 }
556}
557#[doc = "Field `WR_EN` writer - Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits."]
558pub type WrEnW<'a, REG> = crate::BitWriter<'a, REG, WrEn>;
559impl<'a, REG> WrEnW<'a, REG>
560where
561 REG: crate::Writable + crate::RegisterSpec,
562{
563 #[doc = "Not active"]
564 #[inline(always)]
565 pub fn inactive(self) -> &'a mut crate::W<REG> {
566 self.variant(WrEn::Inactive)
567 }
568 #[doc = "Active"]
569 #[inline(always)]
570 pub fn pending(self) -> &'a mut crate::W<REG> {
571 self.variant(WrEn::Pending)
572 }
573}
574impl R {
575 #[doc = "Bit 0 - Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
576 #[inline(always)]
577 pub fn en(&self) -> EnR {
578 EnR::new((self.bits & 1) != 0)
579 }
580 #[doc = "Bit 1 - Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
581 #[inline(always)]
582 pub fn tod_alarm_ie(&self) -> TodAlarmIeR {
583 TodAlarmIeR::new(((self.bits >> 1) & 1) != 0)
584 }
585 #[doc = "Bit 2 - Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
586 #[inline(always)]
587 pub fn ssec_alarm_ie(&self) -> SsecAlarmIeR {
588 SsecAlarmIeR::new(((self.bits >> 2) & 1) != 0)
589 }
590 #[doc = "Bit 3 - RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware."]
591 #[inline(always)]
592 pub fn busy(&self) -> BusyR {
593 BusyR::new(((self.bits >> 3) & 1) != 0)
594 }
595 #[doc = "Bit 4 - RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register."]
596 #[inline(always)]
597 pub fn rdy(&self) -> RdyR {
598 RdyR::new(((self.bits >> 4) & 1) != 0)
599 }
600 #[doc = "Bit 5 - RTC Ready Interrupt Enable."]
601 #[inline(always)]
602 pub fn rdy_ie(&self) -> RdyIeR {
603 RdyIeR::new(((self.bits >> 5) & 1) != 0)
604 }
605 #[doc = "Bit 6 - Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor."]
606 #[inline(always)]
607 pub fn tod_alarm(&self) -> TodAlarmR {
608 TodAlarmR::new(((self.bits >> 6) & 1) != 0)
609 }
610 #[doc = "Bit 7 - Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor."]
611 #[inline(always)]
612 pub fn ssec_alarm(&self) -> SsecAlarmR {
613 SsecAlarmR::new(((self.bits >> 7) & 1) != 0)
614 }
615 #[doc = "Bit 8 - Square Wave Output Enable."]
616 #[inline(always)]
617 pub fn sqw_en(&self) -> SqwEnR {
618 SqwEnR::new(((self.bits >> 8) & 1) != 0)
619 }
620 #[doc = "Bits 9:10 - Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin."]
621 #[inline(always)]
622 pub fn sqw_sel(&self) -> SqwSelR {
623 SqwSelR::new(((self.bits >> 9) & 3) as u8)
624 }
625 #[doc = "Bit 14 - Asynchronous Counter Read Enable."]
626 #[inline(always)]
627 pub fn rd_en(&self) -> RdEnR {
628 RdEnR::new(((self.bits >> 14) & 1) != 0)
629 }
630 #[doc = "Bit 15 - Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits."]
631 #[inline(always)]
632 pub fn wr_en(&self) -> WrEnR {
633 WrEnR::new(((self.bits >> 15) & 1) != 0)
634 }
635}
636impl W {
637 #[doc = "Bit 0 - Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
638 #[inline(always)]
639 pub fn en(&mut self) -> EnW<CtrlSpec> {
640 EnW::new(self, 0)
641 }
642 #[doc = "Bit 1 - Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
643 #[inline(always)]
644 pub fn tod_alarm_ie(&mut self) -> TodAlarmIeW<CtrlSpec> {
645 TodAlarmIeW::new(self, 1)
646 }
647 #[doc = "Bit 2 - Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0."]
648 #[inline(always)]
649 pub fn ssec_alarm_ie(&mut self) -> SsecAlarmIeW<CtrlSpec> {
650 SsecAlarmIeW::new(self, 2)
651 }
652 #[doc = "Bit 4 - RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register."]
653 #[inline(always)]
654 pub fn rdy(&mut self) -> RdyW<CtrlSpec> {
655 RdyW::new(self, 4)
656 }
657 #[doc = "Bit 5 - RTC Ready Interrupt Enable."]
658 #[inline(always)]
659 pub fn rdy_ie(&mut self) -> RdyIeW<CtrlSpec> {
660 RdyIeW::new(self, 5)
661 }
662 #[doc = "Bit 8 - Square Wave Output Enable."]
663 #[inline(always)]
664 pub fn sqw_en(&mut self) -> SqwEnW<CtrlSpec> {
665 SqwEnW::new(self, 8)
666 }
667 #[doc = "Bits 9:10 - Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin."]
668 #[inline(always)]
669 pub fn sqw_sel(&mut self) -> SqwSelW<CtrlSpec> {
670 SqwSelW::new(self, 9)
671 }
672 #[doc = "Bit 14 - Asynchronous Counter Read Enable."]
673 #[inline(always)]
674 pub fn rd_en(&mut self) -> RdEnW<CtrlSpec> {
675 RdEnW::new(self, 14)
676 }
677 #[doc = "Bit 15 - Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits."]
678 #[inline(always)]
679 pub fn wr_en(&mut self) -> WrEnW<CtrlSpec> {
680 WrEnW::new(self, 15)
681 }
682}
683#[doc = "RTC Control Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
684pub struct CtrlSpec;
685impl crate::RegisterSpec for CtrlSpec {
686 type Ux = u32;
687}
688#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
689impl crate::Readable for CtrlSpec {}
690#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
691impl crate::Writable for CtrlSpec {
692 type Safety = crate::Unsafe;
693 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
694 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
695}
696#[doc = "`reset()` method sets CTRL to value 0x08"]
697impl crate::Resettable for CtrlSpec {
698 const RESET_VALUE: u32 = 0x08;
699}