max78000_pac/
owm.rs

1#[repr(C)]
2#[doc = "Register block"]
3pub struct RegisterBlock {
4    cfg: Cfg,
5    clk_div_1us: ClkDiv1us,
6    ctrl_stat: CtrlStat,
7    data: Data,
8    intfl: Intfl,
9    inten: Inten,
10}
11impl RegisterBlock {
12    #[doc = "0x00 - 1-Wire Master Configuration."]
13    #[inline(always)]
14    pub const fn cfg(&self) -> &Cfg {
15        &self.cfg
16    }
17    #[doc = "0x04 - 1-Wire Master Clock Divisor."]
18    #[inline(always)]
19    pub const fn clk_div_1us(&self) -> &ClkDiv1us {
20        &self.clk_div_1us
21    }
22    #[doc = "0x08 - 1-Wire Master Control/Status."]
23    #[inline(always)]
24    pub const fn ctrl_stat(&self) -> &CtrlStat {
25        &self.ctrl_stat
26    }
27    #[doc = "0x0c - 1-Wire Master Data Buffer."]
28    #[inline(always)]
29    pub const fn data(&self) -> &Data {
30        &self.data
31    }
32    #[doc = "0x10 - 1-Wire Master Interrupt Flags."]
33    #[inline(always)]
34    pub const fn intfl(&self) -> &Intfl {
35        &self.intfl
36    }
37    #[doc = "0x14 - 1-Wire Master Interrupt Enables."]
38    #[inline(always)]
39    pub const fn inten(&self) -> &Inten {
40        &self.inten
41    }
42}
43#[doc = "CFG (rw) register accessor: 1-Wire Master Configuration.\n\nYou can [`read`](crate::Reg::read) this register and get [`cfg::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cfg::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cfg`]
44module"]
45#[doc(alias = "CFG")]
46pub type Cfg = crate::Reg<cfg::CfgSpec>;
47#[doc = "1-Wire Master Configuration."]
48pub mod cfg;
49#[doc = "CLK_DIV_1US (rw) register accessor: 1-Wire Master Clock Divisor.\n\nYou can [`read`](crate::Reg::read) this register and get [`clk_div_1us::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clk_div_1us::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@clk_div_1us`]
50module"]
51#[doc(alias = "CLK_DIV_1US")]
52pub type ClkDiv1us = crate::Reg<clk_div_1us::ClkDiv1usSpec>;
53#[doc = "1-Wire Master Clock Divisor."]
54pub mod clk_div_1us;
55#[doc = "CTRL_STAT (rw) register accessor: 1-Wire Master Control/Status.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl_stat::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl_stat::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctrl_stat`]
56module"]
57#[doc(alias = "CTRL_STAT")]
58pub type CtrlStat = crate::Reg<ctrl_stat::CtrlStatSpec>;
59#[doc = "1-Wire Master Control/Status."]
60pub mod ctrl_stat;
61#[doc = "DATA (rw) register accessor: 1-Wire Master Data Buffer.\n\nYou can [`read`](crate::Reg::read) this register and get [`data::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`data::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@data`]
62module"]
63#[doc(alias = "DATA")]
64pub type Data = crate::Reg<data::DataSpec>;
65#[doc = "1-Wire Master Data Buffer."]
66pub mod data;
67#[doc = "INTFL (rw) register accessor: 1-Wire Master Interrupt Flags.\n\nYou can [`read`](crate::Reg::read) this register and get [`intfl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`intfl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@intfl`]
68module"]
69#[doc(alias = "INTFL")]
70pub type Intfl = crate::Reg<intfl::IntflSpec>;
71#[doc = "1-Wire Master Interrupt Flags."]
72pub mod intfl;
73#[doc = "INTEN (rw) register accessor: 1-Wire Master Interrupt Enables.\n\nYou can [`read`](crate::Reg::read) this register and get [`inten::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`inten::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@inten`]
74module"]
75#[doc(alias = "INTEN")]
76pub type Inten = crate::Reg<inten::IntenSpec>;
77#[doc = "1-Wire Master Interrupt Enables."]
78pub mod inten;
max78000_pac/owm.rs

max78000_pac/
owm.rs
