1#[doc = "Register `TXCTRL0` reader"]
2pub type R = crate::R<Txctrl0Spec>;
3#[doc = "Register `TXCTRL0` writer"]
4pub type W = crate::W<Txctrl0Spec>;
5#[doc = "Field `PRELOAD_MODE` reader - Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match."]
6pub type PreloadModeR = crate::BitReader;
7#[doc = "Field `PRELOAD_MODE` writer - Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match."]
8pub type PreloadModeW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Transmit FIFO Ready Manual Mode.\n\nValue on reset: 0"]
10#[derive(Clone, Copy, Debug, PartialEq, Eq)]
11pub enum TxReadyMode {
12 #[doc = "0: HW control of I2CTXRDY enabled."]
13 En = 0,
14 #[doc = "1: HW control of I2CTXRDY disabled."]
15 Dis = 1,
16}
17impl From<TxReadyMode> for bool {
18 #[inline(always)]
19 fn from(variant: TxReadyMode) -> Self {
20 variant as u8 != 0
21 }
22}
23#[doc = "Field `TX_READY_MODE` reader - Transmit FIFO Ready Manual Mode."]
24pub type TxReadyModeR = crate::BitReader<TxReadyMode>;
25impl TxReadyModeR {
26 #[doc = "Get enumerated values variant"]
27 #[inline(always)]
28 pub const fn variant(&self) -> TxReadyMode {
29 match self.bits {
30 false => TxReadyMode::En,
31 true => TxReadyMode::Dis,
32 }
33 }
34 #[doc = "HW control of I2CTXRDY enabled."]
35 #[inline(always)]
36 pub fn is_en(&self) -> bool {
37 *self == TxReadyMode::En
38 }
39 #[doc = "HW control of I2CTXRDY disabled."]
40 #[inline(always)]
41 pub fn is_dis(&self) -> bool {
42 *self == TxReadyMode::Dis
43 }
44}
45#[doc = "Field `TX_READY_MODE` writer - Transmit FIFO Ready Manual Mode."]
46pub type TxReadyModeW<'a, REG> = crate::BitWriter<'a, REG, TxReadyMode>;
47impl<'a, REG> TxReadyModeW<'a, REG>
48where
49 REG: crate::Writable + crate::RegisterSpec,
50{
51 #[doc = "HW control of I2CTXRDY enabled."]
52 #[inline(always)]
53 pub fn en(self) -> &'a mut crate::W<REG> {
54 self.variant(TxReadyMode::En)
55 }
56 #[doc = "HW control of I2CTXRDY disabled."]
57 #[inline(always)]
58 pub fn dis(self) -> &'a mut crate::W<REG> {
59 self.variant(TxReadyMode::Dis)
60 }
61}
62#[doc = "TX FIFO General Call Address Match Auto Flush Disable.\n\nValue on reset: 0"]
63#[derive(Clone, Copy, Debug, PartialEq, Eq)]
64pub enum GcAddrFlushDis {
65 #[doc = "0: Enabled."]
66 En = 0,
67 #[doc = "1: Disabled."]
68 Dis = 1,
69}
70impl From<GcAddrFlushDis> for bool {
71 #[inline(always)]
72 fn from(variant: GcAddrFlushDis) -> Self {
73 variant as u8 != 0
74 }
75}
76#[doc = "Field `GC_ADDR_FLUSH_DIS` reader - TX FIFO General Call Address Match Auto Flush Disable."]
77pub type GcAddrFlushDisR = crate::BitReader<GcAddrFlushDis>;
78impl GcAddrFlushDisR {
79 #[doc = "Get enumerated values variant"]
80 #[inline(always)]
81 pub const fn variant(&self) -> GcAddrFlushDis {
82 match self.bits {
83 false => GcAddrFlushDis::En,
84 true => GcAddrFlushDis::Dis,
85 }
86 }
87 #[doc = "Enabled."]
88 #[inline(always)]
89 pub fn is_en(&self) -> bool {
90 *self == GcAddrFlushDis::En
91 }
92 #[doc = "Disabled."]
93 #[inline(always)]
94 pub fn is_dis(&self) -> bool {
95 *self == GcAddrFlushDis::Dis
96 }
97}
98#[doc = "Field `GC_ADDR_FLUSH_DIS` writer - TX FIFO General Call Address Match Auto Flush Disable."]
99pub type GcAddrFlushDisW<'a, REG> = crate::BitWriter<'a, REG, GcAddrFlushDis>;
100impl<'a, REG> GcAddrFlushDisW<'a, REG>
101where
102 REG: crate::Writable + crate::RegisterSpec,
103{
104 #[doc = "Enabled."]
105 #[inline(always)]
106 pub fn en(self) -> &'a mut crate::W<REG> {
107 self.variant(GcAddrFlushDis::En)
108 }
109 #[doc = "Disabled."]
110 #[inline(always)]
111 pub fn dis(self) -> &'a mut crate::W<REG> {
112 self.variant(GcAddrFlushDis::Dis)
113 }
114}
115#[doc = "TX FIFO Slave Address Match Write Auto Flush Disable.\n\nValue on reset: 0"]
116#[derive(Clone, Copy, Debug, PartialEq, Eq)]
117pub enum WrAddrFlushDis {
118 #[doc = "0: Enabled."]
119 En = 0,
120 #[doc = "1: Disabled."]
121 Dis = 1,
122}
123impl From<WrAddrFlushDis> for bool {
124 #[inline(always)]
125 fn from(variant: WrAddrFlushDis) -> Self {
126 variant as u8 != 0
127 }
128}
129#[doc = "Field `WR_ADDR_FLUSH_DIS` reader - TX FIFO Slave Address Match Write Auto Flush Disable."]
130pub type WrAddrFlushDisR = crate::BitReader<WrAddrFlushDis>;
131impl WrAddrFlushDisR {
132 #[doc = "Get enumerated values variant"]
133 #[inline(always)]
134 pub const fn variant(&self) -> WrAddrFlushDis {
135 match self.bits {
136 false => WrAddrFlushDis::En,
137 true => WrAddrFlushDis::Dis,
138 }
139 }
140 #[doc = "Enabled."]
141 #[inline(always)]
142 pub fn is_en(&self) -> bool {
143 *self == WrAddrFlushDis::En
144 }
145 #[doc = "Disabled."]
146 #[inline(always)]
147 pub fn is_dis(&self) -> bool {
148 *self == WrAddrFlushDis::Dis
149 }
150}
151#[doc = "Field `WR_ADDR_FLUSH_DIS` writer - TX FIFO Slave Address Match Write Auto Flush Disable."]
152pub type WrAddrFlushDisW<'a, REG> = crate::BitWriter<'a, REG, WrAddrFlushDis>;
153impl<'a, REG> WrAddrFlushDisW<'a, REG>
154where
155 REG: crate::Writable + crate::RegisterSpec,
156{
157 #[doc = "Enabled."]
158 #[inline(always)]
159 pub fn en(self) -> &'a mut crate::W<REG> {
160 self.variant(WrAddrFlushDis::En)
161 }
162 #[doc = "Disabled."]
163 #[inline(always)]
164 pub fn dis(self) -> &'a mut crate::W<REG> {
165 self.variant(WrAddrFlushDis::Dis)
166 }
167}
168#[doc = "TX FIFO Slave Address Match Read Auto Flush Disable.\n\nValue on reset: 0"]
169#[derive(Clone, Copy, Debug, PartialEq, Eq)]
170pub enum RdAddrFlushDis {
171 #[doc = "0: Enabled."]
172 En = 0,
173 #[doc = "1: Disabled."]
174 Dis = 1,
175}
176impl From<RdAddrFlushDis> for bool {
177 #[inline(always)]
178 fn from(variant: RdAddrFlushDis) -> Self {
179 variant as u8 != 0
180 }
181}
182#[doc = "Field `RD_ADDR_FLUSH_DIS` reader - TX FIFO Slave Address Match Read Auto Flush Disable."]
183pub type RdAddrFlushDisR = crate::BitReader<RdAddrFlushDis>;
184impl RdAddrFlushDisR {
185 #[doc = "Get enumerated values variant"]
186 #[inline(always)]
187 pub const fn variant(&self) -> RdAddrFlushDis {
188 match self.bits {
189 false => RdAddrFlushDis::En,
190 true => RdAddrFlushDis::Dis,
191 }
192 }
193 #[doc = "Enabled."]
194 #[inline(always)]
195 pub fn is_en(&self) -> bool {
196 *self == RdAddrFlushDis::En
197 }
198 #[doc = "Disabled."]
199 #[inline(always)]
200 pub fn is_dis(&self) -> bool {
201 *self == RdAddrFlushDis::Dis
202 }
203}
204#[doc = "Field `RD_ADDR_FLUSH_DIS` writer - TX FIFO Slave Address Match Read Auto Flush Disable."]
205pub type RdAddrFlushDisW<'a, REG> = crate::BitWriter<'a, REG, RdAddrFlushDis>;
206impl<'a, REG> RdAddrFlushDisW<'a, REG>
207where
208 REG: crate::Writable + crate::RegisterSpec,
209{
210 #[doc = "Enabled."]
211 #[inline(always)]
212 pub fn en(self) -> &'a mut crate::W<REG> {
213 self.variant(RdAddrFlushDis::En)
214 }
215 #[doc = "Disabled."]
216 #[inline(always)]
217 pub fn dis(self) -> &'a mut crate::W<REG> {
218 self.variant(RdAddrFlushDis::Dis)
219 }
220}
221#[doc = "TX FIFO received NACK Auto Flush Disable.\n\nValue on reset: 0"]
222#[derive(Clone, Copy, Debug, PartialEq, Eq)]
223pub enum NackFlushDis {
224 #[doc = "0: Enabled."]
225 En = 0,
226 #[doc = "1: Disabled."]
227 Dis = 1,
228}
229impl From<NackFlushDis> for bool {
230 #[inline(always)]
231 fn from(variant: NackFlushDis) -> Self {
232 variant as u8 != 0
233 }
234}
235#[doc = "Field `NACK_FLUSH_DIS` reader - TX FIFO received NACK Auto Flush Disable."]
236pub type NackFlushDisR = crate::BitReader<NackFlushDis>;
237impl NackFlushDisR {
238 #[doc = "Get enumerated values variant"]
239 #[inline(always)]
240 pub const fn variant(&self) -> NackFlushDis {
241 match self.bits {
242 false => NackFlushDis::En,
243 true => NackFlushDis::Dis,
244 }
245 }
246 #[doc = "Enabled."]
247 #[inline(always)]
248 pub fn is_en(&self) -> bool {
249 *self == NackFlushDis::En
250 }
251 #[doc = "Disabled."]
252 #[inline(always)]
253 pub fn is_dis(&self) -> bool {
254 *self == NackFlushDis::Dis
255 }
256}
257#[doc = "Field `NACK_FLUSH_DIS` writer - TX FIFO received NACK Auto Flush Disable."]
258pub type NackFlushDisW<'a, REG> = crate::BitWriter<'a, REG, NackFlushDis>;
259impl<'a, REG> NackFlushDisW<'a, REG>
260where
261 REG: crate::Writable + crate::RegisterSpec,
262{
263 #[doc = "Enabled."]
264 #[inline(always)]
265 pub fn en(self) -> &'a mut crate::W<REG> {
266 self.variant(NackFlushDis::En)
267 }
268 #[doc = "Disabled."]
269 #[inline(always)]
270 pub fn dis(self) -> &'a mut crate::W<REG> {
271 self.variant(NackFlushDis::Dis)
272 }
273}
274#[doc = "Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.\n\nValue on reset: 0"]
275#[derive(Clone, Copy, Debug, PartialEq, Eq)]
276pub enum Flush {
277 #[doc = "0: FIFO not flushed."]
278 NotFlushed = 0,
279 #[doc = "1: Flush TX_FIFO."]
280 Flush = 1,
281}
282impl From<Flush> for bool {
283 #[inline(always)]
284 fn from(variant: Flush) -> Self {
285 variant as u8 != 0
286 }
287}
288#[doc = "Field `FLUSH` reader - Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation."]
289pub type FlushR = crate::BitReader<Flush>;
290impl FlushR {
291 #[doc = "Get enumerated values variant"]
292 #[inline(always)]
293 pub const fn variant(&self) -> Flush {
294 match self.bits {
295 false => Flush::NotFlushed,
296 true => Flush::Flush,
297 }
298 }
299 #[doc = "FIFO not flushed."]
300 #[inline(always)]
301 pub fn is_not_flushed(&self) -> bool {
302 *self == Flush::NotFlushed
303 }
304 #[doc = "Flush TX_FIFO."]
305 #[inline(always)]
306 pub fn is_flush(&self) -> bool {
307 *self == Flush::Flush
308 }
309}
310#[doc = "Field `FLUSH` writer - Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation."]
311pub type FlushW<'a, REG> = crate::BitWriter<'a, REG, Flush>;
312impl<'a, REG> FlushW<'a, REG>
313where
314 REG: crate::Writable + crate::RegisterSpec,
315{
316 #[doc = "FIFO not flushed."]
317 #[inline(always)]
318 pub fn not_flushed(self) -> &'a mut crate::W<REG> {
319 self.variant(Flush::NotFlushed)
320 }
321 #[doc = "Flush TX_FIFO."]
322 #[inline(always)]
323 pub fn flush(self) -> &'a mut crate::W<REG> {
324 self.variant(Flush::Flush)
325 }
326}
327#[doc = "Field `THD_VAL` reader - Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."]
328pub type ThdValR = crate::FieldReader;
329#[doc = "Field `THD_VAL` writer - Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."]
330pub type ThdValW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
331impl R {
332 #[doc = "Bit 0 - Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match."]
333 #[inline(always)]
334 pub fn preload_mode(&self) -> PreloadModeR {
335 PreloadModeR::new((self.bits & 1) != 0)
336 }
337 #[doc = "Bit 1 - Transmit FIFO Ready Manual Mode."]
338 #[inline(always)]
339 pub fn tx_ready_mode(&self) -> TxReadyModeR {
340 TxReadyModeR::new(((self.bits >> 1) & 1) != 0)
341 }
342 #[doc = "Bit 2 - TX FIFO General Call Address Match Auto Flush Disable."]
343 #[inline(always)]
344 pub fn gc_addr_flush_dis(&self) -> GcAddrFlushDisR {
345 GcAddrFlushDisR::new(((self.bits >> 2) & 1) != 0)
346 }
347 #[doc = "Bit 3 - TX FIFO Slave Address Match Write Auto Flush Disable."]
348 #[inline(always)]
349 pub fn wr_addr_flush_dis(&self) -> WrAddrFlushDisR {
350 WrAddrFlushDisR::new(((self.bits >> 3) & 1) != 0)
351 }
352 #[doc = "Bit 4 - TX FIFO Slave Address Match Read Auto Flush Disable."]
353 #[inline(always)]
354 pub fn rd_addr_flush_dis(&self) -> RdAddrFlushDisR {
355 RdAddrFlushDisR::new(((self.bits >> 4) & 1) != 0)
356 }
357 #[doc = "Bit 5 - TX FIFO received NACK Auto Flush Disable."]
358 #[inline(always)]
359 pub fn nack_flush_dis(&self) -> NackFlushDisR {
360 NackFlushDisR::new(((self.bits >> 5) & 1) != 0)
361 }
362 #[doc = "Bit 7 - Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation."]
363 #[inline(always)]
364 pub fn flush(&self) -> FlushR {
365 FlushR::new(((self.bits >> 7) & 1) != 0)
366 }
367 #[doc = "Bits 8:11 - Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."]
368 #[inline(always)]
369 pub fn thd_val(&self) -> ThdValR {
370 ThdValR::new(((self.bits >> 8) & 0x0f) as u8)
371 }
372}
373impl W {
374 #[doc = "Bit 0 - Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match."]
375 #[inline(always)]
376 pub fn preload_mode(&mut self) -> PreloadModeW<Txctrl0Spec> {
377 PreloadModeW::new(self, 0)
378 }
379 #[doc = "Bit 1 - Transmit FIFO Ready Manual Mode."]
380 #[inline(always)]
381 pub fn tx_ready_mode(&mut self) -> TxReadyModeW<Txctrl0Spec> {
382 TxReadyModeW::new(self, 1)
383 }
384 #[doc = "Bit 2 - TX FIFO General Call Address Match Auto Flush Disable."]
385 #[inline(always)]
386 pub fn gc_addr_flush_dis(&mut self) -> GcAddrFlushDisW<Txctrl0Spec> {
387 GcAddrFlushDisW::new(self, 2)
388 }
389 #[doc = "Bit 3 - TX FIFO Slave Address Match Write Auto Flush Disable."]
390 #[inline(always)]
391 pub fn wr_addr_flush_dis(&mut self) -> WrAddrFlushDisW<Txctrl0Spec> {
392 WrAddrFlushDisW::new(self, 3)
393 }
394 #[doc = "Bit 4 - TX FIFO Slave Address Match Read Auto Flush Disable."]
395 #[inline(always)]
396 pub fn rd_addr_flush_dis(&mut self) -> RdAddrFlushDisW<Txctrl0Spec> {
397 RdAddrFlushDisW::new(self, 4)
398 }
399 #[doc = "Bit 5 - TX FIFO received NACK Auto Flush Disable."]
400 #[inline(always)]
401 pub fn nack_flush_dis(&mut self) -> NackFlushDisW<Txctrl0Spec> {
402 NackFlushDisW::new(self, 5)
403 }
404 #[doc = "Bit 7 - Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation."]
405 #[inline(always)]
406 pub fn flush(&mut self) -> FlushW<Txctrl0Spec> {
407 FlushW::new(self, 7)
408 }
409 #[doc = "Bits 8:11 - Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold."]
410 #[inline(always)]
411 pub fn thd_val(&mut self) -> ThdValW<Txctrl0Spec> {
412 ThdValW::new(self, 8)
413 }
414}
415#[doc = "Transmit Control Register 0.\n\nYou can [`read`](crate::Reg::read) this register and get [`txctrl0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`txctrl0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
416pub struct Txctrl0Spec;
417impl crate::RegisterSpec for Txctrl0Spec {
418 type Ux = u32;
419}
420#[doc = "`read()` method returns [`txctrl0::R`](R) reader structure"]
421impl crate::Readable for Txctrl0Spec {}
422#[doc = "`write(|w| ..)` method takes [`txctrl0::W`](W) writer structure"]
423impl crate::Writable for Txctrl0Spec {
424 type Safety = crate::Unsafe;
425 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
426 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
427}
428#[doc = "`reset()` method sets TXCTRL0 to value 0"]
429impl crate::Resettable for Txctrl0Spec {
430 const RESET_VALUE: u32 = 0;
431}