max78000_pac/i2c0/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "I2C Enable.\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum En {
8    #[doc = "0: Disable I2C."]
9    Dis = 0,
10    #[doc = "1: enable I2C."]
11    En = 1,
12}
13impl From<En> for bool {
14    #[inline(always)]
15    fn from(variant: En) -> Self {
16        variant as u8 != 0
17    }
18}
19#[doc = "Field `EN` reader - I2C Enable."]
20pub type EnR = crate::BitReader<En>;
21impl EnR {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> En {
25        match self.bits {
26            false => En::Dis,
27            true => En::En,
28        }
29    }
30    #[doc = "Disable I2C."]
31    #[inline(always)]
32    pub fn is_dis(&self) -> bool {
33        *self == En::Dis
34    }
35    #[doc = "enable I2C."]
36    #[inline(always)]
37    pub fn is_en(&self) -> bool {
38        *self == En::En
39    }
40}
41#[doc = "Field `EN` writer - I2C Enable."]
42pub type EnW<'a, REG> = crate::BitWriter<'a, REG, En>;
43impl<'a, REG> EnW<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable I2C."]
48    #[inline(always)]
49    pub fn dis(self) -> &'a mut crate::W<REG> {
50        self.variant(En::Dis)
51    }
52    #[doc = "enable I2C."]
53    #[inline(always)]
54    pub fn en(self) -> &'a mut crate::W<REG> {
55        self.variant(En::En)
56    }
57}
58#[doc = "Master Mode Enable.\n\nValue on reset: 0"]
59#[derive(Clone, Copy, Debug, PartialEq, Eq)]
60pub enum MstMode {
61    #[doc = "0: Slave Mode."]
62    SlaveMode = 0,
63    #[doc = "1: Master Mode."]
64    MasterMode = 1,
65}
66impl From<MstMode> for bool {
67    #[inline(always)]
68    fn from(variant: MstMode) -> Self {
69        variant as u8 != 0
70    }
71}
72#[doc = "Field `MST_MODE` reader - Master Mode Enable."]
73pub type MstModeR = crate::BitReader<MstMode>;
74impl MstModeR {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> MstMode {
78        match self.bits {
79            false => MstMode::SlaveMode,
80            true => MstMode::MasterMode,
81        }
82    }
83    #[doc = "Slave Mode."]
84    #[inline(always)]
85    pub fn is_slave_mode(&self) -> bool {
86        *self == MstMode::SlaveMode
87    }
88    #[doc = "Master Mode."]
89    #[inline(always)]
90    pub fn is_master_mode(&self) -> bool {
91        *self == MstMode::MasterMode
92    }
93}
94#[doc = "Field `MST_MODE` writer - Master Mode Enable."]
95pub type MstModeW<'a, REG> = crate::BitWriter<'a, REG, MstMode>;
96impl<'a, REG> MstModeW<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Slave Mode."]
101    #[inline(always)]
102    pub fn slave_mode(self) -> &'a mut crate::W<REG> {
103        self.variant(MstMode::SlaveMode)
104    }
105    #[doc = "Master Mode."]
106    #[inline(always)]
107    pub fn master_mode(self) -> &'a mut crate::W<REG> {
108        self.variant(MstMode::MasterMode)
109    }
110}
111#[doc = "General Call Address Enable.\n\nValue on reset: 0"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum GcAddrEn {
114    #[doc = "0: Ignore Gneral Call Address."]
115    Dis = 0,
116    #[doc = "1: Acknowledge general call address."]
117    En = 1,
118}
119impl From<GcAddrEn> for bool {
120    #[inline(always)]
121    fn from(variant: GcAddrEn) -> Self {
122        variant as u8 != 0
123    }
124}
125#[doc = "Field `GC_ADDR_EN` reader - General Call Address Enable."]
126pub type GcAddrEnR = crate::BitReader<GcAddrEn>;
127impl GcAddrEnR {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> GcAddrEn {
131        match self.bits {
132            false => GcAddrEn::Dis,
133            true => GcAddrEn::En,
134        }
135    }
136    #[doc = "Ignore Gneral Call Address."]
137    #[inline(always)]
138    pub fn is_dis(&self) -> bool {
139        *self == GcAddrEn::Dis
140    }
141    #[doc = "Acknowledge general call address."]
142    #[inline(always)]
143    pub fn is_en(&self) -> bool {
144        *self == GcAddrEn::En
145    }
146}
147#[doc = "Field `GC_ADDR_EN` writer - General Call Address Enable."]
148pub type GcAddrEnW<'a, REG> = crate::BitWriter<'a, REG, GcAddrEn>;
149impl<'a, REG> GcAddrEnW<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Ignore Gneral Call Address."]
154    #[inline(always)]
155    pub fn dis(self) -> &'a mut crate::W<REG> {
156        self.variant(GcAddrEn::Dis)
157    }
158    #[doc = "Acknowledge general call address."]
159    #[inline(always)]
160    pub fn en(self) -> &'a mut crate::W<REG> {
161        self.variant(GcAddrEn::En)
162    }
163}
164#[doc = "Interactive Receive Mode.\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum IrxmEn {
167    #[doc = "0: Disable Interactive Receive Mode."]
168    Dis = 0,
169    #[doc = "1: Enable Interactive Receive Mode."]
170    En = 1,
171}
172impl From<IrxmEn> for bool {
173    #[inline(always)]
174    fn from(variant: IrxmEn) -> Self {
175        variant as u8 != 0
176    }
177}
178#[doc = "Field `IRXM_EN` reader - Interactive Receive Mode."]
179pub type IrxmEnR = crate::BitReader<IrxmEn>;
180impl IrxmEnR {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> IrxmEn {
184        match self.bits {
185            false => IrxmEn::Dis,
186            true => IrxmEn::En,
187        }
188    }
189    #[doc = "Disable Interactive Receive Mode."]
190    #[inline(always)]
191    pub fn is_dis(&self) -> bool {
192        *self == IrxmEn::Dis
193    }
194    #[doc = "Enable Interactive Receive Mode."]
195    #[inline(always)]
196    pub fn is_en(&self) -> bool {
197        *self == IrxmEn::En
198    }
199}
200#[doc = "Field `IRXM_EN` writer - Interactive Receive Mode."]
201pub type IrxmEnW<'a, REG> = crate::BitWriter<'a, REG, IrxmEn>;
202impl<'a, REG> IrxmEnW<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Disable Interactive Receive Mode."]
207    #[inline(always)]
208    pub fn dis(self) -> &'a mut crate::W<REG> {
209        self.variant(IrxmEn::Dis)
210    }
211    #[doc = "Enable Interactive Receive Mode."]
212    #[inline(always)]
213    pub fn en(self) -> &'a mut crate::W<REG> {
214        self.variant(IrxmEn::En)
215    }
216}
217#[doc = "Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219pub enum IrxmAck {
220    #[doc = "0: return ACK (pulling SDA LOW)."]
221    Ack = 0,
222    #[doc = "1: return NACK (leaving SDA HIGH)."]
223    Nack = 1,
224}
225impl From<IrxmAck> for bool {
226    #[inline(always)]
227    fn from(variant: IrxmAck) -> Self {
228        variant as u8 != 0
229    }
230}
231#[doc = "Field `IRXM_ACK` reader - Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0."]
232pub type IrxmAckR = crate::BitReader<IrxmAck>;
233impl IrxmAckR {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> IrxmAck {
237        match self.bits {
238            false => IrxmAck::Ack,
239            true => IrxmAck::Nack,
240        }
241    }
242    #[doc = "return ACK (pulling SDA LOW)."]
243    #[inline(always)]
244    pub fn is_ack(&self) -> bool {
245        *self == IrxmAck::Ack
246    }
247    #[doc = "return NACK (leaving SDA HIGH)."]
248    #[inline(always)]
249    pub fn is_nack(&self) -> bool {
250        *self == IrxmAck::Nack
251    }
252}
253#[doc = "Field `IRXM_ACK` writer - Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0."]
254pub type IrxmAckW<'a, REG> = crate::BitWriter<'a, REG, IrxmAck>;
255impl<'a, REG> IrxmAckW<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "return ACK (pulling SDA LOW)."]
260    #[inline(always)]
261    pub fn ack(self) -> &'a mut crate::W<REG> {
262        self.variant(IrxmAck::Ack)
263    }
264    #[doc = "return NACK (leaving SDA HIGH)."]
265    #[inline(always)]
266    pub fn nack(self) -> &'a mut crate::W<REG> {
267        self.variant(IrxmAck::Nack)
268    }
269}
270#[doc = "SCL Output. This bits control SCL output when SWOE =1.\n\nValue on reset: 0"]
271#[derive(Clone, Copy, Debug, PartialEq, Eq)]
272pub enum SclOut {
273    #[doc = "0: Drive SCL low."]
274    DriveSclLow = 0,
275    #[doc = "1: Release SCL."]
276    ReleaseScl = 1,
277}
278impl From<SclOut> for bool {
279    #[inline(always)]
280    fn from(variant: SclOut) -> Self {
281        variant as u8 != 0
282    }
283}
284#[doc = "Field `SCL_OUT` reader - SCL Output. This bits control SCL output when SWOE =1."]
285pub type SclOutR = crate::BitReader<SclOut>;
286impl SclOutR {
287    #[doc = "Get enumerated values variant"]
288    #[inline(always)]
289    pub const fn variant(&self) -> SclOut {
290        match self.bits {
291            false => SclOut::DriveSclLow,
292            true => SclOut::ReleaseScl,
293        }
294    }
295    #[doc = "Drive SCL low."]
296    #[inline(always)]
297    pub fn is_drive_scl_low(&self) -> bool {
298        *self == SclOut::DriveSclLow
299    }
300    #[doc = "Release SCL."]
301    #[inline(always)]
302    pub fn is_release_scl(&self) -> bool {
303        *self == SclOut::ReleaseScl
304    }
305}
306#[doc = "Field `SCL_OUT` writer - SCL Output. This bits control SCL output when SWOE =1."]
307pub type SclOutW<'a, REG> = crate::BitWriter<'a, REG, SclOut>;
308impl<'a, REG> SclOutW<'a, REG>
309where
310    REG: crate::Writable + crate::RegisterSpec,
311{
312    #[doc = "Drive SCL low."]
313    #[inline(always)]
314    pub fn drive_scl_low(self) -> &'a mut crate::W<REG> {
315        self.variant(SclOut::DriveSclLow)
316    }
317    #[doc = "Release SCL."]
318    #[inline(always)]
319    pub fn release_scl(self) -> &'a mut crate::W<REG> {
320        self.variant(SclOut::ReleaseScl)
321    }
322}
323#[doc = "SDA Output. This bits control SDA output when SWOE = 1.\n\nValue on reset: 0"]
324#[derive(Clone, Copy, Debug, PartialEq, Eq)]
325pub enum SdaOut {
326    #[doc = "0: Drive SDA low."]
327    DriveSdaLow = 0,
328    #[doc = "1: Release SDA."]
329    ReleaseSda = 1,
330}
331impl From<SdaOut> for bool {
332    #[inline(always)]
333    fn from(variant: SdaOut) -> Self {
334        variant as u8 != 0
335    }
336}
337#[doc = "Field `SDA_OUT` reader - SDA Output. This bits control SDA output when SWOE = 1."]
338pub type SdaOutR = crate::BitReader<SdaOut>;
339impl SdaOutR {
340    #[doc = "Get enumerated values variant"]
341    #[inline(always)]
342    pub const fn variant(&self) -> SdaOut {
343        match self.bits {
344            false => SdaOut::DriveSdaLow,
345            true => SdaOut::ReleaseSda,
346        }
347    }
348    #[doc = "Drive SDA low."]
349    #[inline(always)]
350    pub fn is_drive_sda_low(&self) -> bool {
351        *self == SdaOut::DriveSdaLow
352    }
353    #[doc = "Release SDA."]
354    #[inline(always)]
355    pub fn is_release_sda(&self) -> bool {
356        *self == SdaOut::ReleaseSda
357    }
358}
359#[doc = "Field `SDA_OUT` writer - SDA Output. This bits control SDA output when SWOE = 1."]
360pub type SdaOutW<'a, REG> = crate::BitWriter<'a, REG, SdaOut>;
361impl<'a, REG> SdaOutW<'a, REG>
362where
363    REG: crate::Writable + crate::RegisterSpec,
364{
365    #[doc = "Drive SDA low."]
366    #[inline(always)]
367    pub fn drive_sda_low(self) -> &'a mut crate::W<REG> {
368        self.variant(SdaOut::DriveSdaLow)
369    }
370    #[doc = "Release SDA."]
371    #[inline(always)]
372    pub fn release_sda(self) -> &'a mut crate::W<REG> {
373        self.variant(SdaOut::ReleaseSda)
374    }
375}
376#[doc = "Field `SCL` reader - SCL status. This bit reflects the logic gate of SCL signal."]
377pub type SclR = crate::BitReader;
378#[doc = "Field `SDA` reader - SDA status. THis bit reflects the logic gate of SDA signal."]
379pub type SdaR = crate::BitReader;
380#[doc = "Software Output Enable.\n\nValue on reset: 0"]
381#[derive(Clone, Copy, Debug, PartialEq, Eq)]
382pub enum BbMode {
383    #[doc = "0: I2C Outputs SCLO and SDAO disabled."]
384    OutputsDisable = 0,
385    #[doc = "1: I2C Outputs SCLO and SDAO enabled."]
386    OutputsEnable = 1,
387}
388impl From<BbMode> for bool {
389    #[inline(always)]
390    fn from(variant: BbMode) -> Self {
391        variant as u8 != 0
392    }
393}
394#[doc = "Field `BB_MODE` reader - Software Output Enable."]
395pub type BbModeR = crate::BitReader<BbMode>;
396impl BbModeR {
397    #[doc = "Get enumerated values variant"]
398    #[inline(always)]
399    pub const fn variant(&self) -> BbMode {
400        match self.bits {
401            false => BbMode::OutputsDisable,
402            true => BbMode::OutputsEnable,
403        }
404    }
405    #[doc = "I2C Outputs SCLO and SDAO disabled."]
406    #[inline(always)]
407    pub fn is_outputs_disable(&self) -> bool {
408        *self == BbMode::OutputsDisable
409    }
410    #[doc = "I2C Outputs SCLO and SDAO enabled."]
411    #[inline(always)]
412    pub fn is_outputs_enable(&self) -> bool {
413        *self == BbMode::OutputsEnable
414    }
415}
416#[doc = "Field `BB_MODE` writer - Software Output Enable."]
417pub type BbModeW<'a, REG> = crate::BitWriter<'a, REG, BbMode>;
418impl<'a, REG> BbModeW<'a, REG>
419where
420    REG: crate::Writable + crate::RegisterSpec,
421{
422    #[doc = "I2C Outputs SCLO and SDAO disabled."]
423    #[inline(always)]
424    pub fn outputs_disable(self) -> &'a mut crate::W<REG> {
425        self.variant(BbMode::OutputsDisable)
426    }
427    #[doc = "I2C Outputs SCLO and SDAO enabled."]
428    #[inline(always)]
429    pub fn outputs_enable(self) -> &'a mut crate::W<REG> {
430        self.variant(BbMode::OutputsEnable)
431    }
432}
433#[doc = "Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.\n\nValue on reset: 0"]
434#[derive(Clone, Copy, Debug, PartialEq, Eq)]
435pub enum Read {
436    #[doc = "0: Write."]
437    Write = 0,
438    #[doc = "1: Read."]
439    Read = 1,
440}
441impl From<Read> for bool {
442    #[inline(always)]
443    fn from(variant: Read) -> Self {
444        variant as u8 != 0
445    }
446}
447#[doc = "Field `READ` reader - Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set."]
448pub type ReadR = crate::BitReader<Read>;
449impl ReadR {
450    #[doc = "Get enumerated values variant"]
451    #[inline(always)]
452    pub const fn variant(&self) -> Read {
453        match self.bits {
454            false => Read::Write,
455            true => Read::Read,
456        }
457    }
458    #[doc = "Write."]
459    #[inline(always)]
460    pub fn is_write(&self) -> bool {
461        *self == Read::Write
462    }
463    #[doc = "Read."]
464    #[inline(always)]
465    pub fn is_read(&self) -> bool {
466        *self == Read::Read
467    }
468}
469#[doc = "This bit will disable slave clock stretching when set.\n\nValue on reset: 0"]
470#[derive(Clone, Copy, Debug, PartialEq, Eq)]
471pub enum ClkstrDis {
472    #[doc = "0: Slave clock stretching enabled."]
473    En = 0,
474    #[doc = "1: Slave clock stretching disabled."]
475    Dis = 1,
476}
477impl From<ClkstrDis> for bool {
478    #[inline(always)]
479    fn from(variant: ClkstrDis) -> Self {
480        variant as u8 != 0
481    }
482}
483#[doc = "Field `CLKSTR_DIS` reader - This bit will disable slave clock stretching when set."]
484pub type ClkstrDisR = crate::BitReader<ClkstrDis>;
485impl ClkstrDisR {
486    #[doc = "Get enumerated values variant"]
487    #[inline(always)]
488    pub const fn variant(&self) -> ClkstrDis {
489        match self.bits {
490            false => ClkstrDis::En,
491            true => ClkstrDis::Dis,
492        }
493    }
494    #[doc = "Slave clock stretching enabled."]
495    #[inline(always)]
496    pub fn is_en(&self) -> bool {
497        *self == ClkstrDis::En
498    }
499    #[doc = "Slave clock stretching disabled."]
500    #[inline(always)]
501    pub fn is_dis(&self) -> bool {
502        *self == ClkstrDis::Dis
503    }
504}
505#[doc = "Field `CLKSTR_DIS` writer - This bit will disable slave clock stretching when set."]
506pub type ClkstrDisW<'a, REG> = crate::BitWriter<'a, REG, ClkstrDis>;
507impl<'a, REG> ClkstrDisW<'a, REG>
508where
509    REG: crate::Writable + crate::RegisterSpec,
510{
511    #[doc = "Slave clock stretching enabled."]
512    #[inline(always)]
513    pub fn en(self) -> &'a mut crate::W<REG> {
514        self.variant(ClkstrDis::En)
515    }
516    #[doc = "Slave clock stretching disabled."]
517    #[inline(always)]
518    pub fn dis(self) -> &'a mut crate::W<REG> {
519        self.variant(ClkstrDis::Dis)
520    }
521}
522#[doc = "SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low.\n\nValue on reset: 0"]
523#[derive(Clone, Copy, Debug, PartialEq, Eq)]
524pub enum OneMstMode {
525    #[doc = "0: Standard open-drain operation: drive low for 0, Hi-Z for 1"]
526    Dis = 0,
527    #[doc = "1: Non-standard push-pull operation: drive low for 0, drive high for 1"]
528    En = 1,
529}
530impl From<OneMstMode> for bool {
531    #[inline(always)]
532    fn from(variant: OneMstMode) -> Self {
533        variant as u8 != 0
534    }
535}
536#[doc = "Field `ONE_MST_MODE` reader - SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low."]
537pub type OneMstModeR = crate::BitReader<OneMstMode>;
538impl OneMstModeR {
539    #[doc = "Get enumerated values variant"]
540    #[inline(always)]
541    pub const fn variant(&self) -> OneMstMode {
542        match self.bits {
543            false => OneMstMode::Dis,
544            true => OneMstMode::En,
545        }
546    }
547    #[doc = "Standard open-drain operation: drive low for 0, Hi-Z for 1"]
548    #[inline(always)]
549    pub fn is_dis(&self) -> bool {
550        *self == OneMstMode::Dis
551    }
552    #[doc = "Non-standard push-pull operation: drive low for 0, drive high for 1"]
553    #[inline(always)]
554    pub fn is_en(&self) -> bool {
555        *self == OneMstMode::En
556    }
557}
558#[doc = "Field `ONE_MST_MODE` writer - SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low."]
559pub type OneMstModeW<'a, REG> = crate::BitWriter<'a, REG, OneMstMode>;
560impl<'a, REG> OneMstModeW<'a, REG>
561where
562    REG: crate::Writable + crate::RegisterSpec,
563{
564    #[doc = "Standard open-drain operation: drive low for 0, Hi-Z for 1"]
565    #[inline(always)]
566    pub fn dis(self) -> &'a mut crate::W<REG> {
567        self.variant(OneMstMode::Dis)
568    }
569    #[doc = "Non-standard push-pull operation: drive low for 0, drive high for 1"]
570    #[inline(always)]
571    pub fn en(self) -> &'a mut crate::W<REG> {
572        self.variant(OneMstMode::En)
573    }
574}
575#[doc = "Field `HS_EN` reader - High speed mode enable"]
576pub type HsEnR = crate::BitReader;
577#[doc = "Field `HS_EN` writer - High speed mode enable"]
578pub type HsEnW<'a, REG> = crate::BitWriter<'a, REG>;
579impl R {
580    #[doc = "Bit 0 - I2C Enable."]
581    #[inline(always)]
582    pub fn en(&self) -> EnR {
583        EnR::new((self.bits & 1) != 0)
584    }
585    #[doc = "Bit 1 - Master Mode Enable."]
586    #[inline(always)]
587    pub fn mst_mode(&self) -> MstModeR {
588        MstModeR::new(((self.bits >> 1) & 1) != 0)
589    }
590    #[doc = "Bit 2 - General Call Address Enable."]
591    #[inline(always)]
592    pub fn gc_addr_en(&self) -> GcAddrEnR {
593        GcAddrEnR::new(((self.bits >> 2) & 1) != 0)
594    }
595    #[doc = "Bit 3 - Interactive Receive Mode."]
596    #[inline(always)]
597    pub fn irxm_en(&self) -> IrxmEnR {
598        IrxmEnR::new(((self.bits >> 3) & 1) != 0)
599    }
600    #[doc = "Bit 4 - Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0."]
601    #[inline(always)]
602    pub fn irxm_ack(&self) -> IrxmAckR {
603        IrxmAckR::new(((self.bits >> 4) & 1) != 0)
604    }
605    #[doc = "Bit 6 - SCL Output. This bits control SCL output when SWOE =1."]
606    #[inline(always)]
607    pub fn scl_out(&self) -> SclOutR {
608        SclOutR::new(((self.bits >> 6) & 1) != 0)
609    }
610    #[doc = "Bit 7 - SDA Output. This bits control SDA output when SWOE = 1."]
611    #[inline(always)]
612    pub fn sda_out(&self) -> SdaOutR {
613        SdaOutR::new(((self.bits >> 7) & 1) != 0)
614    }
615    #[doc = "Bit 8 - SCL status. This bit reflects the logic gate of SCL signal."]
616    #[inline(always)]
617    pub fn scl(&self) -> SclR {
618        SclR::new(((self.bits >> 8) & 1) != 0)
619    }
620    #[doc = "Bit 9 - SDA status. THis bit reflects the logic gate of SDA signal."]
621    #[inline(always)]
622    pub fn sda(&self) -> SdaR {
623        SdaR::new(((self.bits >> 9) & 1) != 0)
624    }
625    #[doc = "Bit 10 - Software Output Enable."]
626    #[inline(always)]
627    pub fn bb_mode(&self) -> BbModeR {
628        BbModeR::new(((self.bits >> 10) & 1) != 0)
629    }
630    #[doc = "Bit 11 - Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set."]
631    #[inline(always)]
632    pub fn read(&self) -> ReadR {
633        ReadR::new(((self.bits >> 11) & 1) != 0)
634    }
635    #[doc = "Bit 12 - This bit will disable slave clock stretching when set."]
636    #[inline(always)]
637    pub fn clkstr_dis(&self) -> ClkstrDisR {
638        ClkstrDisR::new(((self.bits >> 12) & 1) != 0)
639    }
640    #[doc = "Bit 13 - SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low."]
641    #[inline(always)]
642    pub fn one_mst_mode(&self) -> OneMstModeR {
643        OneMstModeR::new(((self.bits >> 13) & 1) != 0)
644    }
645    #[doc = "Bit 15 - High speed mode enable"]
646    #[inline(always)]
647    pub fn hs_en(&self) -> HsEnR {
648        HsEnR::new(((self.bits >> 15) & 1) != 0)
649    }
650}
651impl W {
652    #[doc = "Bit 0 - I2C Enable."]
653    #[inline(always)]
654    pub fn en(&mut self) -> EnW<CtrlSpec> {
655        EnW::new(self, 0)
656    }
657    #[doc = "Bit 1 - Master Mode Enable."]
658    #[inline(always)]
659    pub fn mst_mode(&mut self) -> MstModeW<CtrlSpec> {
660        MstModeW::new(self, 1)
661    }
662    #[doc = "Bit 2 - General Call Address Enable."]
663    #[inline(always)]
664    pub fn gc_addr_en(&mut self) -> GcAddrEnW<CtrlSpec> {
665        GcAddrEnW::new(self, 2)
666    }
667    #[doc = "Bit 3 - Interactive Receive Mode."]
668    #[inline(always)]
669    pub fn irxm_en(&mut self) -> IrxmEnW<CtrlSpec> {
670        IrxmEnW::new(self, 3)
671    }
672    #[doc = "Bit 4 - Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0."]
673    #[inline(always)]
674    pub fn irxm_ack(&mut self) -> IrxmAckW<CtrlSpec> {
675        IrxmAckW::new(self, 4)
676    }
677    #[doc = "Bit 6 - SCL Output. This bits control SCL output when SWOE =1."]
678    #[inline(always)]
679    pub fn scl_out(&mut self) -> SclOutW<CtrlSpec> {
680        SclOutW::new(self, 6)
681    }
682    #[doc = "Bit 7 - SDA Output. This bits control SDA output when SWOE = 1."]
683    #[inline(always)]
684    pub fn sda_out(&mut self) -> SdaOutW<CtrlSpec> {
685        SdaOutW::new(self, 7)
686    }
687    #[doc = "Bit 10 - Software Output Enable."]
688    #[inline(always)]
689    pub fn bb_mode(&mut self) -> BbModeW<CtrlSpec> {
690        BbModeW::new(self, 10)
691    }
692    #[doc = "Bit 12 - This bit will disable slave clock stretching when set."]
693    #[inline(always)]
694    pub fn clkstr_dis(&mut self) -> ClkstrDisW<CtrlSpec> {
695        ClkstrDisW::new(self, 12)
696    }
697    #[doc = "Bit 13 - SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low."]
698    #[inline(always)]
699    pub fn one_mst_mode(&mut self) -> OneMstModeW<CtrlSpec> {
700        OneMstModeW::new(self, 13)
701    }
702    #[doc = "Bit 15 - High speed mode enable"]
703    #[inline(always)]
704    pub fn hs_en(&mut self) -> HsEnW<CtrlSpec> {
705        HsEnW::new(self, 15)
706    }
707}
708#[doc = "Control Register0.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
709pub struct CtrlSpec;
710impl crate::RegisterSpec for CtrlSpec {
711    type Ux = u32;
712}
713#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
714impl crate::Readable for CtrlSpec {}
715#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
716impl crate::Writable for CtrlSpec {
717    type Safety = crate::Unsafe;
718    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
719    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
720}
721#[doc = "`reset()` method sets CTRL to value 0"]
722impl crate::Resettable for CtrlSpec {
723    const RESET_VALUE: u32 = 0;
724}
max78000_pac/i2c0/ctrl.rs

max78000_pac/i2c0/
ctrl.rs
