max78000_pac/gcr/
clkctrl.rs

1#[doc = "Register `CLKCTRL` reader"]
2pub type R = crate::R<ClkctrlSpec>;
3#[doc = "Register `CLKCTRL` writer"]
4pub type W = crate::W<ClkctrlSpec>;
5#[doc = "Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum SysclkDiv {
9    #[doc = "0: Divide by 1."]
10    Div1 = 0,
11    #[doc = "1: Divide by 2."]
12    Div2 = 1,
13    #[doc = "2: Divide by 4."]
14    Div4 = 2,
15    #[doc = "3: Divide by 8."]
16    Div8 = 3,
17    #[doc = "4: Divide by 16."]
18    Div16 = 4,
19    #[doc = "5: Divide by 32."]
20    Div32 = 5,
21    #[doc = "6: Divide by 64."]
22    Div64 = 6,
23    #[doc = "7: Divide by 128."]
24    Div128 = 7,
25}
26impl From<SysclkDiv> for u8 {
27    #[inline(always)]
28    fn from(variant: SysclkDiv) -> Self {
29        variant as _
30    }
31}
32impl crate::FieldSpec for SysclkDiv {
33    type Ux = u8;
34}
35impl crate::IsEnum for SysclkDiv {}
36#[doc = "Field `SYSCLK_DIV` reader - Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0."]
37pub type SysclkDivR = crate::FieldReader<SysclkDiv>;
38impl SysclkDivR {
39    #[doc = "Get enumerated values variant"]
40    #[inline(always)]
41    pub const fn variant(&self) -> SysclkDiv {
42        match self.bits {
43            0 => SysclkDiv::Div1,
44            1 => SysclkDiv::Div2,
45            2 => SysclkDiv::Div4,
46            3 => SysclkDiv::Div8,
47            4 => SysclkDiv::Div16,
48            5 => SysclkDiv::Div32,
49            6 => SysclkDiv::Div64,
50            7 => SysclkDiv::Div128,
51            _ => unreachable!(),
52        }
53    }
54    #[doc = "Divide by 1."]
55    #[inline(always)]
56    pub fn is_div1(&self) -> bool {
57        *self == SysclkDiv::Div1
58    }
59    #[doc = "Divide by 2."]
60    #[inline(always)]
61    pub fn is_div2(&self) -> bool {
62        *self == SysclkDiv::Div2
63    }
64    #[doc = "Divide by 4."]
65    #[inline(always)]
66    pub fn is_div4(&self) -> bool {
67        *self == SysclkDiv::Div4
68    }
69    #[doc = "Divide by 8."]
70    #[inline(always)]
71    pub fn is_div8(&self) -> bool {
72        *self == SysclkDiv::Div8
73    }
74    #[doc = "Divide by 16."]
75    #[inline(always)]
76    pub fn is_div16(&self) -> bool {
77        *self == SysclkDiv::Div16
78    }
79    #[doc = "Divide by 32."]
80    #[inline(always)]
81    pub fn is_div32(&self) -> bool {
82        *self == SysclkDiv::Div32
83    }
84    #[doc = "Divide by 64."]
85    #[inline(always)]
86    pub fn is_div64(&self) -> bool {
87        *self == SysclkDiv::Div64
88    }
89    #[doc = "Divide by 128."]
90    #[inline(always)]
91    pub fn is_div128(&self) -> bool {
92        *self == SysclkDiv::Div128
93    }
94}
95#[doc = "Field `SYSCLK_DIV` writer - Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0."]
96pub type SysclkDivW<'a, REG> = crate::FieldWriter<'a, REG, 3, SysclkDiv, crate::Safe>;
97impl<'a, REG> SysclkDivW<'a, REG>
98where
99    REG: crate::Writable + crate::RegisterSpec,
100    REG::Ux: From<u8>,
101{
102    #[doc = "Divide by 1."]
103    #[inline(always)]
104    pub fn div1(self) -> &'a mut crate::W<REG> {
105        self.variant(SysclkDiv::Div1)
106    }
107    #[doc = "Divide by 2."]
108    #[inline(always)]
109    pub fn div2(self) -> &'a mut crate::W<REG> {
110        self.variant(SysclkDiv::Div2)
111    }
112    #[doc = "Divide by 4."]
113    #[inline(always)]
114    pub fn div4(self) -> &'a mut crate::W<REG> {
115        self.variant(SysclkDiv::Div4)
116    }
117    #[doc = "Divide by 8."]
118    #[inline(always)]
119    pub fn div8(self) -> &'a mut crate::W<REG> {
120        self.variant(SysclkDiv::Div8)
121    }
122    #[doc = "Divide by 16."]
123    #[inline(always)]
124    pub fn div16(self) -> &'a mut crate::W<REG> {
125        self.variant(SysclkDiv::Div16)
126    }
127    #[doc = "Divide by 32."]
128    #[inline(always)]
129    pub fn div32(self) -> &'a mut crate::W<REG> {
130        self.variant(SysclkDiv::Div32)
131    }
132    #[doc = "Divide by 64."]
133    #[inline(always)]
134    pub fn div64(self) -> &'a mut crate::W<REG> {
135        self.variant(SysclkDiv::Div64)
136    }
137    #[doc = "Divide by 128."]
138    #[inline(always)]
139    pub fn div128(self) -> &'a mut crate::W<REG> {
140        self.variant(SysclkDiv::Div128)
141    }
142}
143#[doc = "Clock Source Select. This 3 bit field selects the source for the system clock.\n\nValue on reset: 0"]
144#[derive(Clone, Copy, Debug, PartialEq, Eq)]
145#[repr(u8)]
146pub enum SysclkSel {
147    #[doc = "0: The internal 60 MHz oscillator is used for the system clock."]
148    Iso = 0,
149    #[doc = "3: 8 kHz LIRC is used for the system clock."]
150    Inro = 3,
151    #[doc = "4: The internal 100 MHz oscillator is used for the system clock."]
152    Ipo = 4,
153    #[doc = "5: The internal 7.3725 MHz oscillator is used for the system clock."]
154    Ibro = 5,
155    #[doc = "6: 32 kHz is used for the system clock."]
156    Ertco = 6,
157    #[doc = "7: External clock on GPIO0.30."]
158    Extclk = 7,
159}
160impl From<SysclkSel> for u8 {
161    #[inline(always)]
162    fn from(variant: SysclkSel) -> Self {
163        variant as _
164    }
165}
166impl crate::FieldSpec for SysclkSel {
167    type Ux = u8;
168}
169impl crate::IsEnum for SysclkSel {}
170#[doc = "Field `SYSCLK_SEL` reader - Clock Source Select. This 3 bit field selects the source for the system clock."]
171pub type SysclkSelR = crate::FieldReader<SysclkSel>;
172impl SysclkSelR {
173    #[doc = "Get enumerated values variant"]
174    #[inline(always)]
175    pub const fn variant(&self) -> Option<SysclkSel> {
176        match self.bits {
177            0 => Some(SysclkSel::Iso),
178            3 => Some(SysclkSel::Inro),
179            4 => Some(SysclkSel::Ipo),
180            5 => Some(SysclkSel::Ibro),
181            6 => Some(SysclkSel::Ertco),
182            7 => Some(SysclkSel::Extclk),
183            _ => None,
184        }
185    }
186    #[doc = "The internal 60 MHz oscillator is used for the system clock."]
187    #[inline(always)]
188    pub fn is_iso(&self) -> bool {
189        *self == SysclkSel::Iso
190    }
191    #[doc = "8 kHz LIRC is used for the system clock."]
192    #[inline(always)]
193    pub fn is_inro(&self) -> bool {
194        *self == SysclkSel::Inro
195    }
196    #[doc = "The internal 100 MHz oscillator is used for the system clock."]
197    #[inline(always)]
198    pub fn is_ipo(&self) -> bool {
199        *self == SysclkSel::Ipo
200    }
201    #[doc = "The internal 7.3725 MHz oscillator is used for the system clock."]
202    #[inline(always)]
203    pub fn is_ibro(&self) -> bool {
204        *self == SysclkSel::Ibro
205    }
206    #[doc = "32 kHz is used for the system clock."]
207    #[inline(always)]
208    pub fn is_ertco(&self) -> bool {
209        *self == SysclkSel::Ertco
210    }
211    #[doc = "External clock on GPIO0.30."]
212    #[inline(always)]
213    pub fn is_extclk(&self) -> bool {
214        *self == SysclkSel::Extclk
215    }
216}
217#[doc = "Field `SYSCLK_SEL` writer - Clock Source Select. This 3 bit field selects the source for the system clock."]
218pub type SysclkSelW<'a, REG> = crate::FieldWriter<'a, REG, 3, SysclkSel>;
219impl<'a, REG> SysclkSelW<'a, REG>
220where
221    REG: crate::Writable + crate::RegisterSpec,
222    REG::Ux: From<u8>,
223{
224    #[doc = "The internal 60 MHz oscillator is used for the system clock."]
225    #[inline(always)]
226    pub fn iso(self) -> &'a mut crate::W<REG> {
227        self.variant(SysclkSel::Iso)
228    }
229    #[doc = "8 kHz LIRC is used for the system clock."]
230    #[inline(always)]
231    pub fn inro(self) -> &'a mut crate::W<REG> {
232        self.variant(SysclkSel::Inro)
233    }
234    #[doc = "The internal 100 MHz oscillator is used for the system clock."]
235    #[inline(always)]
236    pub fn ipo(self) -> &'a mut crate::W<REG> {
237        self.variant(SysclkSel::Ipo)
238    }
239    #[doc = "The internal 7.3725 MHz oscillator is used for the system clock."]
240    #[inline(always)]
241    pub fn ibro(self) -> &'a mut crate::W<REG> {
242        self.variant(SysclkSel::Ibro)
243    }
244    #[doc = "32 kHz is used for the system clock."]
245    #[inline(always)]
246    pub fn ertco(self) -> &'a mut crate::W<REG> {
247        self.variant(SysclkSel::Ertco)
248    }
249    #[doc = "External clock on GPIO0.30."]
250    #[inline(always)]
251    pub fn extclk(self) -> &'a mut crate::W<REG> {
252        self.variant(SysclkSel::Extclk)
253    }
254}
255#[doc = "Clock Ready. This read only bit reflects whether the currently selected system clock source is running.\n\nValue on reset: 0"]
256#[derive(Clone, Copy, Debug, PartialEq, Eq)]
257pub enum SysclkRdy {
258    #[doc = "0: Switchover to the new clock source (as selected by CLKSEL) has not yet occurred."]
259    Busy = 0,
260    #[doc = "1: System clock running from CLKSEL clock source."]
261    Ready = 1,
262}
263impl From<SysclkRdy> for bool {
264    #[inline(always)]
265    fn from(variant: SysclkRdy) -> Self {
266        variant as u8 != 0
267    }
268}
269#[doc = "Field `SYSCLK_RDY` reader - Clock Ready. This read only bit reflects whether the currently selected system clock source is running."]
270pub type SysclkRdyR = crate::BitReader<SysclkRdy>;
271impl SysclkRdyR {
272    #[doc = "Get enumerated values variant"]
273    #[inline(always)]
274    pub const fn variant(&self) -> SysclkRdy {
275        match self.bits {
276            false => SysclkRdy::Busy,
277            true => SysclkRdy::Ready,
278        }
279    }
280    #[doc = "Switchover to the new clock source (as selected by CLKSEL) has not yet occurred."]
281    #[inline(always)]
282    pub fn is_busy(&self) -> bool {
283        *self == SysclkRdy::Busy
284    }
285    #[doc = "System clock running from CLKSEL clock source."]
286    #[inline(always)]
287    pub fn is_ready(&self) -> bool {
288        *self == SysclkRdy::Ready
289    }
290}
291#[doc = "32 kHz Crystal Oscillator Enable.\n\nValue on reset: 0"]
292#[derive(Clone, Copy, Debug, PartialEq, Eq)]
293pub enum ErtcoEn {
294    #[doc = "0: Is Disabled."]
295    Dis = 0,
296    #[doc = "1: Is Enabled."]
297    En = 1,
298}
299impl From<ErtcoEn> for bool {
300    #[inline(always)]
301    fn from(variant: ErtcoEn) -> Self {
302        variant as u8 != 0
303    }
304}
305#[doc = "Field `ERTCO_EN` reader - 32 kHz Crystal Oscillator Enable."]
306pub type ErtcoEnR = crate::BitReader<ErtcoEn>;
307impl ErtcoEnR {
308    #[doc = "Get enumerated values variant"]
309    #[inline(always)]
310    pub const fn variant(&self) -> ErtcoEn {
311        match self.bits {
312            false => ErtcoEn::Dis,
313            true => ErtcoEn::En,
314        }
315    }
316    #[doc = "Is Disabled."]
317    #[inline(always)]
318    pub fn is_dis(&self) -> bool {
319        *self == ErtcoEn::Dis
320    }
321    #[doc = "Is Enabled."]
322    #[inline(always)]
323    pub fn is_en(&self) -> bool {
324        *self == ErtcoEn::En
325    }
326}
327#[doc = "Field `ERTCO_EN` writer - 32 kHz Crystal Oscillator Enable."]
328pub type ErtcoEnW<'a, REG> = crate::BitWriter<'a, REG, ErtcoEn>;
329impl<'a, REG> ErtcoEnW<'a, REG>
330where
331    REG: crate::Writable + crate::RegisterSpec,
332{
333    #[doc = "Is Disabled."]
334    #[inline(always)]
335    pub fn dis(self) -> &'a mut crate::W<REG> {
336        self.variant(ErtcoEn::Dis)
337    }
338    #[doc = "Is Enabled."]
339    #[inline(always)]
340    pub fn en(self) -> &'a mut crate::W<REG> {
341        self.variant(ErtcoEn::En)
342    }
343}
344#[doc = "60 MHz High Frequency Internal Reference Clock Enable."]
345pub use ErtcoEn as IsoEn;
346#[doc = "100 MHz High Frequency Internal Reference Clock Enable."]
347pub use ErtcoEn as IpoEn;
348#[doc = "7.3725 MHz High Frequency Internal Reference Clock Enable."]
349pub use ErtcoEn as IbroEn;
350#[doc = "Field `ISO_EN` reader - 60 MHz High Frequency Internal Reference Clock Enable."]
351pub use ErtcoEnR as IsoEnR;
352#[doc = "Field `IPO_EN` reader - 100 MHz High Frequency Internal Reference Clock Enable."]
353pub use ErtcoEnR as IpoEnR;
354#[doc = "Field `IBRO_EN` reader - 7.3725 MHz High Frequency Internal Reference Clock Enable."]
355pub use ErtcoEnR as IbroEnR;
356#[doc = "Field `ISO_EN` writer - 60 MHz High Frequency Internal Reference Clock Enable."]
357pub use ErtcoEnW as IsoEnW;
358#[doc = "Field `IPO_EN` writer - 100 MHz High Frequency Internal Reference Clock Enable."]
359pub use ErtcoEnW as IpoEnW;
360#[doc = "Field `IBRO_EN` writer - 7.3725 MHz High Frequency Internal Reference Clock Enable."]
361pub use ErtcoEnW as IbroEnW;
362#[doc = "7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO.\n\nValue on reset: 0"]
363#[derive(Clone, Copy, Debug, PartialEq, Eq)]
364pub enum IbroVs {
365    #[doc = "0: VCore Supply"]
366    Vcor = 0,
367    #[doc = "1: Dedicated 1V regulated supply."]
368    _1v = 1,
369}
370impl From<IbroVs> for bool {
371    #[inline(always)]
372    fn from(variant: IbroVs) -> Self {
373        variant as u8 != 0
374    }
375}
376#[doc = "Field `IBRO_VS` reader - 7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO."]
377pub type IbroVsR = crate::BitReader<IbroVs>;
378impl IbroVsR {
379    #[doc = "Get enumerated values variant"]
380    #[inline(always)]
381    pub const fn variant(&self) -> IbroVs {
382        match self.bits {
383            false => IbroVs::Vcor,
384            true => IbroVs::_1v,
385        }
386    }
387    #[doc = "VCore Supply"]
388    #[inline(always)]
389    pub fn is_vcor(&self) -> bool {
390        *self == IbroVs::Vcor
391    }
392    #[doc = "Dedicated 1V regulated supply."]
393    #[inline(always)]
394    pub fn is_1v(&self) -> bool {
395        *self == IbroVs::_1v
396    }
397}
398#[doc = "Field `IBRO_VS` writer - 7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO."]
399pub type IbroVsW<'a, REG> = crate::BitWriter<'a, REG, IbroVs>;
400impl<'a, REG> IbroVsW<'a, REG>
401where
402    REG: crate::Writable + crate::RegisterSpec,
403{
404    #[doc = "VCore Supply"]
405    #[inline(always)]
406    pub fn vcor(self) -> &'a mut crate::W<REG> {
407        self.variant(IbroVs::Vcor)
408    }
409    #[doc = "Dedicated 1V regulated supply."]
410    #[inline(always)]
411    pub fn _1v(self) -> &'a mut crate::W<REG> {
412        self.variant(IbroVs::_1v)
413    }
414}
415#[doc = "32 kHz Crystal Oscillator Ready\n\nValue on reset: 0"]
416#[derive(Clone, Copy, Debug, PartialEq, Eq)]
417pub enum ErtcoRdy {
418    #[doc = "0: Is not Ready."]
419    Not = 0,
420    #[doc = "1: Is Ready."]
421    Ready = 1,
422}
423impl From<ErtcoRdy> for bool {
424    #[inline(always)]
425    fn from(variant: ErtcoRdy) -> Self {
426        variant as u8 != 0
427    }
428}
429#[doc = "Field `ERTCO_RDY` reader - 32 kHz Crystal Oscillator Ready"]
430pub type ErtcoRdyR = crate::BitReader<ErtcoRdy>;
431impl ErtcoRdyR {
432    #[doc = "Get enumerated values variant"]
433    #[inline(always)]
434    pub const fn variant(&self) -> ErtcoRdy {
435        match self.bits {
436            false => ErtcoRdy::Not,
437            true => ErtcoRdy::Ready,
438        }
439    }
440    #[doc = "Is not Ready."]
441    #[inline(always)]
442    pub fn is_not(&self) -> bool {
443        *self == ErtcoRdy::Not
444    }
445    #[doc = "Is Ready."]
446    #[inline(always)]
447    pub fn is_ready(&self) -> bool {
448        *self == ErtcoRdy::Ready
449    }
450}
451#[doc = "60 MHz HIRC Ready."]
452pub use ErtcoRdy as IsoRdy;
453#[doc = "100 MHz HIRC Ready."]
454pub use ErtcoRdy as IpoRdy;
455#[doc = "7.3725 MHz HIRC Ready."]
456pub use ErtcoRdy as IbroRdy;
457#[doc = "8 kHz Low Frequency Reference Clock Ready."]
458pub use ErtcoRdy as InroRdy;
459#[doc = "Field `ISO_RDY` reader - 60 MHz HIRC Ready."]
460pub use ErtcoRdyR as IsoRdyR;
461#[doc = "Field `IPO_RDY` reader - 100 MHz HIRC Ready."]
462pub use ErtcoRdyR as IpoRdyR;
463#[doc = "Field `IBRO_RDY` reader - 7.3725 MHz HIRC Ready."]
464pub use ErtcoRdyR as IbroRdyR;
465#[doc = "Field `INRO_RDY` reader - 8 kHz Low Frequency Reference Clock Ready."]
466pub use ErtcoRdyR as InroRdyR;
467impl R {
468    #[doc = "Bits 6:8 - Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0."]
469    #[inline(always)]
470    pub fn sysclk_div(&self) -> SysclkDivR {
471        SysclkDivR::new(((self.bits >> 6) & 7) as u8)
472    }
473    #[doc = "Bits 9:11 - Clock Source Select. This 3 bit field selects the source for the system clock."]
474    #[inline(always)]
475    pub fn sysclk_sel(&self) -> SysclkSelR {
476        SysclkSelR::new(((self.bits >> 9) & 7) as u8)
477    }
478    #[doc = "Bit 13 - Clock Ready. This read only bit reflects whether the currently selected system clock source is running."]
479    #[inline(always)]
480    pub fn sysclk_rdy(&self) -> SysclkRdyR {
481        SysclkRdyR::new(((self.bits >> 13) & 1) != 0)
482    }
483    #[doc = "Bit 17 - 32 kHz Crystal Oscillator Enable."]
484    #[inline(always)]
485    pub fn ertco_en(&self) -> ErtcoEnR {
486        ErtcoEnR::new(((self.bits >> 17) & 1) != 0)
487    }
488    #[doc = "Bit 18 - 60 MHz High Frequency Internal Reference Clock Enable."]
489    #[inline(always)]
490    pub fn iso_en(&self) -> IsoEnR {
491        IsoEnR::new(((self.bits >> 18) & 1) != 0)
492    }
493    #[doc = "Bit 19 - 100 MHz High Frequency Internal Reference Clock Enable."]
494    #[inline(always)]
495    pub fn ipo_en(&self) -> IpoEnR {
496        IpoEnR::new(((self.bits >> 19) & 1) != 0)
497    }
498    #[doc = "Bit 20 - 7.3725 MHz High Frequency Internal Reference Clock Enable."]
499    #[inline(always)]
500    pub fn ibro_en(&self) -> IbroEnR {
501        IbroEnR::new(((self.bits >> 20) & 1) != 0)
502    }
503    #[doc = "Bit 21 - 7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO."]
504    #[inline(always)]
505    pub fn ibro_vs(&self) -> IbroVsR {
506        IbroVsR::new(((self.bits >> 21) & 1) != 0)
507    }
508    #[doc = "Bit 25 - 32 kHz Crystal Oscillator Ready"]
509    #[inline(always)]
510    pub fn ertco_rdy(&self) -> ErtcoRdyR {
511        ErtcoRdyR::new(((self.bits >> 25) & 1) != 0)
512    }
513    #[doc = "Bit 26 - 60 MHz HIRC Ready."]
514    #[inline(always)]
515    pub fn iso_rdy(&self) -> IsoRdyR {
516        IsoRdyR::new(((self.bits >> 26) & 1) != 0)
517    }
518    #[doc = "Bit 27 - 100 MHz HIRC Ready."]
519    #[inline(always)]
520    pub fn ipo_rdy(&self) -> IpoRdyR {
521        IpoRdyR::new(((self.bits >> 27) & 1) != 0)
522    }
523    #[doc = "Bit 28 - 7.3725 MHz HIRC Ready."]
524    #[inline(always)]
525    pub fn ibro_rdy(&self) -> IbroRdyR {
526        IbroRdyR::new(((self.bits >> 28) & 1) != 0)
527    }
528    #[doc = "Bit 29 - 8 kHz Low Frequency Reference Clock Ready."]
529    #[inline(always)]
530    pub fn inro_rdy(&self) -> InroRdyR {
531        InroRdyR::new(((self.bits >> 29) & 1) != 0)
532    }
533}
534impl W {
535    #[doc = "Bits 6:8 - Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0."]
536    #[inline(always)]
537    pub fn sysclk_div(&mut self) -> SysclkDivW<ClkctrlSpec> {
538        SysclkDivW::new(self, 6)
539    }
540    #[doc = "Bits 9:11 - Clock Source Select. This 3 bit field selects the source for the system clock."]
541    #[inline(always)]
542    pub fn sysclk_sel(&mut self) -> SysclkSelW<ClkctrlSpec> {
543        SysclkSelW::new(self, 9)
544    }
545    #[doc = "Bit 17 - 32 kHz Crystal Oscillator Enable."]
546    #[inline(always)]
547    pub fn ertco_en(&mut self) -> ErtcoEnW<ClkctrlSpec> {
548        ErtcoEnW::new(self, 17)
549    }
550    #[doc = "Bit 18 - 60 MHz High Frequency Internal Reference Clock Enable."]
551    #[inline(always)]
552    pub fn iso_en(&mut self) -> IsoEnW<ClkctrlSpec> {
553        IsoEnW::new(self, 18)
554    }
555    #[doc = "Bit 19 - 100 MHz High Frequency Internal Reference Clock Enable."]
556    #[inline(always)]
557    pub fn ipo_en(&mut self) -> IpoEnW<ClkctrlSpec> {
558        IpoEnW::new(self, 19)
559    }
560    #[doc = "Bit 20 - 7.3725 MHz High Frequency Internal Reference Clock Enable."]
561    #[inline(always)]
562    pub fn ibro_en(&mut self) -> IbroEnW<ClkctrlSpec> {
563        IbroEnW::new(self, 20)
564    }
565    #[doc = "Bit 21 - 7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO."]
566    #[inline(always)]
567    pub fn ibro_vs(&mut self) -> IbroVsW<ClkctrlSpec> {
568        IbroVsW::new(self, 21)
569    }
570}
571#[doc = "Clock Control.\n\nYou can [`read`](crate::Reg::read) this register and get [`clkctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`clkctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
572pub struct ClkctrlSpec;
573impl crate::RegisterSpec for ClkctrlSpec {
574    type Ux = u32;
575}
576#[doc = "`read()` method returns [`clkctrl::R`](R) reader structure"]
577impl crate::Readable for ClkctrlSpec {}
578#[doc = "`write(|w| ..)` method takes [`clkctrl::W`](W) writer structure"]
579impl crate::Writable for ClkctrlSpec {
580    type Safety = crate::Unsafe;
581    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
582    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
583}
584#[doc = "`reset()` method sets CLKCTRL to value 0x08"]
585impl crate::Resettable for ClkctrlSpec {
586    const RESET_VALUE: u32 = 0x08;
587}
max78000_pac/gcr/clkctrl.rs

max78000_pac/gcr/
clkctrl.rs
