max78000_pac/dma/ch/
src.rs

1#[doc = "Register `SRC` reader"]
2pub type R = crate::R<SrcSpec>;
3#[doc = "Register `SRC` writer"]
4pub type W = crate::W<SrcSpec>;
5#[doc = "Field `ADDR` reader - "]
6pub type AddrR = crate::FieldReader<u32>;
7#[doc = "Field `ADDR` writer - "]
8pub type AddrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10    #[doc = "Bits 0:31"]
11    #[inline(always)]
12    pub fn addr(&self) -> AddrR {
13        AddrR::new(self.bits)
14    }
15}
16impl W {
17    #[doc = "Bits 0:31"]
18    #[inline(always)]
19    pub fn addr(&mut self) -> AddrW<SrcSpec> {
20        AddrW::new(self, 0)
21    }
22}
23#[doc = "Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.\n\nYou can [`read`](crate::Reg::read) this register and get [`src::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`src::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
24pub struct SrcSpec;
25impl crate::RegisterSpec for SrcSpec {
26    type Ux = u32;
27}
28#[doc = "`read()` method returns [`src::R`](R) reader structure"]
29impl crate::Readable for SrcSpec {}
30#[doc = "`write(|w| ..)` method takes [`src::W`](W) writer structure"]
31impl crate::Writable for SrcSpec {
32    type Safety = crate::Unsafe;
33    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
34    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
35}
36#[doc = "`reset()` method sets SRC to value 0"]
37impl crate::Resettable for SrcSpec {
38    const RESET_VALUE: u32 = 0;
39}
max78000_pac/dma/ch/src.rs

max78000_pac/dma/ch/
src.rs
