max78000_pac/cameraif/
ctrl.rs

1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Read Mode.\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7#[repr(u8)]
8pub enum ReadMode {
9    #[doc = "0: Camera Interface Disabled."]
10    Dis = 0,
11    #[doc = "1: Single Image Capture."]
12    SingleImg = 1,
13    #[doc = "2: Continuous Image Capture."]
14    Continuous = 2,
15}
16impl From<ReadMode> for u8 {
17    #[inline(always)]
18    fn from(variant: ReadMode) -> Self {
19        variant as _
20    }
21}
22impl crate::FieldSpec for ReadMode {
23    type Ux = u8;
24}
25impl crate::IsEnum for ReadMode {}
26#[doc = "Field `READ_MODE` reader - Read Mode."]
27pub type ReadModeR = crate::FieldReader<ReadMode>;
28impl ReadModeR {
29    #[doc = "Get enumerated values variant"]
30    #[inline(always)]
31    pub const fn variant(&self) -> Option<ReadMode> {
32        match self.bits {
33            0 => Some(ReadMode::Dis),
34            1 => Some(ReadMode::SingleImg),
35            2 => Some(ReadMode::Continuous),
36            _ => None,
37        }
38    }
39    #[doc = "Camera Interface Disabled."]
40    #[inline(always)]
41    pub fn is_dis(&self) -> bool {
42        *self == ReadMode::Dis
43    }
44    #[doc = "Single Image Capture."]
45    #[inline(always)]
46    pub fn is_single_img(&self) -> bool {
47        *self == ReadMode::SingleImg
48    }
49    #[doc = "Continuous Image Capture."]
50    #[inline(always)]
51    pub fn is_continuous(&self) -> bool {
52        *self == ReadMode::Continuous
53    }
54}
55#[doc = "Field `READ_MODE` writer - Read Mode."]
56pub type ReadModeW<'a, REG> = crate::FieldWriter<'a, REG, 2, ReadMode>;
57impl<'a, REG> ReadModeW<'a, REG>
58where
59    REG: crate::Writable + crate::RegisterSpec,
60    REG::Ux: From<u8>,
61{
62    #[doc = "Camera Interface Disabled."]
63    #[inline(always)]
64    pub fn dis(self) -> &'a mut crate::W<REG> {
65        self.variant(ReadMode::Dis)
66    }
67    #[doc = "Single Image Capture."]
68    #[inline(always)]
69    pub fn single_img(self) -> &'a mut crate::W<REG> {
70        self.variant(ReadMode::SingleImg)
71    }
72    #[doc = "Continuous Image Capture."]
73    #[inline(always)]
74    pub fn continuous(self) -> &'a mut crate::W<REG> {
75        self.variant(ReadMode::Continuous)
76    }
77}
78#[doc = "Data Width.\n\nValue on reset: 0"]
79#[derive(Clone, Copy, Debug, PartialEq, Eq)]
80#[repr(u8)]
81pub enum DataWidth {
82    #[doc = "0: 8 bit."]
83    _8bit = 0,
84    #[doc = "1: 10 bit."]
85    _10bit = 1,
86    #[doc = "2: 12 bit."]
87    _12bit = 2,
88}
89impl From<DataWidth> for u8 {
90    #[inline(always)]
91    fn from(variant: DataWidth) -> Self {
92        variant as _
93    }
94}
95impl crate::FieldSpec for DataWidth {
96    type Ux = u8;
97}
98impl crate::IsEnum for DataWidth {}
99#[doc = "Field `DATA_WIDTH` reader - Data Width."]
100pub type DataWidthR = crate::FieldReader<DataWidth>;
101impl DataWidthR {
102    #[doc = "Get enumerated values variant"]
103    #[inline(always)]
104    pub const fn variant(&self) -> Option<DataWidth> {
105        match self.bits {
106            0 => Some(DataWidth::_8bit),
107            1 => Some(DataWidth::_10bit),
108            2 => Some(DataWidth::_12bit),
109            _ => None,
110        }
111    }
112    #[doc = "8 bit."]
113    #[inline(always)]
114    pub fn is_8bit(&self) -> bool {
115        *self == DataWidth::_8bit
116    }
117    #[doc = "10 bit."]
118    #[inline(always)]
119    pub fn is_10bit(&self) -> bool {
120        *self == DataWidth::_10bit
121    }
122    #[doc = "12 bit."]
123    #[inline(always)]
124    pub fn is_12bit(&self) -> bool {
125        *self == DataWidth::_12bit
126    }
127}
128#[doc = "Field `DATA_WIDTH` writer - Data Width."]
129pub type DataWidthW<'a, REG> = crate::FieldWriter<'a, REG, 2, DataWidth>;
130impl<'a, REG> DataWidthW<'a, REG>
131where
132    REG: crate::Writable + crate::RegisterSpec,
133    REG::Ux: From<u8>,
134{
135    #[doc = "8 bit."]
136    #[inline(always)]
137    pub fn _8bit(self) -> &'a mut crate::W<REG> {
138        self.variant(DataWidth::_8bit)
139    }
140    #[doc = "10 bit."]
141    #[inline(always)]
142    pub fn _10bit(self) -> &'a mut crate::W<REG> {
143        self.variant(DataWidth::_10bit)
144    }
145    #[doc = "12 bit."]
146    #[inline(always)]
147    pub fn _12bit(self) -> &'a mut crate::W<REG> {
148        self.variant(DataWidth::_12bit)
149    }
150}
151#[doc = "DS Timing Enable.\n\nValue on reset: 0"]
152#[derive(Clone, Copy, Debug, PartialEq, Eq)]
153pub enum DsTimingEn {
154    #[doc = "0: Timing from VSYNC and HSYNC."]
155    Dis = 0,
156    #[doc = "1: Timing embedded in data using SAV and EAV codes."]
157    En = 1,
158}
159impl From<DsTimingEn> for bool {
160    #[inline(always)]
161    fn from(variant: DsTimingEn) -> Self {
162        variant as u8 != 0
163    }
164}
165#[doc = "Field `DS_TIMING_EN` reader - DS Timing Enable."]
166pub type DsTimingEnR = crate::BitReader<DsTimingEn>;
167impl DsTimingEnR {
168    #[doc = "Get enumerated values variant"]
169    #[inline(always)]
170    pub const fn variant(&self) -> DsTimingEn {
171        match self.bits {
172            false => DsTimingEn::Dis,
173            true => DsTimingEn::En,
174        }
175    }
176    #[doc = "Timing from VSYNC and HSYNC."]
177    #[inline(always)]
178    pub fn is_dis(&self) -> bool {
179        *self == DsTimingEn::Dis
180    }
181    #[doc = "Timing embedded in data using SAV and EAV codes."]
182    #[inline(always)]
183    pub fn is_en(&self) -> bool {
184        *self == DsTimingEn::En
185    }
186}
187#[doc = "Field `DS_TIMING_EN` writer - DS Timing Enable."]
188pub type DsTimingEnW<'a, REG> = crate::BitWriter<'a, REG, DsTimingEn>;
189impl<'a, REG> DsTimingEnW<'a, REG>
190where
191    REG: crate::Writable + crate::RegisterSpec,
192{
193    #[doc = "Timing from VSYNC and HSYNC."]
194    #[inline(always)]
195    pub fn dis(self) -> &'a mut crate::W<REG> {
196        self.variant(DsTimingEn::Dis)
197    }
198    #[doc = "Timing embedded in data using SAV and EAV codes."]
199    #[inline(always)]
200    pub fn en(self) -> &'a mut crate::W<REG> {
201        self.variant(DsTimingEn::En)
202    }
203}
204#[doc = "Field `FIFO_THRSH` reader - Data FIFO Threshold."]
205pub type FifoThrshR = crate::FieldReader;
206#[doc = "Field `FIFO_THRSH` writer - Data FIFO Threshold."]
207pub type FifoThrshW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
208#[doc = "DMA Enable.\n\nValue on reset: 0"]
209#[derive(Clone, Copy, Debug, PartialEq, Eq)]
210pub enum RxDma {
211    #[doc = "0: DMA disabled."]
212    Dis = 0,
213    #[doc = "1: DMA enabled."]
214    En = 1,
215}
216impl From<RxDma> for bool {
217    #[inline(always)]
218    fn from(variant: RxDma) -> Self {
219        variant as u8 != 0
220    }
221}
222#[doc = "Field `RX_DMA` reader - DMA Enable."]
223pub type RxDmaR = crate::BitReader<RxDma>;
224impl RxDmaR {
225    #[doc = "Get enumerated values variant"]
226    #[inline(always)]
227    pub const fn variant(&self) -> RxDma {
228        match self.bits {
229            false => RxDma::Dis,
230            true => RxDma::En,
231        }
232    }
233    #[doc = "DMA disabled."]
234    #[inline(always)]
235    pub fn is_dis(&self) -> bool {
236        *self == RxDma::Dis
237    }
238    #[doc = "DMA enabled."]
239    #[inline(always)]
240    pub fn is_en(&self) -> bool {
241        *self == RxDma::En
242    }
243}
244#[doc = "Field `RX_DMA` writer - DMA Enable."]
245pub type RxDmaW<'a, REG> = crate::BitWriter<'a, REG, RxDma>;
246impl<'a, REG> RxDmaW<'a, REG>
247where
248    REG: crate::Writable + crate::RegisterSpec,
249{
250    #[doc = "DMA disabled."]
251    #[inline(always)]
252    pub fn dis(self) -> &'a mut crate::W<REG> {
253        self.variant(RxDma::Dis)
254    }
255    #[doc = "DMA enabled."]
256    #[inline(always)]
257    pub fn en(self) -> &'a mut crate::W<REG> {
258        self.variant(RxDma::En)
259    }
260}
261#[doc = "Field `RX_DMA_THRSH` reader - DMA Threshold."]
262pub type RxDmaThrshR = crate::FieldReader;
263#[doc = "Field `RX_DMA_THRSH` writer - DMA Threshold."]
264pub type RxDmaThrshW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
265#[doc = "Field `THREE_CH_EN` reader - Three-channel mode enable."]
266pub type ThreeChEnR = crate::BitReader;
267#[doc = "Field `THREE_CH_EN` writer - Three-channel mode enable."]
268pub type ThreeChEnW<'a, REG> = crate::BitWriter<'a, REG>;
269#[doc = "PCIF Control.\n\nValue on reset: 0"]
270#[derive(Clone, Copy, Debug, PartialEq, Eq)]
271pub enum PcifSys {
272    #[doc = "0: PCIF disabled."]
273    Dis = 0,
274    #[doc = "1: PCIF enabled."]
275    En = 1,
276}
277impl From<PcifSys> for bool {
278    #[inline(always)]
279    fn from(variant: PcifSys) -> Self {
280        variant as u8 != 0
281    }
282}
283#[doc = "Field `PCIF_SYS` reader - PCIF Control."]
284pub type PcifSysR = crate::BitReader<PcifSys>;
285impl PcifSysR {
286    #[doc = "Get enumerated values variant"]
287    #[inline(always)]
288    pub const fn variant(&self) -> PcifSys {
289        match self.bits {
290            false => PcifSys::Dis,
291            true => PcifSys::En,
292        }
293    }
294    #[doc = "PCIF disabled."]
295    #[inline(always)]
296    pub fn is_dis(&self) -> bool {
297        *self == PcifSys::Dis
298    }
299    #[doc = "PCIF enabled."]
300    #[inline(always)]
301    pub fn is_en(&self) -> bool {
302        *self == PcifSys::En
303    }
304}
305#[doc = "Field `PCIF_SYS` writer - PCIF Control."]
306pub type PcifSysW<'a, REG> = crate::BitWriter<'a, REG, PcifSys>;
307impl<'a, REG> PcifSysW<'a, REG>
308where
309    REG: crate::Writable + crate::RegisterSpec,
310{
311    #[doc = "PCIF disabled."]
312    #[inline(always)]
313    pub fn dis(self) -> &'a mut crate::W<REG> {
314        self.variant(PcifSys::Dis)
315    }
316    #[doc = "PCIF enabled."]
317    #[inline(always)]
318    pub fn en(self) -> &'a mut crate::W<REG> {
319        self.variant(PcifSys::En)
320    }
321}
322impl R {
323    #[doc = "Bits 0:1 - Read Mode."]
324    #[inline(always)]
325    pub fn read_mode(&self) -> ReadModeR {
326        ReadModeR::new((self.bits & 3) as u8)
327    }
328    #[doc = "Bits 2:3 - Data Width."]
329    #[inline(always)]
330    pub fn data_width(&self) -> DataWidthR {
331        DataWidthR::new(((self.bits >> 2) & 3) as u8)
332    }
333    #[doc = "Bit 4 - DS Timing Enable."]
334    #[inline(always)]
335    pub fn ds_timing_en(&self) -> DsTimingEnR {
336        DsTimingEnR::new(((self.bits >> 4) & 1) != 0)
337    }
338    #[doc = "Bits 5:9 - Data FIFO Threshold."]
339    #[inline(always)]
340    pub fn fifo_thrsh(&self) -> FifoThrshR {
341        FifoThrshR::new(((self.bits >> 5) & 0x1f) as u8)
342    }
343    #[doc = "Bit 16 - DMA Enable."]
344    #[inline(always)]
345    pub fn rx_dma(&self) -> RxDmaR {
346        RxDmaR::new(((self.bits >> 16) & 1) != 0)
347    }
348    #[doc = "Bits 17:20 - DMA Threshold."]
349    #[inline(always)]
350    pub fn rx_dma_thrsh(&self) -> RxDmaThrshR {
351        RxDmaThrshR::new(((self.bits >> 17) & 0x0f) as u8)
352    }
353    #[doc = "Bit 30 - Three-channel mode enable."]
354    #[inline(always)]
355    pub fn three_ch_en(&self) -> ThreeChEnR {
356        ThreeChEnR::new(((self.bits >> 30) & 1) != 0)
357    }
358    #[doc = "Bit 31 - PCIF Control."]
359    #[inline(always)]
360    pub fn pcif_sys(&self) -> PcifSysR {
361        PcifSysR::new(((self.bits >> 31) & 1) != 0)
362    }
363}
364impl W {
365    #[doc = "Bits 0:1 - Read Mode."]
366    #[inline(always)]
367    pub fn read_mode(&mut self) -> ReadModeW<CtrlSpec> {
368        ReadModeW::new(self, 0)
369    }
370    #[doc = "Bits 2:3 - Data Width."]
371    #[inline(always)]
372    pub fn data_width(&mut self) -> DataWidthW<CtrlSpec> {
373        DataWidthW::new(self, 2)
374    }
375    #[doc = "Bit 4 - DS Timing Enable."]
376    #[inline(always)]
377    pub fn ds_timing_en(&mut self) -> DsTimingEnW<CtrlSpec> {
378        DsTimingEnW::new(self, 4)
379    }
380    #[doc = "Bits 5:9 - Data FIFO Threshold."]
381    #[inline(always)]
382    pub fn fifo_thrsh(&mut self) -> FifoThrshW<CtrlSpec> {
383        FifoThrshW::new(self, 5)
384    }
385    #[doc = "Bit 16 - DMA Enable."]
386    #[inline(always)]
387    pub fn rx_dma(&mut self) -> RxDmaW<CtrlSpec> {
388        RxDmaW::new(self, 16)
389    }
390    #[doc = "Bits 17:20 - DMA Threshold."]
391    #[inline(always)]
392    pub fn rx_dma_thrsh(&mut self) -> RxDmaThrshW<CtrlSpec> {
393        RxDmaThrshW::new(self, 17)
394    }
395    #[doc = "Bit 30 - Three-channel mode enable."]
396    #[inline(always)]
397    pub fn three_ch_en(&mut self) -> ThreeChEnW<CtrlSpec> {
398        ThreeChEnW::new(self, 30)
399    }
400    #[doc = "Bit 31 - PCIF Control."]
401    #[inline(always)]
402    pub fn pcif_sys(&mut self) -> PcifSysW<CtrlSpec> {
403        PcifSysW::new(self, 31)
404    }
405}
406#[doc = "Control Register.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
407pub struct CtrlSpec;
408impl crate::RegisterSpec for CtrlSpec {
409    type Ux = u32;
410}
411#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
412impl crate::Readable for CtrlSpec {}
413#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
414impl crate::Writable for CtrlSpec {
415    type Safety = crate::Unsafe;
416    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
417    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
418}
419#[doc = "`reset()` method sets CTRL to value 0"]
420impl crate::Resettable for CtrlSpec {
421    const RESET_VALUE: u32 = 0;
422}
max78000_pac/cameraif/ctrl.rs

max78000_pac/cameraif/
ctrl.rs
