1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CtrlSpec>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CtrlSpec>;
5#[doc = "Field `start` reader - Start ADC Conversion"]
6pub type StartR = crate::BitReader;
7#[doc = "Field `start` writer - Start ADC Conversion"]
8pub type StartW<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `pwr` reader - ADC Power Up"]
10pub type PwrR = crate::BitReader;
11#[doc = "Field `pwr` writer - ADC Power Up"]
12pub type PwrW<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `refbuf_pwr` reader - ADC Reference Buffer Power Up"]
14pub type RefbufPwrR = crate::BitReader;
15#[doc = "Field `refbuf_pwr` writer - ADC Reference Buffer Power Up"]
16pub type RefbufPwrW<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `ref_sel` reader - ADC Reference Select"]
18pub type RefSelR = crate::BitReader;
19#[doc = "Field `ref_sel` writer - ADC Reference Select"]
20pub type RefSelW<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `ref_scale` reader - ADC Reference Scale"]
22pub type RefScaleR = crate::BitReader;
23#[doc = "Field `ref_scale` writer - ADC Reference Scale"]
24pub type RefScaleW<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `scale` reader - ADC Scale"]
26pub type ScaleR = crate::BitReader;
27#[doc = "Field `scale` writer - ADC Scale"]
28pub type ScaleW<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `clk_en` reader - ADC Clock Enable"]
30pub type ClkEnR = crate::BitReader;
31#[doc = "Field `clk_en` writer - ADC Clock Enable"]
32pub type ClkEnW<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "ADC Channel Select\n\nValue on reset: 0"]
34#[derive(Clone, Copy, Debug, PartialEq, Eq)]
35#[repr(u8)]
36pub enum ChSel {
37 #[doc = "0: `0`"]
38 Ain0 = 0,
39 #[doc = "1: `1`"]
40 Ain1 = 1,
41 #[doc = "2: `10`"]
42 Ain2 = 2,
43 #[doc = "3: `11`"]
44 Ain3 = 3,
45 #[doc = "4: `100`"]
46 Ain4 = 4,
47 #[doc = "5: `101`"]
48 Ain5 = 5,
49 #[doc = "6: `110`"]
50 Ain6 = 6,
51 #[doc = "7: `111`"]
52 Ain7 = 7,
53 #[doc = "8: `1000`"]
54 VcoreA = 8,
55 #[doc = "9: `1001`"]
56 VcoreB = 9,
57 #[doc = "10: `1010`"]
58 Vrxout = 10,
59 #[doc = "11: `1011`"]
60 Vtxout = 11,
61 #[doc = "12: `1100`"]
62 VddA = 12,
63 #[doc = "13: VddB/4"]
64 VddB = 13,
65 #[doc = "14: Vddio/4"]
66 Vddio = 14,
67 #[doc = "15: Vddioh/4"]
68 Vddioh = 15,
69 #[doc = "16: VregI/4"]
70 VregI = 16,
71}
72impl From<ChSel> for u8 {
73 #[inline(always)]
74 fn from(variant: ChSel) -> Self {
75 variant as _
76 }
77}
78impl crate::FieldSpec for ChSel {
79 type Ux = u8;
80}
81impl crate::IsEnum for ChSel {}
82#[doc = "Field `ch_sel` reader - ADC Channel Select"]
83pub type ChSelR = crate::FieldReader<ChSel>;
84impl ChSelR {
85 #[doc = "Get enumerated values variant"]
86 #[inline(always)]
87 pub const fn variant(&self) -> Option<ChSel> {
88 match self.bits {
89 0 => Some(ChSel::Ain0),
90 1 => Some(ChSel::Ain1),
91 2 => Some(ChSel::Ain2),
92 3 => Some(ChSel::Ain3),
93 4 => Some(ChSel::Ain4),
94 5 => Some(ChSel::Ain5),
95 6 => Some(ChSel::Ain6),
96 7 => Some(ChSel::Ain7),
97 8 => Some(ChSel::VcoreA),
98 9 => Some(ChSel::VcoreB),
99 10 => Some(ChSel::Vrxout),
100 11 => Some(ChSel::Vtxout),
101 12 => Some(ChSel::VddA),
102 13 => Some(ChSel::VddB),
103 14 => Some(ChSel::Vddio),
104 15 => Some(ChSel::Vddioh),
105 16 => Some(ChSel::VregI),
106 _ => None,
107 }
108 }
109 #[doc = "`0`"]
110 #[inline(always)]
111 pub fn is_ain0(&self) -> bool {
112 *self == ChSel::Ain0
113 }
114 #[doc = "`1`"]
115 #[inline(always)]
116 pub fn is_ain1(&self) -> bool {
117 *self == ChSel::Ain1
118 }
119 #[doc = "`10`"]
120 #[inline(always)]
121 pub fn is_ain2(&self) -> bool {
122 *self == ChSel::Ain2
123 }
124 #[doc = "`11`"]
125 #[inline(always)]
126 pub fn is_ain3(&self) -> bool {
127 *self == ChSel::Ain3
128 }
129 #[doc = "`100`"]
130 #[inline(always)]
131 pub fn is_ain4(&self) -> bool {
132 *self == ChSel::Ain4
133 }
134 #[doc = "`101`"]
135 #[inline(always)]
136 pub fn is_ain5(&self) -> bool {
137 *self == ChSel::Ain5
138 }
139 #[doc = "`110`"]
140 #[inline(always)]
141 pub fn is_ain6(&self) -> bool {
142 *self == ChSel::Ain6
143 }
144 #[doc = "`111`"]
145 #[inline(always)]
146 pub fn is_ain7(&self) -> bool {
147 *self == ChSel::Ain7
148 }
149 #[doc = "`1000`"]
150 #[inline(always)]
151 pub fn is_vcore_a(&self) -> bool {
152 *self == ChSel::VcoreA
153 }
154 #[doc = "`1001`"]
155 #[inline(always)]
156 pub fn is_vcore_b(&self) -> bool {
157 *self == ChSel::VcoreB
158 }
159 #[doc = "`1010`"]
160 #[inline(always)]
161 pub fn is_vrxout(&self) -> bool {
162 *self == ChSel::Vrxout
163 }
164 #[doc = "`1011`"]
165 #[inline(always)]
166 pub fn is_vtxout(&self) -> bool {
167 *self == ChSel::Vtxout
168 }
169 #[doc = "`1100`"]
170 #[inline(always)]
171 pub fn is_vdd_a(&self) -> bool {
172 *self == ChSel::VddA
173 }
174 #[doc = "VddB/4"]
175 #[inline(always)]
176 pub fn is_vdd_b(&self) -> bool {
177 *self == ChSel::VddB
178 }
179 #[doc = "Vddio/4"]
180 #[inline(always)]
181 pub fn is_vddio(&self) -> bool {
182 *self == ChSel::Vddio
183 }
184 #[doc = "Vddioh/4"]
185 #[inline(always)]
186 pub fn is_vddioh(&self) -> bool {
187 *self == ChSel::Vddioh
188 }
189 #[doc = "VregI/4"]
190 #[inline(always)]
191 pub fn is_vreg_i(&self) -> bool {
192 *self == ChSel::VregI
193 }
194}
195#[doc = "Field `ch_sel` writer - ADC Channel Select"]
196pub type ChSelW<'a, REG> = crate::FieldWriter<'a, REG, 5, ChSel>;
197impl<'a, REG> ChSelW<'a, REG>
198where
199 REG: crate::Writable + crate::RegisterSpec,
200 REG::Ux: From<u8>,
201{
202 #[doc = "`0`"]
203 #[inline(always)]
204 pub fn ain0(self) -> &'a mut crate::W<REG> {
205 self.variant(ChSel::Ain0)
206 }
207 #[doc = "`1`"]
208 #[inline(always)]
209 pub fn ain1(self) -> &'a mut crate::W<REG> {
210 self.variant(ChSel::Ain1)
211 }
212 #[doc = "`10`"]
213 #[inline(always)]
214 pub fn ain2(self) -> &'a mut crate::W<REG> {
215 self.variant(ChSel::Ain2)
216 }
217 #[doc = "`11`"]
218 #[inline(always)]
219 pub fn ain3(self) -> &'a mut crate::W<REG> {
220 self.variant(ChSel::Ain3)
221 }
222 #[doc = "`100`"]
223 #[inline(always)]
224 pub fn ain4(self) -> &'a mut crate::W<REG> {
225 self.variant(ChSel::Ain4)
226 }
227 #[doc = "`101`"]
228 #[inline(always)]
229 pub fn ain5(self) -> &'a mut crate::W<REG> {
230 self.variant(ChSel::Ain5)
231 }
232 #[doc = "`110`"]
233 #[inline(always)]
234 pub fn ain6(self) -> &'a mut crate::W<REG> {
235 self.variant(ChSel::Ain6)
236 }
237 #[doc = "`111`"]
238 #[inline(always)]
239 pub fn ain7(self) -> &'a mut crate::W<REG> {
240 self.variant(ChSel::Ain7)
241 }
242 #[doc = "`1000`"]
243 #[inline(always)]
244 pub fn vcore_a(self) -> &'a mut crate::W<REG> {
245 self.variant(ChSel::VcoreA)
246 }
247 #[doc = "`1001`"]
248 #[inline(always)]
249 pub fn vcore_b(self) -> &'a mut crate::W<REG> {
250 self.variant(ChSel::VcoreB)
251 }
252 #[doc = "`1010`"]
253 #[inline(always)]
254 pub fn vrxout(self) -> &'a mut crate::W<REG> {
255 self.variant(ChSel::Vrxout)
256 }
257 #[doc = "`1011`"]
258 #[inline(always)]
259 pub fn vtxout(self) -> &'a mut crate::W<REG> {
260 self.variant(ChSel::Vtxout)
261 }
262 #[doc = "`1100`"]
263 #[inline(always)]
264 pub fn vdd_a(self) -> &'a mut crate::W<REG> {
265 self.variant(ChSel::VddA)
266 }
267 #[doc = "VddB/4"]
268 #[inline(always)]
269 pub fn vdd_b(self) -> &'a mut crate::W<REG> {
270 self.variant(ChSel::VddB)
271 }
272 #[doc = "Vddio/4"]
273 #[inline(always)]
274 pub fn vddio(self) -> &'a mut crate::W<REG> {
275 self.variant(ChSel::Vddio)
276 }
277 #[doc = "Vddioh/4"]
278 #[inline(always)]
279 pub fn vddioh(self) -> &'a mut crate::W<REG> {
280 self.variant(ChSel::Vddioh)
281 }
282 #[doc = "VregI/4"]
283 #[inline(always)]
284 pub fn vreg_i(self) -> &'a mut crate::W<REG> {
285 self.variant(ChSel::VregI)
286 }
287}
288#[doc = "Scales the external inputs, all inputs are scaled the same\n\nValue on reset: 0"]
289#[derive(Clone, Copy, Debug, PartialEq, Eq)]
290#[repr(u8)]
291pub enum AdcDivsel {
292 #[doc = "0: `0`"]
293 Div1 = 0,
294 #[doc = "1: `1`"]
295 Div2 = 1,
296 #[doc = "2: `10`"]
297 Div3 = 2,
298 #[doc = "3: `11`"]
299 Div4 = 3,
300}
301impl From<AdcDivsel> for u8 {
302 #[inline(always)]
303 fn from(variant: AdcDivsel) -> Self {
304 variant as _
305 }
306}
307impl crate::FieldSpec for AdcDivsel {
308 type Ux = u8;
309}
310impl crate::IsEnum for AdcDivsel {}
311#[doc = "Field `adc_divsel` reader - Scales the external inputs, all inputs are scaled the same"]
312pub type AdcDivselR = crate::FieldReader<AdcDivsel>;
313impl AdcDivselR {
314 #[doc = "Get enumerated values variant"]
315 #[inline(always)]
316 pub const fn variant(&self) -> AdcDivsel {
317 match self.bits {
318 0 => AdcDivsel::Div1,
319 1 => AdcDivsel::Div2,
320 2 => AdcDivsel::Div3,
321 3 => AdcDivsel::Div4,
322 _ => unreachable!(),
323 }
324 }
325 #[doc = "`0`"]
326 #[inline(always)]
327 pub fn is_div1(&self) -> bool {
328 *self == AdcDivsel::Div1
329 }
330 #[doc = "`1`"]
331 #[inline(always)]
332 pub fn is_div2(&self) -> bool {
333 *self == AdcDivsel::Div2
334 }
335 #[doc = "`10`"]
336 #[inline(always)]
337 pub fn is_div3(&self) -> bool {
338 *self == AdcDivsel::Div3
339 }
340 #[doc = "`11`"]
341 #[inline(always)]
342 pub fn is_div4(&self) -> bool {
343 *self == AdcDivsel::Div4
344 }
345}
346#[doc = "Field `adc_divsel` writer - Scales the external inputs, all inputs are scaled the same"]
347pub type AdcDivselW<'a, REG> = crate::FieldWriter<'a, REG, 2, AdcDivsel, crate::Safe>;
348impl<'a, REG> AdcDivselW<'a, REG>
349where
350 REG: crate::Writable + crate::RegisterSpec,
351 REG::Ux: From<u8>,
352{
353 #[doc = "`0`"]
354 #[inline(always)]
355 pub fn div1(self) -> &'a mut crate::W<REG> {
356 self.variant(AdcDivsel::Div1)
357 }
358 #[doc = "`1`"]
359 #[inline(always)]
360 pub fn div2(self) -> &'a mut crate::W<REG> {
361 self.variant(AdcDivsel::Div2)
362 }
363 #[doc = "`10`"]
364 #[inline(always)]
365 pub fn div3(self) -> &'a mut crate::W<REG> {
366 self.variant(AdcDivsel::Div3)
367 }
368 #[doc = "`11`"]
369 #[inline(always)]
370 pub fn div4(self) -> &'a mut crate::W<REG> {
371 self.variant(AdcDivsel::Div4)
372 }
373}
374#[doc = "Field `data_align` reader - ADC Data Alignment Select"]
375pub type DataAlignR = crate::BitReader;
376#[doc = "Field `data_align` writer - ADC Data Alignment Select"]
377pub type DataAlignW<'a, REG> = crate::BitWriter<'a, REG>;
378impl R {
379 #[doc = "Bit 0 - Start ADC Conversion"]
380 #[inline(always)]
381 pub fn start(&self) -> StartR {
382 StartR::new((self.bits & 1) != 0)
383 }
384 #[doc = "Bit 1 - ADC Power Up"]
385 #[inline(always)]
386 pub fn pwr(&self) -> PwrR {
387 PwrR::new(((self.bits >> 1) & 1) != 0)
388 }
389 #[doc = "Bit 3 - ADC Reference Buffer Power Up"]
390 #[inline(always)]
391 pub fn refbuf_pwr(&self) -> RefbufPwrR {
392 RefbufPwrR::new(((self.bits >> 3) & 1) != 0)
393 }
394 #[doc = "Bit 4 - ADC Reference Select"]
395 #[inline(always)]
396 pub fn ref_sel(&self) -> RefSelR {
397 RefSelR::new(((self.bits >> 4) & 1) != 0)
398 }
399 #[doc = "Bit 8 - ADC Reference Scale"]
400 #[inline(always)]
401 pub fn ref_scale(&self) -> RefScaleR {
402 RefScaleR::new(((self.bits >> 8) & 1) != 0)
403 }
404 #[doc = "Bit 9 - ADC Scale"]
405 #[inline(always)]
406 pub fn scale(&self) -> ScaleR {
407 ScaleR::new(((self.bits >> 9) & 1) != 0)
408 }
409 #[doc = "Bit 11 - ADC Clock Enable"]
410 #[inline(always)]
411 pub fn clk_en(&self) -> ClkEnR {
412 ClkEnR::new(((self.bits >> 11) & 1) != 0)
413 }
414 #[doc = "Bits 12:16 - ADC Channel Select"]
415 #[inline(always)]
416 pub fn ch_sel(&self) -> ChSelR {
417 ChSelR::new(((self.bits >> 12) & 0x1f) as u8)
418 }
419 #[doc = "Bits 17:18 - Scales the external inputs, all inputs are scaled the same"]
420 #[inline(always)]
421 pub fn adc_divsel(&self) -> AdcDivselR {
422 AdcDivselR::new(((self.bits >> 17) & 3) as u8)
423 }
424 #[doc = "Bit 20 - ADC Data Alignment Select"]
425 #[inline(always)]
426 pub fn data_align(&self) -> DataAlignR {
427 DataAlignR::new(((self.bits >> 20) & 1) != 0)
428 }
429}
430impl W {
431 #[doc = "Bit 0 - Start ADC Conversion"]
432 #[inline(always)]
433 pub fn start(&mut self) -> StartW<CtrlSpec> {
434 StartW::new(self, 0)
435 }
436 #[doc = "Bit 1 - ADC Power Up"]
437 #[inline(always)]
438 pub fn pwr(&mut self) -> PwrW<CtrlSpec> {
439 PwrW::new(self, 1)
440 }
441 #[doc = "Bit 3 - ADC Reference Buffer Power Up"]
442 #[inline(always)]
443 pub fn refbuf_pwr(&mut self) -> RefbufPwrW<CtrlSpec> {
444 RefbufPwrW::new(self, 3)
445 }
446 #[doc = "Bit 4 - ADC Reference Select"]
447 #[inline(always)]
448 pub fn ref_sel(&mut self) -> RefSelW<CtrlSpec> {
449 RefSelW::new(self, 4)
450 }
451 #[doc = "Bit 8 - ADC Reference Scale"]
452 #[inline(always)]
453 pub fn ref_scale(&mut self) -> RefScaleW<CtrlSpec> {
454 RefScaleW::new(self, 8)
455 }
456 #[doc = "Bit 9 - ADC Scale"]
457 #[inline(always)]
458 pub fn scale(&mut self) -> ScaleW<CtrlSpec> {
459 ScaleW::new(self, 9)
460 }
461 #[doc = "Bit 11 - ADC Clock Enable"]
462 #[inline(always)]
463 pub fn clk_en(&mut self) -> ClkEnW<CtrlSpec> {
464 ClkEnW::new(self, 11)
465 }
466 #[doc = "Bits 12:16 - ADC Channel Select"]
467 #[inline(always)]
468 pub fn ch_sel(&mut self) -> ChSelW<CtrlSpec> {
469 ChSelW::new(self, 12)
470 }
471 #[doc = "Bits 17:18 - Scales the external inputs, all inputs are scaled the same"]
472 #[inline(always)]
473 pub fn adc_divsel(&mut self) -> AdcDivselW<CtrlSpec> {
474 AdcDivselW::new(self, 17)
475 }
476 #[doc = "Bit 20 - ADC Data Alignment Select"]
477 #[inline(always)]
478 pub fn data_align(&mut self) -> DataAlignW<CtrlSpec> {
479 DataAlignW::new(self, 20)
480 }
481}
482#[doc = "ADC Control\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
483pub struct CtrlSpec;
484impl crate::RegisterSpec for CtrlSpec {
485 type Ux = u32;
486}
487#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
488impl crate::Readable for CtrlSpec {}
489#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
490impl crate::Writable for CtrlSpec {
491 type Safety = crate::Unsafe;
492 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
493 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
494}
495#[doc = "`reset()` method sets CTRL to value 0"]
496impl crate::Resettable for CtrlSpec {
497 const RESET_VALUE: u32 = 0;
498}