Expand description
Peripheral access API for MAX78000 microcontrollers (generated using svd2rust v0.35.0 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.
Re-exports§
pub use self::gpio0 as gpio1;pub use self::gpio0 as gpio2;pub use self::i2c0 as i2c1;pub use self::i2c0 as i2c2;pub use self::pt0 as pt1;pub use self::pt0 as pt2;pub use self::pt0 as pt3;pub use self::spi0 as spi1;pub use self::tmr0 as tmr1;pub use self::tmr0 as tmr2;pub use self::tmr0 as tmr3;pub use self::tmr0 as tmr4;pub use self::tmr0 as tmr5;pub use self::uart0 as uart1;pub use self::uart0 as uart2;pub use self::uart0 as uart3;pub use self::wdt0 as wdt1;
Modules§
- adc
- 10-bit Analog to Digital Converter
- aes
- AES Keys.
- aeskeys
- AES Key Registers.
- cameraif
- Parallel Camera Interface.
- crc
- CRC Registers.
- dma
- DMA Controller Fully programmable, chaining capable DMA channels.
- dvs
- Dynamic Voltage Scaling
- fcr
- Function Control Register.
- flc
- Flash Memory Control.
- gcfr
- Global Control Function Register.
- gcr
- Global Control Registers.
- generic
- Common register and bit access and modify traits
- gpio0
- Individual I/O for each GPIO
- i2c0
- Inter-Integrated Circuit.
- i2s
- Inter-IC Sound Interface.
- icc0
- Instruction Cache Controller Registers
- lpcmp
- Low Power Comparator
- lpgcr
- Low Power Global Control.
- mcr
- Misc Control.
- owm
- 1-Wire Master Interface.
- pt0
- Pulse Train
- ptg
- Pulse Train Generation
- pwrseq
- Power Sequencer / Low Power Control Register.
- rtc
- Real Time Clock and Alarm.
- sema
- The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain.
- simo
- Single Inductor Multiple Output Switching Converter
- sir
- System Initialization Registers.
- spi0
- SPI peripheral.
- tmr0
- Low-Power Configurable Timer
- trimsir
- Trim System Initilazation Registers
- trng
- Random Number Generator.
- uart0
- UART Low Power Registers
- wdt0
- Windowed Watchdog Timer
- wut
- 32-bit reloadable timer that can be used for timing and wakeup.
Structs§
- Adc
- 10-bit Analog to Digital Converter
- Aes
- AES Keys.
- Aeskeys
- AES Key Registers.
- CBP
- Cache and branch predictor maintenance operations
- CPUID
- CPUID
- Cameraif
- Parallel Camera Interface.
- Core
Peripherals - Core peripherals
- Crc
- CRC Registers.
- DCB
- Debug Control Block
- DWT
- Data Watchpoint and Trace unit
- Dma
- DMA Controller Fully programmable, chaining capable DMA channels.
- Dvs
- Dynamic Voltage Scaling
- FPB
- Flash Patch and Breakpoint unit
- FPU
- Floating Point Unit
- Fcr
- Function Control Register.
- Flc
- Flash Memory Control.
- Gcfr
- Global Control Function Register.
- Gcr
- Global Control Registers.
- Gpio0
- Individual I/O for each GPIO
- Gpio1
- Individual I/O for each GPIO 1
- Gpio2
- Individual I/O for each GPIO 2
- I2c0
- Inter-Integrated Circuit.
- I2c1
- Inter-Integrated Circuit. 1
- I2c2
- Inter-Integrated Circuit. 2
- I2s
- Inter-IC Sound Interface.
- ITM
- Instrumentation Trace Macrocell
- Icc0
- Instruction Cache Controller Registers
- Lpcmp
- Low Power Comparator
- Lpgcr
- Low Power Global Control.
- MPU
- Memory Protection Unit
- Mcr
- Misc Control.
- NVIC
- Nested Vector Interrupt Controller
- Owm
- 1-Wire Master Interface.
- Peripherals
- All the peripherals.
- Pt0
- Pulse Train
- Pt1
- Pulse Train 1
- Pt2
- Pulse Train 2
- Pt3
- Pulse Train 3
- Ptg
- Pulse Train Generation
- Pwrseq
- Power Sequencer / Low Power Control Register.
- Rtc
- Real Time Clock and Alarm.
- SCB
- System Control Block
- SYST
- SysTick: System Timer
- Sema
- The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain.
- Simo
- Single Inductor Multiple Output Switching Converter
- Sir
- System Initialization Registers.
- Spi0
- SPI peripheral.
- Spi1
- SPI peripheral. 1
- TPIU
- Trace Port Interface Unit
- Tmr0
- Low-Power Configurable Timer
- Tmr1
- Low-Power Configurable Timer 1
- Tmr2
- Low-Power Configurable Timer 2
- Tmr3
- Low-Power Configurable Timer 3
- Tmr4
- Low-Power Configurable Timer 4
- Tmr5
- Low-Power Configurable Timer 5
- Trimsir
- Trim System Initilazation Registers
- Trng
- Random Number Generator.
- Uart0
- UART Low Power Registers
- Uart1
- UART Low Power Registers 1
- Uart2
- UART Low Power Registers 2
- Uart3
- UART Low Power Registers 3
- Wdt0
- Windowed Watchdog Timer
- Wdt1
- Windowed Watchdog Timer 1
- Wut
- 32-bit reloadable timer that can be used for timing and wakeup.
Enums§
- Interrupt
- Enumeration of all the interrupts.
Constants§
- NVIC_
PRIO_ BITS - Number available in the NVIC for configuring priority