max32660_pac/
dma.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    #[doc = "0x00 - DMA Control Register."]
5    pub int_en: crate::Reg<int_en::INT_EN_SPEC>,
6    #[doc = "0x04 - DMA Interrupt Register."]
7    pub int_fl: crate::Reg<int_fl::INT_FL_SPEC>,
8    _reserved2: [u8; 0xf8],
9    #[doc = "0x100..0x180 - DMA Channel registers."]
10    pub ch: [CH; 4],
11}
12#[doc = r"Register block"]
13#[repr(C)]
14pub struct CH {
15    #[doc = "0x00 - DMA Channel Configuration Register."]
16    pub cfg: crate::Reg<self::ch::cfg::CFG_SPEC>,
17    #[doc = "0x04 - DMA Channel Status Register."]
18    pub stat: crate::Reg<self::ch::stat::STAT_SPEC>,
19    #[doc = "0x08 - Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD."]
20    pub src: crate::Reg<self::ch::src::SRC_SPEC>,
21    #[doc = "0x0c - Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD."]
22    pub dst: crate::Reg<self::ch::dst::DST_SPEC>,
23    #[doc = "0x10 - DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered."]
24    pub cnt: crate::Reg<self::ch::cnt::CNT_SPEC>,
25    #[doc = "0x14 - Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition."]
26    pub src_rld: crate::Reg<self::ch::src_rld::SRC_RLD_SPEC>,
27    #[doc = "0x18 - Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition."]
28    pub dst_rld: crate::Reg<self::ch::dst_rld::DST_RLD_SPEC>,
29    #[doc = "0x1c - DMA Channel Count Reload Register."]
30    pub cnt_rld: crate::Reg<self::ch::cnt_rld::CNT_RLD_SPEC>,
31}
32#[doc = r"Register block"]
33#[doc = "DMA Channel registers."]
34pub mod ch;
35#[doc = "INT_EN register accessor: an alias for `Reg<INT_EN_SPEC>`"]
36pub type INT_EN = crate::Reg<int_en::INT_EN_SPEC>;
37#[doc = "DMA Control Register."]
38pub mod int_en;
39#[doc = "INT_FL register accessor: an alias for `Reg<INT_FL_SPEC>`"]
40pub type INT_FL = crate::Reg<int_fl::INT_FL_SPEC>;
41#[doc = "DMA Interrupt Register."]
42pub mod int_fl;
max32660_pac/dma.rs

max32660_pac/
dma.rs
